CN112885881B - Display panel, manufacturing method thereof and display device - Google Patents
Display panel, manufacturing method thereof and display device Download PDFInfo
- Publication number
- CN112885881B CN112885881B CN202110082454.8A CN202110082454A CN112885881B CN 112885881 B CN112885881 B CN 112885881B CN 202110082454 A CN202110082454 A CN 202110082454A CN 112885881 B CN112885881 B CN 112885881B
- Authority
- CN
- China
- Prior art keywords
- layer
- electrode
- capacitor plate
- capacitor
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000003990 capacitor Substances 0.000 claims abstract description 233
- 239000002184 metal Substances 0.000 claims abstract description 89
- 238000000034 method Methods 0.000 claims description 30
- 238000003860 storage Methods 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000010408 film Substances 0.000 description 23
- 230000009286 beneficial effect Effects 0.000 description 21
- 230000008569 process Effects 0.000 description 20
- 238000010586 diagram Methods 0.000 description 12
- 239000010409 thin film Substances 0.000 description 10
- 238000004458 analytical method Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003090 exacerbative effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the invention discloses a display panel, a manufacturing method thereof and a display device. The display panel includes: the array circuit layer comprises a plurality of metal layers and a plurality of insulating layers, and the insulating layers are arranged between two adjacent metal layers; one of the metal layers is provided with a first capacitor plate; the light-emitting device layer comprises a first electrode layer, and the first electrode layer is provided with a second capacitance pole plate; at least one insulating layer is arranged between the first capacitor plate and the second capacitor plate, and the first capacitor plate and the second capacitor plate form a capacitor. Compared with the prior art, the embodiment of the invention improves the mura problem and the display uniformity of the display panel and improves the display image quality.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel, a manufacturing method thereof and a display device.
Background
Along with the continuous development of display technology, the application range of the display panel is wider and wider, and the requirements of people on the display panel are also higher and higher. Particularly, the display image quality of the display panel is always one of important indicators for quality measurement of the display panel by consumers and panel manufacturers. However, the conventional display panel has serious mura problem and poor display uniformity at low gray level, which affects the improvement of the display quality of the display panel.
Disclosure of Invention
The embodiment of the invention provides a display panel, a manufacturing method thereof and a display device, which are used for improving the mura problem and the display uniformity of the display panel and improving the display image quality.
In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:
a display panel, comprising:
the array circuit layer comprises a plurality of metal layers and a plurality of insulating layers, and the insulating layers are arranged between two adjacent metal layers; one of the metal layers is provided with a first capacitor plate;
the light-emitting device comprises a light-emitting device layer, wherein the light-emitting device layer comprises a first electrode layer, and the first electrode layer is provided with a second capacitance polar plate; at least one insulating layer is arranged between the first capacitor plate and the second capacitor plate, and the first capacitor plate and the second capacitor plate form a capacitor.
Optionally, the light emitting device layer further includes a pixel defining layer, a light emitting layer, and a second electrode layer, the pixel defining layer being located between the first electrode layer and the second electrode layer, and the pixel defining layer including a first opening, the first opening accommodating the light emitting layer;
wherein the first electrode layer is further provided with a first electrode, and the second electrode layer is provided with a second electrode; the first electrode layer is positioned on one side close to the array circuit layer; alternatively, the second electrode layer is located on a side close to the array circuit layer.
Optionally, the material of the second capacitor plate is the same as the material of the first electrode; alternatively, the material of the second capacitor plate is the same as the material of the first capacitor plate.
Optionally, the array circuit layer further includes an active layer, and the active layer is disposed between two adjacent insulating layers; the metal layer comprises a first metal layer, a second metal layer and a third metal layer; the first metal layer is provided with a grid electrode, and the third metal layer is provided with a source electrode and a drain electrode; the active layer, the gate electrode, the source electrode, and the drain electrode constitute a transistor;
the first capacitor plate is arranged on the first metal layer, the second metal layer or the third metal layer.
Optionally, the capacitor is a storage capacitor in the pixel circuit, the first capacitor plate is electrically connected with a gate of the driving transistor in the pixel circuit, and the second capacitor plate is electrically connected with a fixed potential line.
Optionally, the fixed potential line is wound by an edge of the display panel;
the second capacitor polar plate is electrically connected with the fixed potential line through a conductive connecting wire; wherein the conductive connection line and the second capacitor plate are arranged on the same layer.
Optionally, the pixel circuit includes at least one of a first power line, a second power line, and a reference voltage line; wherein, the first power line and part of the wires of the reference voltage line are positioned on the array circuit layer; part of the wiring of the second power line is positioned on the light-emitting device layer;
the first power line is multiplexed into the fixed potential line; alternatively, the reference voltage line is multiplexed to the fixed potential line;
the second capacitor plate is electrically connected with the fixed potential line through an insulating layer via hole in the array circuit layer.
Optionally, the light emitting device layer further includes a pixel defining layer, a light emitting layer, and a second electrode layer, the pixel defining layer being located between the first electrode layer and the second electrode layer; the first electrode layer is also provided with a first electrode, and the pixel circuit is electrically connected with the first electrode; the second electrode layer is provided with a second electrode, and the second power line transmits voltage to the second electrode; the second power line is multiplexed into the fixed potential line;
wherein the pixel defining layer includes a first opening corresponding to the first electrode and accommodating the light emitting layer, and a second opening; the second opening corresponds to the second capacitor plate, and the second capacitor plate is electrically connected with the second electrode through the second opening.
Correspondingly, the embodiment of the invention also provides a display device, which comprises: the display panel according to any embodiment of the present invention.
Correspondingly, the embodiment of the invention also provides a manufacturing method of the display panel, which can be applied to the display panel provided by any embodiment of the invention, and the manufacturing method of the display panel comprises the following steps:
manufacturing an array circuit layer on a substrate; the array circuit layer comprises a plurality of metal layers and a plurality of insulating layers, and the insulating layers are arranged between two adjacent metal layers; one of the metal layers is provided with a first capacitor plate;
manufacturing a light emitting device layer on the array circuit layer; the light-emitting device layer comprises a first electrode layer, and the first electrode layer is provided with a second capacitance pole plate; at least one insulating layer is arranged between the first capacitor plate and the second capacitor plate, and the first capacitor plate and the second capacitor plate form a capacitor.
Optionally, fabricating a light emitting device layer on the array circuit layer, including:
manufacturing a first electrode layer on the array circuit layer, and patterning the first electrode layer to form a first electrode and the second capacitor plate;
manufacturing a pixel definition layer on the first electrode layer, and patterning the pixel definition layer to form a first opening and a second opening; wherein the first opening exposes the first electrode and the second opening exposes the second capacitive plate;
manufacturing a light-emitting layer in the first opening;
and manufacturing a second electrode layer in the second opening and on the light-emitting layer so that the second capacitor plate is electrically connected with the second electrode through the second opening.
In the embodiment of the invention, the first capacitor electrode plate is arranged in the array circuit layer, and the second capacitor electrode plate is arranged in the light-emitting device layer, so that a planarization layer with thicker film layer thickness is arranged between the array circuit layer and the light-emitting device layer. That is, the embodiment of the invention skillfully utilizes the thicker film layer in the display panel as the dielectric layer of the capacitor, and the arrangement can at least realize the following beneficial effects:
compared with the prior art, the embodiment of the invention increases the distance between the first capacitor plate and the second capacitor plate, thereby being beneficial to reducing the capacitance of the capacitor on the basis of not reducing the opposite area of the capacitor plate and being beneficial to being applied to the display panel with high refresh frequency.
In the second aspect, compared with the prior art, the embodiment of the invention increases the distance between the first capacitor plate and the second capacitor plate, so that the capacitor of the embodiment of the invention has relatively smaller fluctuation under the process fluctuation of the same film thickness, the tolerance of the capacitor to the process fluctuation of the film thickness is higher, and the stability of the capacitor is improved.
In the third aspect, compared with the prior art, the embodiment of the invention increases the distance between the first capacitor plate and the second capacitor plate, and can increase the line widths of the first capacitor plate and the second capacitor plate when the same capacitance is provided, so that the capacitance fluctuation of the embodiment of the invention is relatively smaller under the same line width process fluctuation, the tolerance of the capacitance to the line width process fluctuation is higher, and the stability of the capacitance is improved.
In summary, the embodiment of the invention improves the stability of the capacitor, thereby being beneficial to improving the stability of the pixel circuit and leading the uniformity of the driving current generated between different pixel circuits on the display panel to be better; further, the mura problem of the display panel is improved, and the display uniformity is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional pixel circuit;
FIG. 2 is a schematic cross-sectional view of a conventional display panel;
fig. 3 is a schematic cross-sectional structure of a display panel according to an embodiment of the invention;
FIG. 4 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;
FIG. 5 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;
fig. 6 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention;
fig. 7 is a schematic top view of a display panel according to an embodiment of the invention;
FIG. 8 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;
FIG. 9 is a schematic circuit diagram of another pixel circuit according to an embodiment of the present invention;
fig. 10 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;
FIG. 11 is a schematic diagram of a simulation waveform of a pixel circuit according to an embodiment of the present invention;
fig. 12 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram of a manufacturing method of another display panel according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
As described in the background art, the existing display panel has the problems of serious mura problem and poor uniformity at low gray scale. In the prior art, the pixel circuit is improved by adopting a mode of compensating the driving transistor, and the inventor researches and discovers that the problems are also caused by larger fluctuation and poorer uniformity of the storage capacitor, and the specific analysis is as follows:
fig. 1 is a circuit schematic diagram of a conventional pixel circuit. Referring to fig. 1, the pixel circuit is a 2T1C pixel circuit, and specifically includes a driving transistor DTFT, a switching transistor STFT, and a storage capacitor Cst. The Scan signal Scan controls the switching transistor STFT to be turned on to write the data signal Vdata to the gate G of the driving transistor DTFT. The driving transistor DTFT generates a driving current driven by the gate-source voltage thereof, and the driving current is outputted to the light emitting device OLED via the drain electrode of the driving transistor DTFT to drive the light emitting device OLED to emit light. The storage capacitor Cst is connected between the gate G and the source S of the driving transistor DTFT, and is used for maintaining a gate-source voltage difference of the driving transistor DTFT, and maintaining the light emitting device OLED to emit light stably. Therefore, when there is a fluctuation in the storage capacitance Cst, the display panel has problems of mura and poor uniformity. Particularly, at low gray scale, the electric quantity stored by the storage capacitor Cst is small, the mura is more serious due to fluctuation of the storage capacitor Cst, and the mura and uniformity problems are more obvious.
The inventor further researches and discovers that in layout design, the fluctuation of the storage capacitor Cst is related to factors such as the line width, the film thickness and the like of the storage capacitor Cst, and the specific analysis is as follows:
fig. 2 is a schematic cross-sectional structure of a conventional display panel. Referring to fig. 2, the thin film transistor TFT is a driving transistor, and the capacitor C is a storage capacitor. The grid electrode G of the thin film transistor TFT and the first capacitance electrode plate 1A0 of the capacitor C are both positioned on the first metal layer, the second capacitance electrode plate 1B0 of the capacitor C is positioned on the second metal layer, and the source electrode S and the drain electrode D of the thin film transistor TFT are both positioned on the third metal layer. The anode 210 of the light emitting device OLED is connected to the drain D of the thin film transistor TFT, and the cathode 240 of the light emitting device OLED is a common electrode. Only one insulating layer 150 is disposed between the first capacitor plate 1A0 and the second capacitor plate 1B 0. The thickness of the insulating layer 150 is thin, and uniformity of film thickness of the insulating layer 150 is poor due to process fluctuation or the like, resulting in fluctuation of the capacitance C. In addition, the line width uniformity of the first and second capacitor plates 1A0 and 1B0 is poor due to process fluctuation or the like, thereby exacerbating the fluctuation of the capacitance C.
As the proportion of games occupied in the lives of people is larger and larger (especially mobile games), the demands of people for mobile phones to be multifunctional are also higher and higher, and display panels with high refresh frequencies are also generated. At high refresh frequencies, the capacitance C needs to be reduced to further reduce the linewidth, while the smaller the linewidth, the less tolerant to process fluctuations. Therefore, the relative fluctuation of the capacitance C of the display panel with a high refresh frequency is larger, resulting in more serious mura problem and more obvious uniformity problem.
In view of the above, the embodiment of the invention provides a display panel. Fig. 3 is a schematic cross-sectional structure of a display panel according to an embodiment of the invention. Referring to fig. 3, the display panel includes: an array circuit layer 100 and a light emitting device layer 200. The array circuit layer 100 includes a plurality of metal layers and a plurality of insulating layers, and an insulating layer is disposed between two adjacent metal layers. The metal layer is a film layer provided with a metal pattern, for example, a metal layer provided with a gate electrode G, a metal layer provided with a source electrode S and a drain electrode D, or the like. The insulating layer refers to a film layer for performing an insulating function between metal layers, such as the insulating layer 120, the insulating layer 130, the insulating layer 140, the insulating layer 150, the insulating layer 160, the insulating layer 170, the insulating layer 180, and the like. One of the metal layers is provided with a first capacitor plate 1A0, and the first capacitor plate 1A0 and the gate G are located on the same metal layer. The light emitting device layer 200 includes a first electrode layer, which refers to a film layer in which a conductive pattern is disposed in the light emitting device layer 200. The first electrode layer is provided with a second capacitor plate 260; at least one insulating layer is arranged between the first capacitor plate 1A0 and the second capacitor plate 260, and the first capacitor plate 1A0 and the second capacitor plate 260 form a capacitor C.
The first capacitor plate 1A0 is located in the array circuit layer 100, and the second capacitor plate 260 is located in the light emitting device layer 200, so that a planarization layer with a thicker film layer thickness is disposed between the array circuit layer 100 and the light emitting device layer 200. That is, the embodiment of the invention skillfully utilizes the thicker film layer in the display panel as the dielectric layer of the capacitor C, and the arrangement can at least realize the following beneficial effects:
in the first aspect, compared with the prior art, the embodiment of the invention increases the distance between the first capacitor plate 1A0 and the second capacitor plate 260, thereby being beneficial to reducing the capacitance of the capacitor C on the basis of not reducing the facing area of the capacitor plates and being beneficial to being applied to the display panel with high refresh frequency.
In the second aspect, compared with the prior art, the distance between the first capacitor plate 1A0 and the second capacitor plate 260 is increased, so that the capacitor C of the embodiment of the invention has relatively smaller fluctuation under the same film thickness process fluctuation, so that the tolerance of the capacitor C to the film thickness process fluctuation is higher, and the stability of the capacitor C is improved.
In the third aspect, compared with the prior art, the distance between the first capacitor plate 1A0 and the second capacitor plate 260 is increased, and when the same capacitance is provided, the line widths of the first capacitor plate 1A0 and the second capacitor plate 260 can be increased, so that the fluctuation of the capacitor C in the embodiment of the invention is relatively smaller under the same line width process fluctuation, so that the tolerance of the capacitor C to the line width process fluctuation is higher, and the stability of the capacitor C is improved.
In summary, the embodiment of the invention improves the stability of the capacitor C, thereby being beneficial to improving the stability of the pixel circuit, and ensuring that the uniformity of the driving current generated between different pixel circuits on the display panel is better; further, the mura problem of the display panel is improved, and the display uniformity is improved.
In the above-described embodiments, the first capacitor plate 1A0 and the second capacitor plate 260 are disposed in the light emitting device layer 200 in various manners, and several of them are described below, but the present invention is not limited thereto.
With continued reference to fig. 3, in one embodiment of the present invention, the light emitting device layer 200 optionally further includes a pixel defining layer 220, a light emitting layer 230, and a second electrode layer, the pixel defining layer 220 is located between the first electrode layer and the second electrode layer, and the pixel defining layer 220 includes a first opening 201, the first opening 201 accommodating the light emitting layer 230.
The first electrode layer is further provided with a first electrode, and the second electrode layer is provided with a second electrode, that is, the second capacitor plate 260 and the first electrode are arranged in the same layer. And the first electrode layer is positioned at a side close to the array circuit layer 100, i.e., the first electrode is connected to the thin film transistor TFT in the pixel circuit. Illustratively, the first electrode is an anode 210, the second capacitive plate 260 is disposed in the same layer as the anode 210, the first electrode layer is an anode layer, and the second capacitive plate 260 may be referred to as a virtual anode. Accordingly, the second electrode layer is located at a side far from the array circuit layer 100, the second electrode is the cathode 240, and the second electrode layer is the cathode layer. The second capacitor plate 260 and the first electrode are arranged on the same layer, so that the thickness of the display panel can be further kept from increasing on the basis of realizing the beneficial effects.
Optionally, the material of the second capacitor plate 260 is the same as the material of the first capacitor plate 1A0, which is advantageous to make the conductive properties of the second capacitor plate 260 the same as the conductive properties of the first capacitor plate 1A0. Compared with a capacitor plate with poor conductivity, the method is beneficial to improving the charge and discharge speed of the capacitor C so as to improve the response speed of the pixel circuit, thereby being beneficial to improving the refresh frequency of the display panel.
Optionally, the material of the second capacitor plate 260 is the same as the material of the anode 210, so that the second capacitor plate 260 and the anode 210 are formed in the same process step to simplify the process cost.
Fig. 4 is a schematic cross-sectional structure of another display panel according to an embodiment of the invention. Referring to fig. 4, in one embodiment of the present invention, optionally, a second electrode layer is disposed on a side close to the array circuit layer 100, that is, the second electrode is connected to the thin film transistor TFT in the pixel circuit, and the second electrode is the anode 210. Correspondingly, the first electrode layer is located at a side far away from the array circuit layer 100, the first electrode is a cathode 240, the first electrode layer is a cathode layer, the second capacitor plate 260 is disposed on the same layer as the cathode 240, the second capacitor plate 260 may be referred to as a virtual cathode 240, and the second electrode layer is an anode layer. The second capacitor plate 260 and the first electrode are arranged on the same layer, so that the thickness of the display panel can be further kept from increasing on the basis of realizing the beneficial effects.
Optionally, the material of the second capacitor plate 260 is the same as the material of the cathode 240, so that the second capacitor plate 260 and the cathode 240 can be formed in the same process step to simplify the process cost.
With continued reference to fig. 3 and 4, in one embodiment of the present invention, the array circuit layer 100 optionally further includes an active layer 190, the active layer 190 being disposed between two adjacent insulating layers, and the active layer 190 being disposed between the insulating layer 130 and the insulating layer 140, for example. The metal layer comprises a first metal layer, a second metal layer and a third metal layer; the first metal layer is provided with a grid G, and the third metal layer is provided with a source electrode S and a drain electrode D; the active layer 190, the gate electrode G, the source electrode S, the drain electrode D, and insulating layers therebetween constitute a thin film transistor TFT. The first capacitor plate 1A0 may be disposed on any one of the first metal layer, the second metal layer, or the third metal layer.
The first capacitor plate 1A0 is exemplarily shown in fig. 3 and 4 to be located in the first metal layer and is disposed in the same layer as the gate G. Specifically, in fig. 3, the first capacitor plate 1A0 is disposed in the same layer as the gate G, the second capacitor plate 260 is disposed in the same layer as the anode 210, and the dielectric layers between the first capacitor plate 1A0 and the second capacitor plate 260 are the insulating layer 150, the insulating layer 160, the insulating layer 170, and the insulating layer 180. In fig. 4, the first capacitor plate 1A0 is disposed in the same layer as the gate G, the second capacitor plate 260 is disposed in the same layer as the cathode 240, and the dielectric layers between the first capacitor plate 1A0 and the second capacitor plate 260 are the insulating layer 150, the insulating layer 160, the insulating layer 170, the insulating layer 180, and the pixel defining layer 220. Compared with the technical scheme shown in fig. 3, the dielectric layer of the capacitor C in fig. 4 is thicker, and can be applied to the application occasion with smaller capacitance to be set; correspondingly, the technical scheme in fig. 3 can be applied to occasions needing to set larger capacitance.
Fig. 5 is a schematic cross-sectional view of another display panel according to an embodiment of the invention. Referring to fig. 5, illustratively, the first capacitor plate 1A0 is disposed on a second metal layer, the second capacitor plate 260 is disposed on the same layer as the anode 210, and the dielectric layers between the first capacitor plate 1A0 and the second capacitor plate 260 are an insulating layer 160, an insulating layer 170, and an insulating layer 180.
Optionally, the first capacitor plate 1A0 is disposed on the third metal layer, the second capacitor plate 260 is disposed on the same layer as the anode 210, and the dielectric layer between the first capacitor plate 1A0 and the second capacitor plate 260 is the insulating layer 180.
In each of the above embodiments, optionally, the second metal layer is further provided with metal wires such as a data line, a scan line, a power signal line, and the like. In the prior art, since the second capacitor plate 260 is disposed on the second metal layer, in order to achieve reasonable utilization of layout space, the second metal layer is further provided with metal wires such as data lines, scan lines, and power signal lines. In an embodiment of the present invention, although the second metal layer is not provided with the second capacitor plate 260, other metal wires of the second metal layer may be still reserved, and only the positions of the first capacitor plate 1A0 and the second capacitor plate 260 are adjusted, which is beneficial to simplifying the difficulty of re-designing the layout of the display panel. In other embodiments, the display panel may further be provided to include only the first metal layer and the third metal layer to reduce the thickness of the display panel.
In the above embodiments, two insulating layers, namely, the insulating layer 160 and the insulating layer 170 are exemplarily shown to be disposed between the second metal layer and the third metal layer, but the present invention is not limited thereto, and in other embodiments, an insulating layer may be disposed between the second metal layer and the third metal layer.
The film layer positions of the first capacitor plate 1A0 and the second capacitor plate 260 are exemplarily described in the above embodiments, and a signal connection manner of the capacitor C is described below in connection with the pixel circuit.
Fig. 6 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 6, the pixel circuit includes seven thin film transistors and one capacitor. Specifically, the first transistor M1 is a driving transistor, and the other transistors are switching transistors. The gate of the second transistor M2 is electrically connected to the emission control line EM, and the source and drain of the second transistor M2 are connected to the first power line VDD and the source S of the first transistor M1, respectively. The gate of the third transistor M3 is electrically connected to the second scan line S2, and the source and the drain of the third transistor M3 are respectively connected to the drain D and the gate G of the first transistor M1. The gate of the fourth transistor M4 is electrically connected to the first scan line S1, and the source and drain of the fourth transistor M4 are connected to the reference voltage line Vref and the gate G of the first transistor M1, respectively. The gate of the fifth transistor M5 is electrically connected to the second scan line S2, and the source and the drain of the fifth transistor M5 are connected to the DATA line DATA and the source S of the first transistor M1, respectively. The gate of the sixth transistor M6 is electrically connected to the emission control line EM, and the source and drain of the sixth transistor M6 are connected to the drain D of the first transistor M1 and the anode of the light emitting device OLED, respectively. The gate of the seventh transistor M7 is electrically connected to the second scan line S2, and the source and drain of the seventh transistor M7 are connected to the reference voltage line Vref and the anode of the light emitting device OLED, respectively. The cathode of the light emitting device OLED is connected to the second power line VSS, i.e., the second power line VSS directly transfers voltage to the light emitting device OLED.
The second transistor M2 and the sixth transistor M6 are transistors that function as light emission control, the third transistor M3 and the fifth transistor M5 are transistors that function as data writing and threshold voltage compensation, the fourth transistor M4 is a transistor that functions as gate initialization, and the seventh transistor M7 is a transistor that functions as anode initialization.
The pixel circuit further includes a storage capacitor Cst connected between the gate electrode G of the first transistor M1 and a fixed potential line (the fixed potential line is the first power supply line VDD in fig. 6, for example). The storage capacitor Cst functions to maintain the gate-source voltage difference of the first transistor M1 unchanged.
With continued reference to fig. 6, in an embodiment, optionally, the capacitor provided by the embodiment of the present invention is a storage capacitor Cst in the pixel circuit, the first capacitor plate is electrically connected to the gate of the first transistor M1 in the pixel circuit, and the second capacitor plate is electrically connected to the fixed potential line. The first power line VDD is multiplexed as a fixed potential line, i.e., the storage capacitor Cst is connected between the gate electrode G of the first transistor M1 and the first power line VDD, and the storage capacitor Cst is supplied with a fixed potential by the first power line VDD.
Fig. 7 is a schematic top view of a display panel according to an embodiment of the invention. Referring to fig. 7, the display panel includes pixels 1 arranged in an array, and a capacitor C is provided in each pixel 1, and plays an important role in stable light emission of the pixel, and one end of the capacitor C needs to be connected to a fixed potential line 2. In one embodiment, optionally, the fixed potential line 2 is wound around the edge of the display panel, and the second capacitor plate of the capacitor C is electrically connected to the fixed potential line 2 through the conductive connection line 3; wherein, the conductive connecting wire 3 and the second capacitor plate are arranged on the same layer, so that the second capacitor plate is connected with a fixed potential.
Fig. 8 is a schematic cross-sectional view of another display panel according to an embodiment of the invention. In an embodiment of the present invention, referring to fig. 6 and 8, optionally, part of the traces of the first power line VDD and the reference voltage line Vref are located in the array circuit layer 100; a portion of the second power line VSS is routed to the light emitting device layer 200. The first power line VDD is multiplexed as a fixed potential line; alternatively, the reference voltage line Vref is multiplexed as a fixed potential line. Then, the second capacitor plate 260 may be electrically connected to the fixed potential line through the insulating layer via 101 in the array circuit layer 100. In fig. 8, the first power line VDD is multiplexed as a fixed potential line, the first power line VDD is disposed on the second metal layer, the insulating layer via 101 corresponding to the second capacitor plate 260 is disposed on the insulating layer 160, the insulating layer 170 and the insulating layer 180, and the second capacitor plate 260 disposed on the first electrode layer is connected to the first power line VDD through the insulating layer via 101 so that the second capacitor plate 260 is connected to the fixed potential. Compared with the previous embodiments, the embodiment of the invention does not need to additionally provide the conductive connection line for fixing the potential line, which is beneficial to simplifying the wiring design of the display panel.
Fig. 9 is a schematic circuit diagram of another pixel circuit according to an embodiment of the invention. Referring to fig. 9, unlike the foregoing embodiment, the second power supply line VSS is multiplexed as a fixed potential line. That is, the storage capacitor Cst is connected between the gate electrode G of the first transistor M1 and the second power line VSS, and the storage capacitor Cst is supplied with a fixed potential from the second power line VSS.
Fig. 10 is a schematic cross-sectional view of another display panel according to an embodiment of the invention. Referring to fig. 10, corresponding to fig. 9, the second power line VSS transmitting a voltage to the second electrode is multiplexed as a fixed potential line. Specifically, the pixel defining layer 220 includes a first opening 201 and a second opening 202, the first opening 201 corresponding to a first electrode (e.g., the anode 210) and accommodating the light emitting layer 230; the second opening 202 corresponds to a second capacitor plate 260, and the second capacitor plate 260 is electrically connected to a second electrode (e.g., the cathode 240) through the second opening 202, so that the second capacitor plate 260 is connected to a fixed potential through the second electrode. The embodiment of the invention can etch the pixel definition layer 220 to form the first opening 201 and etch the second opening 202 at the same time, and does not need to carry out an etching and punching process, thereby being beneficial to simplifying the process steps and reducing the cost.
With continued reference to fig. 10, the display panel may further include a support pillar 250, where the support pillar 250 is located on a side of the pixel defining layer 220 away from the array circuit layer 100, for supporting a mask plate to facilitate fabrication of the light emitting layer 230.
Fig. 11 is a schematic diagram of a simulation waveform of a pixel circuit according to an embodiment of the present invention. Referring to fig. 11, a curve l1 is a voltage waveform of the gate of the driving transistor when the second capacitor plate of the storage capacitor is connected to the second power line; curve l2 is the voltage waveform of the gate of the drive transistor when the second capacitor plate of the storage capacitor is connected with the first power line; curve l3 is the voltage waveform of the scan signal on the second scan line. Through verification, no matter the second capacitor polar plate of the storage capacitor is connected with the first power line or the second power line, the storage capacitor can maintain stable voltage after data writing.
In the above embodiments, the pixel circuit of the type 2T1C or the pixel circuit of the type 7T1C is exemplarily shown, but the present invention is not limited thereto, and the pixel circuit is also provided as another type in other embodiments.
In the above embodiments, the thin film transistor TFT is exemplarily shown as a top gate type, but the present invention is not limited thereto, and in other embodiments, the thin film transistor TFT is also provided as a bottom gate type, a double gate type, or the like.
In the above embodiments, the display panel may further include a support pillar PS disposed between the pixel defining layer 220 and the second electrode layer.
In summary, in the embodiment of the invention, the first capacitor plate 1A0 is disposed in the array circuit layer 100, and the second capacitor plate 260 is disposed in the light emitting device layer 200, so that a planarization layer with a thicker film layer thickness is disposed between the array circuit layer 100 and the light emitting device layer 200. That is, the embodiment of the invention skillfully utilizes the thicker film layer in the display panel as the dielectric layer of the capacitor C, and the arrangement can at least realize the following beneficial effects:
in the first aspect, compared with the prior art, the embodiment of the invention increases the distance between the first capacitor plate 1A0 and the second capacitor plate 260, thereby being beneficial to reducing the capacitance of the capacitor C on the basis of not reducing the facing area of the capacitor plates and being beneficial to being applied to the display panel with high refresh frequency.
In the second aspect, compared with the prior art, the distance between the first capacitor plate 1A0 and the second capacitor plate 260 is increased, so that the capacitor C of the embodiment of the invention has relatively smaller fluctuation under the same film thickness process fluctuation, so that the tolerance of the capacitor C to the film thickness process fluctuation is higher, and the stability of the capacitor C is improved.
In the third aspect, compared with the prior art, the distance between the first capacitor plate 1A0 and the second capacitor plate 260 is increased, and when the same capacitance is provided, the line widths of the first capacitor plate 1A0 and the second capacitor plate 260 can be increased, so that the fluctuation of the capacitor C in the embodiment of the invention is relatively smaller under the same line width process fluctuation, so that the tolerance of the capacitor C to the line width process fluctuation is higher, and the stability of the capacitor C is improved.
In summary, the embodiment of the invention improves the stability of the capacitor C, thereby being beneficial to improving the stability of the pixel circuit, and ensuring that the uniformity of the driving current generated between different pixel circuits on the display panel is better; further, the mura problem of the display panel is improved, and the display uniformity is improved.
The embodiment of the invention also provides a display device, which comprises: the technical principle and the effect of the display panel provided by any embodiment of the present invention are similar, and are not repeated here.
The embodiment of the invention also provides a manufacturing method of the display panel, and the manufacturing method of the display panel can be applied to the display panel provided by any embodiment of the invention. Fig. 12 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present invention, and fig. 13 is a schematic structural diagram of the method for manufacturing a display panel according to an embodiment of the present invention formed in each step. Referring to fig. 12 and 13, the manufacturing method of the display panel includes the steps of:
s110, manufacturing an array circuit layer 100 on the substrate 110.
The array circuit layer 100 comprises a plurality of metal layers and a plurality of insulating layers, wherein the insulating layers are arranged between two adjacent metal layers; one of the metal layers is provided with a first capacitor plate 1A0. The metal layer is a film layer provided with a metal pattern, for example, a metal layer provided with a gate electrode G, a metal layer provided with a source electrode S and a drain electrode D, or the like. The insulating layer refers to a film layer for performing an insulating function between metal layers, such as the insulating layer 120, the insulating layer 130, the insulating layer 140, the insulating layer 150, the insulating layer 160, the insulating layer 170, the insulating layer 180, and the like. One of the metal layers is provided with a first capacitor plate 1A0, and the first capacitor plate 1A0 and the gate G are located on the same metal layer.
S120, a light emitting device layer 200 is fabricated on the array circuit layer 100.
The light emitting device layer 200 includes a first electrode layer, which refers to a film layer in which a conductive pattern is disposed in the light emitting device layer 200. The first electrode layer is provided with a second capacitor plate 260; at least one insulating layer is arranged between the first capacitor plate 1A0 and the second capacitor plate 260, and the first capacitor plate 1A0 and the second capacitor plate 260 form a capacitor C.
Through the above steps, in the manufactured display panel, the first capacitor plate 1A0 is located in the array circuit layer 100, and the second capacitor plate 260 is located in the light emitting device layer 200, so that a planarization layer having a thicker film thickness is provided between the array circuit layer 100 and the light emitting device layer 200. That is, the embodiment of the invention skillfully utilizes the thicker film layer in the display panel as the dielectric layer of the capacitor C, and improves the stability of the capacitor C, thereby being beneficial to improving the stability of the pixel circuits and ensuring that the uniformity of the driving current generated between different pixel circuits on the display panel is better; further, the mura problem of the display panel is improved, and the display uniformity is improved.
Fig. 14 is a schematic structural diagram of a manufacturing method of another display panel according to an embodiment of the present invention. Referring to fig. 14, on the basis of the above embodiment, optionally, the method for manufacturing the display panel includes the following steps:
s210, manufacturing an array circuit layer 100 on a substrate 110; the array circuit layer 100 comprises a plurality of metal layers and a plurality of insulating layers, wherein the insulating layers are arranged between two adjacent metal layers; one of the metal layers is provided with a first capacitor plate 1A0.
S220, a first electrode layer is fabricated on the array circuit layer 100, and patterned to form a first electrode (e.g., the anode 210) and a second capacitor plate 260.
The first electrode and the second capacitor plate 260 may be formed in the same deposition process to simplify the process flow. The first electrode and the second capacitor plate 260 may also be formed by two-step deposition processes, respectively, to employ different conductive materials.
S230, a pixel defining layer 220 is fabricated on the first electrode layer, and the pixel defining layer 220 is patterned to form a first opening 201 and a second opening 202.
Wherein the first opening 201 exposes the first electrode to form a pixel opening, accommodates the light emitting layer 230, and provides a driving current to the light emitting layer 230 from the first electrode. The second opening 202 exposes the second capacitive plate 260 to facilitate connection of the second electrode to the second capacitive plate 260 through the second opening 202.
S240, a light emitting layer 230 is fabricated in the first opening 201.
S250, a second electrode layer is fabricated in the second opening 202 and on the light emitting layer 230, so that the second capacitor plate 260 is electrically connected to the second electrode through the second opening 202.
The embodiment of the invention realizes the manufacture of connecting the second capacitor plate 260 with the second electrode through S210-S250. By the arrangement, the second opening 202 can be etched while the first opening 201 is etched by the pixel defining layer 220, so that the fixed potential connection of the second capacitor plate 260 is completed, and an etching and punching process is not needed, thereby being beneficial to simplifying the process steps and reducing the manufacturing cost.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A display panel, comprising:
the array circuit layer comprises a plurality of metal layers and a plurality of insulating layers, and the insulating layers are arranged between two adjacent metal layers; one of the metal layers is provided with a first capacitor plate;
the light-emitting device comprises a light-emitting device layer, wherein the light-emitting device layer comprises a first electrode layer, and the first electrode layer is provided with a second capacitance polar plate; at least one insulating layer is arranged between the first capacitor plate and the second capacitor plate, the first capacitor plate and the second capacitor plate form a capacitor, and the metal layer comprises a first metal layer, a second metal layer and a third metal layer; the first metal layer is provided with a grid electrode, and the first capacitor electrode plate is arranged on the first metal layer;
the light emitting device layer further comprises a pixel defining layer, a light emitting layer and a second electrode layer, wherein the pixel defining layer is positioned between the first electrode layer and the second electrode layer; the first electrode layer is also provided with a first electrode, and the pixel circuit is electrically connected with the first electrode; the second electrode layer is provided with a second electrode, and a second power line transmits voltage to the second electrode; the second power line is multiplexed into a fixed potential line;
wherein the pixel defining layer includes a first opening corresponding to the first electrode and accommodating the light emitting layer, and a second opening; the second opening corresponds to the second capacitor plate, and the second capacitor plate is electrically connected with the second electrode through the second opening.
2. The display panel of claim 1, wherein the light-emitting device layer further comprises a pixel definition layer, a light-emitting layer, and a second electrode layer, the pixel definition layer is located between the first electrode layer and the second electrode layer, and the pixel definition layer comprises a first opening that accommodates the light-emitting layer;
wherein the first electrode layer is further provided with a first electrode, and the second electrode layer is provided with a second electrode; the first electrode layer is positioned on one side close to the array circuit layer; alternatively, the second electrode layer is located on a side close to the array circuit layer.
3. The display panel of claim 2, wherein the material of the second capacitive plate is the same as the material of the first electrode; alternatively, the material of the second capacitor plate is the same as the material of the first capacitor plate.
4. The display panel according to claim 1, wherein the array circuit layer further comprises an active layer disposed between two adjacent insulating layers; the third metal layer is provided with a source electrode and a drain electrode; the active layer, the gate electrode, the source electrode, and the drain electrode constitute a transistor.
5. The display panel according to claim 1 or 4, wherein the capacitor is a storage capacitor in a pixel circuit, the first capacitor plate is electrically connected to a gate of a driving transistor in the pixel circuit, and the second capacitor plate is electrically connected to a fixed potential line.
6. The display panel according to claim 5, wherein the fixed potential line is wound from an edge of the display panel;
the second capacitor polar plate is electrically connected with the fixed potential line through a conductive connecting wire; wherein the conductive connection line and the second capacitor plate are arranged on the same layer.
7. The display panel according to claim 5, wherein the pixel circuit includes at least one of a first power line, a second power line, and a reference voltage line; wherein, the first power line and part of the wires of the reference voltage line are positioned on the array circuit layer; part of the wiring of the second power line is positioned on the light-emitting device layer;
the first power line is multiplexed into the fixed potential line; alternatively, the reference voltage line is multiplexed to the fixed potential line;
the second capacitor plate is electrically connected with the fixed potential line through an insulating layer via hole in the array circuit layer.
8. A display device, comprising: the display panel of any one of claims 1-7.
9. A method for manufacturing a display panel, comprising:
manufacturing an array circuit layer on a substrate; the array circuit layer comprises a plurality of metal layers and a plurality of insulating layers, and the insulating layers are arranged between two adjacent metal layers; one of the metal layers is provided with a first capacitor plate;
manufacturing a light emitting device layer on the array circuit layer; the light-emitting device layer comprises a first electrode layer, and the first electrode layer is provided with a second capacitance pole plate; at least one insulating layer is arranged between the first capacitor plate and the second capacitor plate, and the first capacitor plate and the second capacitor plate form a capacitor; the metal layer comprises a first metal layer, a second metal layer and a third metal layer; the first metal layer is provided with a grid electrode, and the first capacitor electrode plate is arranged on the first metal layer;
manufacturing a pixel definition layer on the first electrode layer, and patterning the pixel definition layer to form a first opening and a second opening; wherein the first opening exposes the first electrode and the second opening exposes the second capacitive plate;
manufacturing a light-emitting layer in the first opening;
and manufacturing a second electrode layer in the second opening and on the light-emitting layer so that the second capacitor plate is electrically connected with the second electrode through the second opening.
10. The method of manufacturing a display panel according to claim 9, wherein manufacturing a light emitting device layer on the array circuit layer, comprises:
and manufacturing a first electrode layer on the array circuit layer, and patterning the first electrode layer to form a first electrode and the second capacitor electrode plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110082454.8A CN112885881B (en) | 2021-01-21 | 2021-01-21 | Display panel, manufacturing method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110082454.8A CN112885881B (en) | 2021-01-21 | 2021-01-21 | Display panel, manufacturing method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112885881A CN112885881A (en) | 2021-06-01 |
| CN112885881B true CN112885881B (en) | 2023-05-16 |
Family
ID=76051519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110082454.8A Active CN112885881B (en) | 2021-01-21 | 2021-01-21 | Display panel, manufacturing method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112885881B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116669477B (en) * | 2023-07-26 | 2023-10-24 | 合肥维信诺科技有限公司 | Display panel, manufacturing method thereof and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104269414A (en) * | 2014-09-25 | 2015-01-07 | 合肥京东方光电科技有限公司 | Array substrate, array substrate manufacturing method and display device |
| CN105470269A (en) * | 2016-01-26 | 2016-04-06 | 深圳市华星光电技术有限公司 | TFT array substrate and manufacturing method thereof |
| CN210837108U (en) * | 2019-12-27 | 2020-06-23 | 昆山国显光电有限公司 | Display panel and display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102015873B1 (en) * | 2013-01-03 | 2019-10-22 | 삼성디스플레이 주식회사 | Back plane of display and manufacturing method for the same |
| CN111210732B (en) * | 2020-03-06 | 2022-06-21 | 合肥维信诺科技有限公司 | Display panel and display device |
-
2021
- 2021-01-21 CN CN202110082454.8A patent/CN112885881B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104269414A (en) * | 2014-09-25 | 2015-01-07 | 合肥京东方光电科技有限公司 | Array substrate, array substrate manufacturing method and display device |
| CN105470269A (en) * | 2016-01-26 | 2016-04-06 | 深圳市华星光电技术有限公司 | TFT array substrate and manufacturing method thereof |
| CN210837108U (en) * | 2019-12-27 | 2020-06-23 | 昆山国显光电有限公司 | Display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112885881A (en) | 2021-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220271107A1 (en) | Array substrate and manufacturing method thereof, and display panel | |
| CN111951729B (en) | Array substrate, display panel and display device | |
| CN109524445B (en) | Display panel and display device | |
| CN111403465B (en) | Array substrate, display panel and display device | |
| CN113078174B (en) | Array substrate, display panel and display device | |
| CN109585511A (en) | Display panel and its manufacturing method | |
| CN112466245A (en) | Display panel and display device | |
| US10868103B2 (en) | Wiring structure and manufacture method thereof, OLED array substrate and display device | |
| US11903279B2 (en) | Display substrate including first reference voltage line being electrically coupled to first reference voltage auxiliary line through via holes penetrating through insulation layer therebetween, and display device having the same | |
| CN113471264A (en) | Display panel and display device | |
| CN113035134A (en) | Display panel and display device | |
| CN113436569B (en) | Display panel, manufacturing method thereof and display device | |
| US12165582B2 (en) | Display panel for reducing flickering display | |
| CN114613822A (en) | Display panels and display devices | |
| CN112885881B (en) | Display panel, manufacturing method thereof and display device | |
| CN114783372B (en) | Pixel driving circuit, display panel and display device | |
| CN210628317U (en) | Display substrate and display device | |
| CN114724519B (en) | Pixel circuit, display panel and display device | |
| CN112968032B (en) | Display panel, preparation method thereof and display device | |
| CN114284317B (en) | display panel | |
| CN113241365B (en) | Display panel and display device | |
| CN114743989A (en) | Array substrate and display panel | |
| CN112599010B (en) | Display panel and display device | |
| CN114743504B (en) | Pixel circuit, display panel and display device | |
| US20240268172A1 (en) | Display substrate and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |