CN112885389A - Double-end data transmission circuit and memory - Google Patents
Double-end data transmission circuit and memory Download PDFInfo
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- CN112885389A CN112885389A CN202110340036.4A CN202110340036A CN112885389A CN 112885389 A CN112885389 A CN 112885389A CN 202110340036 A CN202110340036 A CN 202110340036A CN 112885389 A CN112885389 A CN 112885389A
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Abstract
The embodiment of the application provides a bi-polar data transmission circuit and memory, bi-polar data transmission line, includes: a first global data line and a second global data line which are differential data transmission lines; a first local data line and a second local data line which are differential data transmission lines; the conversion module is connected among the external data line, the first global data line and the second global data line and is used for controlling data transmission between the external data line and the first global data line according to a first control signal; the enabling control module is used for outputting a third control signal; the writing module is connected among the first local data line, the second local data line, the first global data line and the second global data line, and judges that the data in the first global data line is transmitted to the first local data line and the data in the second global data line is transmitted to the second local data line based on a third control signal; the present application is directed to reducing memory power consumption and improving reliability of data storage.
Description
Technical Field
The present disclosure relates to the field of semiconductor circuit design, and more particularly, to a dual-terminal data transmission circuit and a memory.
Background
Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and high transmission speed. With the development of semiconductor technology, the DRAM technology is more and more advanced, and the integration level of the memory cell is higher and higher; meanwhile, performance, power consumption, reliability and the like of the DRAM are also increasingly required by various applications.
However, the existing memory still has room for improvement in power consumption, reliability, and the like, and it is urgently needed to design a memory capable of reducing power consumption and improving storage reliability, and further improve the comprehensive performance of the existing memory, so as to meet the requirements of various application scenarios.
Disclosure of Invention
The embodiment of the application provides a double-end data transmission circuit and a memory, so that the power consumption of the memory is reduced, the reliability of data storage is improved, and the like.
In order to solve the above technical problem, an embodiment of the present application provides a data transmission line for writing data into a memory cell and reading data from the memory cell, including: the first global data line and the second global data line are mutually differential data transmission lines and transmit signals which are mutually opposite in phase; the first local data line and the second local data line are mutually differential data transmission lines and transmit signals which are mutually opposite in phase; the conversion module is connected among the external data line, the first global data line and the second global data line and is used for controlling data transmission between the external data line and the first global data line and/or the second global data line according to a first control signal, the first control signal is used for representing whether the difference bit number of the currently transmitted data of the external data line and the currently transmitted data of the first global data line exceeds a first preset value; if the difference digit exceeds a first preset value, the conversion module is configured to transmit data in the external data line to a second global data line; if the difference digit does not exceed a first preset value, the conversion module is configured to transmit data in the external data line to a first global data line; the enabling control module is used for receiving the first control signal and the second control signal and outputting a third control signal for representing whether the first control signal and the second control signal are the same or not; the second control signal is used for representing whether the bit number occupied by the high-level data in the external data line exceeds a second preset value; and the writing module is connected among the first local data line, the second local data line, the first global data line and the second global data line, controls the data in the first global data line and/or the second global data line to be transmitted to the first local data line and/or the second local data line, and judges whether to transmit the data in the first global data line to the first local data line and transmit the data in the second global data line to the second local data line or transmit the data in the first global data line to the second local data line and transmit the data in the second global data line to the first local data line based on a third control signal.
Compared with the prior art, the first control signal is obtained by comparing the data difference between the external data line and the first global data line, and whether the data of the external data line is transmitted to the first global data line or the second global data line is judged, so that the data overturning frequency in the data transmission process is reduced, and the power consumption of data transmission is saved; acquiring a second control signal by comparing the number of low-level data and high-level data in an external data line, and acquiring a third control signal by the first control signal and the second control signal to judge whether the data of the first global data line is transmitted to the first local data line or the second local data line, and/or whether the second global data line is transmitted to the first local data line or the second local data line, so as to ensure the reliability of data storage and reading; and judging whether the data of the first local data line or the second local data line is transmitted to the external data line during reading by acquiring the second control signal so as to ensure that the read data is the data originally written into the memory.
In addition, the write module includes: a first conversion circuit configured to control data in the first global data line to be transmitted to the first local data line or to control data in the second global data line to be transmitted to the first local data line; and the second conversion circuit is configured to control data in the first global data line to be transmitted to the second local data line or transmit data in the second global data line to the second local data line.
In addition, a first conversion circuit includes: the MOS transistor comprises a first MOS transistor and a second MOS transistor; the grid electrode of the first MOS tube receives a third control signal, the source electrode of the first MOS tube is connected with the first global data line, and the drain electrode of the first MOS tube is connected with the first local data line; the grid electrode of the second MOS tube receives a fourth control signal, the source electrode of the second MOS tube is connected with the second global data line, the drain electrode of the second MOS tube is connected with the first local data line, and the third control signal and the fourth control signal are opposite-phase signals.
In addition, the second conversion circuit includes: a third MOS transistor and a fourth MOS transistor; a grid electrode of the third MOS tube receives a fourth control signal, a source electrode of the third MOS tube is connected with the first global data line, a drain electrode of the third MOS tube is connected with the second local data line, and the third control signal and the fourth control signal are mutually opposite-phase signals; the grid electrode of the fourth MOS tube receives a third control signal, the source electrode of the fourth MOS tube is connected with the second global data line, and the drain electrode of the fourth MOS tube is connected with the second local data line.
In addition, the two-terminal data transmission circuit further includes: and the counting module is connected with the external data line and used for outputting a second control signal, and the second control signal is stored in the storage unit as the marking bit data so as to read the second control signal in the data reading process.
In addition, the two-terminal data transmission circuit further includes: the reading module is used for controlling data transmission among the first local data line, the second local data line and the external data line according to the read second control signal; if the number of bits occupied by the high-level data exceeds a second preset value, the reading module is configured to finally transmit the data in the second local data line to an external data line; if the number of bits occupied by the high-level data does not exceed the second preset value, the reading module is configured to finally transmit the data in the first local data line to the external data line.
In addition, the reading module is connected among the first local data line, the second local data line, the first global data line and the second global data line, and is used for controlling data transmission among the first local data line, the second local data line, the first global data line and the second global data line according to a second control signal, if the number of bits occupied by the high-level data exceeds a second preset value, the reading module is configured to transmit an opposite value of the data in the first local data line to the first global data line, and/or transmit an opposite value of the data in the second local data line to the second global data line; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module is configured to transmit an opposite value of data in the first local data line to the second global data line and/or transmit an opposite value of data in the second local data line to the first global data line. After the data conversion from the global data line to the local data line is carried out through the second control signal, the number of low-level data in the data is not lower than that of high-level data, and the total turnover frequency of subsequently read data is 0 or even number, so that the accuracy of data reading is ensured.
In addition, the readout module includes: a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor and a fourteenth MOS transistor; the grid electrode of the thirteenth MOS tube is connected with the first local data line, the drain electrode of the thirteenth MOS tube is connected with the second global data line, and the source electrode of the thirteenth MOS tube is connected with the drain electrode of the seventh MOS tube; the grid electrode of the fifth MOS tube is connected with the second local data line, the drain electrode of the fifth MOS tube is connected with the second global data line, and the source electrode of the fifth MOS tube is connected with the drain electrode of the eighth MOS tube; the grid electrode of the seventh MOS tube is connected with a fifth control signal, the source electrode of the seventh MOS tube is connected with the drain electrode of the eleventh MOS tube, and the second control signal and the fifth control signal are mutually opposite-phase signals; the grid electrode of the eighth MOS tube is connected with the second control signal, and the source electrode of the eighth MOS tube is connected with the drain electrode of the eleventh MOS tube; a grid electrode of the eleventh MOS tube receives a read enabling signal, and a source electrode of the eleventh MOS tube is grounded; the grid electrode of the fourteenth MOS tube is connected with the second local data line, the drain electrode of the fourteenth MOS tube is connected with the first global data line, and the source electrode of the fourteenth MOS tube is connected with the drain electrode of the ninth MOS tube; the grid electrode of the sixth MOS tube is connected with the first local data line, the drain electrode of the sixth MOS tube is connected with the first global data line, and the source electrode of the sixth MOS tube is connected with the drain electrode of the tenth MOS tube; the grid electrode of the ninth MOS tube is connected with the fifth control signal, and the source electrode of the ninth MOS tube is connected with the drain electrode of the twelfth MOS tube; the grid electrode of the tenth MOS tube is connected with the second control signal, and the source electrode of the tenth MOS tube is connected with the drain electrode of the twelfth MOS tube; the grid electrode of the twelfth MOS tube receives the read enabling signal, and the source electrode of the twelfth MOS tube is grounded.
In addition, the reading module is connected with the first global data line, the second global data line and the external data line and is used for controlling data transmission among the first global data line, the second global data line and the external data line according to a second control signal, and if the bit number occupied by the high-level data exceeds a second preset value, the reading module is configured to transmit the opposite value of the data in the first global data line to the external data line and/or transmit the data in the second global data line to the external data line; if the number of bits occupied by the high-level data does not exceed the second preset value, the reading module is configured to transmit the data in the first global data line to the external data line and/or transmit the opposite value of the data in the second global data line to the external data line. And after the data from the global data line to the first local data line is converted by the second control signal, the number of low-level data in the data is not lower than that of high-level data, so that the accuracy of data reading is ensured.
In addition, the readout module includes: one end of the first transmission element is connected with the first global data line, and the other end of the first transmission element is connected with the external data line; one end of the second transmission element is connected with the second global data line, and the other end of the second transmission element is connected with the external data line; the first transmission element and the second transmission element are also used for receiving a second control signal and conducting the first transmission element or the second transmission element according to the second control signal.
In addition, the second preset value is 50% of the number of bits of data transmitted by the external data line.
In addition, the conversion module includes: one end of the third transmission element is connected with the external data line through the phase inverter, and the other end of the third transmission element is connected with the first global data line; one end of the fourth transmission element is connected with the external data line, and the other end of the fourth transmission element is connected with the first global data line; the third transmission element and the fourth transmission element are also used for receiving a first control signal and selecting to conduct the third transmission element or the fourth transmission element according to the first control signal.
In addition, the two-terminal data transmission circuit further includes: and the comparison module is connected with the external data line and the global data line and used for generating a first control signal according to whether the difference digit of the data currently transmitted by the external data line and the data currently transmitted by the global data line exceeds a first preset value.
In addition, the comparison module includes: the detection unit is connected with the external data line and the global data line and detects currently transmitted data of the external data line and currently transmitted data of the global data line bit by bit, if the currently transmitted data of the external data line is different from the currently transmitted data of the global data line, a first sub-control signal is generated, and if the currently transmitted data of the external data line is the same as the currently transmitted data of the global data line, a second sub-control signal is generated; and the acquisition unit is connected with the detection unit and used for acquiring the first sub-control signals and the second sub-control signals, and if the number of the first sub-control signals exceeds a first preset value, the first control signals are generated, wherein the first preset value is a preset percentage of the sum of the number of the first sub-control signals and the number of the second sub-control signals. The first control signal is obtained by comparing the data difference between the external data line and the global data line, and whether the first data turnover is carried out is judged so as to avoid the turnover of the transmission data line in the data transmission process and save the power consumption of data transmission.
In addition, the preset percentage is 50%.
In addition, the enable control module includes: the first enabling control module is used for generating a third control signal according to the first control signal and the second control signal.
In addition, the first enabling control module is further used for receiving a writing enabling signal, and if the writing enabling signal is in an active level, a third control signal is generated.
In addition, the enable control module further includes: the second enabling control module is used for receiving the first control signal, the second control signal and the inverted signal of the writing enabling signal, if the inverted signal of the writing enabling signal is an effective level, a fourth control signal is generated, and the third control signal and the fourth control signal are mutually inverted signals.
An embodiment of the present application further provides a memory, including the above-mentioned double-ended data transmission circuit, further including: and the memory unit is connected with the first local data line and the second local data line, and the first local data line and the second local data line are used for writing data into the memory unit and reading data out of the memory unit.
Compared with the related art, the first control signal is obtained by comparing the data difference between the external data line and the first global data line, and whether the data of the external data line is transmitted to the first global data line or the second global data line is judged, so that the data turnover frequency in the data transmission process is reduced, and the power consumption of data transmission is saved; acquiring a second control signal by comparing the number of low-level data and high-level data in an external data line, and acquiring a third control signal by the first control signal and the second control signal to judge whether the data of the first global data line is transmitted to the first local data line or the second local data line, and/or whether the data of the second global data line is transmitted to the first local data line or the second local data line, so as to ensure the reliability of data storage and readout; and judging whether the data of the first local data line or the second local data line is transmitted to an external data line during reading by acquiring the second control signal so as to ensure that the read data is the data originally written into the memory.
Drawings
Fig. 1 and fig. 2 are schematic structural diagrams of a dual-ended data transmission circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a comparison module according to an embodiment of the present invention;
fig. 4 is a circuit diagram of a conversion module according to an embodiment of the invention;
FIG. 5 is a circuit diagram of an enable control module according to an embodiment of the present invention;
fig. 6 is a circuit diagram of a first conversion circuit according to an embodiment of the invention;
fig. 7 is a circuit diagram of a second conversion circuit according to an embodiment of the invention;
fig. 8 is a circuit diagram of a readout module according to an embodiment of the invention;
fig. 9 and 10 are schematic structural diagrams of a dual-ended data transmission circuit according to another embodiment of the present invention;
fig. 11 is a circuit diagram of a readout module according to another embodiment of the invention;
fig. 12 and fig. 13 are schematic structural diagrams of a memory according to still another embodiment of the invention;
Detailed Description
Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and high transmission speed. With the development of semiconductor technology, the DRAM technology is more and more advanced, and the integration level of the memory cell is higher and higher; meanwhile, various applications have higher and higher requirements on the performance, power consumption, reliability and the like of the DRAM, and the existing memory still has an improvement space in the aspects of power consumption, reliability and the like, so that a memory capable of reducing power consumption and improving storage reliability is urgently needed to be designed, and the comprehensive performance of the existing memory is further improved so as to meet the requirements of various application scenarios.
To solve the above problem, an embodiment of the present application provides a two-terminal data transmission line for writing data into a memory cell and reading data from the memory cell, including: the first global data line and the second global data line are mutually differential data transmission lines and transmit signals which are mutually opposite in phase; the first local data line and the second local data line are mutually differential data transmission lines and transmit signals which are mutually opposite in phase; the conversion module is connected among the external data line, the first global data line and the second global data line and is used for controlling data transmission between the external data line and the first global data line and/or the second global data line according to a first control signal, the first control signal is used for representing whether the difference bit number of the currently transmitted data of the external data line and the currently transmitted data of the first global data line exceeds a first preset value; if the difference digit exceeds a first preset value, the conversion module is configured to transmit data in the external data line to a second global data line; if the difference digit does not exceed a first preset value, the conversion module is configured to transmit data in the external data line to a first global data line; the enabling control module is used for receiving the first control signal and the second control signal and outputting a third control signal for representing whether the first control signal and the second control signal are the same or not; the second control signal is used for representing whether the bit number occupied by the high-level data in the external data line exceeds a second preset value; and the writing module is connected among the first local data line, the second local data line, the first global data line and the second global data line, controls the data in the first global data line and/or the second global data line to be transmitted to the first local data line and/or the second local data line, and judges whether to transmit the data in the first global data line to the first local data line and transmit the data in the second global data line to the second local data line or transmit the data in the first global data line to the second local data line and transmit the data in the second global data line to the first local data line based on a third control signal.
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be combined with each other and cited as reference to each other without contradiction.
Fig. 1 and fig. 2 are schematic structural diagrams of a double-ended data transmission circuit provided in this embodiment; fig. 3 is a schematic structural diagram of a comparison module provided in this embodiment, fig. 4 is a schematic circuit diagram of a conversion module provided in this embodiment, fig. 5 is a schematic circuit diagram of an enable control module provided in this embodiment, fig. 6 is a schematic circuit diagram of a first conversion circuit provided in this embodiment, fig. 7 is a schematic circuit diagram of a second conversion circuit provided in this embodiment, and fig. 8 is a schematic circuit diagram of a readout module provided in this embodiment; the double-ended data transmission circuit provided in the present embodiment is further described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a two-terminal data transfer circuit 100 for writing data to and reading data from a memory cell includes:
the first global data line YIO and the second global data line YIO-, which are differential data transmission lines, the first global data line YIO and the second global data line YIO-transmit signals that are opposite in phase to each other.
The first local data line LIO and the second local data line LIO-of the differential data transmission lines transmit signals which are opposite in phase.
By providing the first local data line LIO, the second local data line LIO-, and the first global data line YIO and the second global data line YIO-for transmitting differential data, stability of data inversion between the first local data line LIO and the second local data line LIO-and the first global data line YIO and the second global data line YIO-is ensured.
And a conversion module 101 connected among the external data line DataBus, the first global data line YIO and the second global data line YIO-, and configured to control data transmission between the external data line DataBus and the first global data line YIO and/or the second global data line YIO-according to a first control signal Flag.
The first control signal Flag is used to indicate whether the difference bit number between the data currently transmitted by the external data line DataBus and the data currently transmitted by the first global data line YIO exceeds a first preset value.
It should be noted that, in other embodiments, the first control signal is further used to characterize whether a difference bit number between data currently transmitted by the external data line and data currently transmitted by the second global data line exceeds a first preset value; in practical applications, the difference between the external data line DataBus and the first global data line YIO or the difference between the external data line DataBus and the second global data line YIO "may be selected according to specific application scenarios, and the corresponding first control signal Flag may be set.
Note that, the external data line DataBus mentioned in this embodiment is only for distinguishing a transmission line different from the global data line YIO, and the "external" in the external data line DataBus is external to the global data line YIO and the memory cell array, and is not a data line external to the chip.
In one example, referring to fig. 2, the dual ended data transmission circuit 100 further comprises: the comparing module 111 is connected to the external data line DataBus and the first global data line YIO, and configured to generate the first control signal according to whether a difference bit number between data currently transmitted by the external data line DataBus and data currently transmitted by the first global data line YIO exceeds a first preset value.
Specifically, referring to fig. 3, the comparison module 111 includes: the detecting unit 201 is connected to the external data line DataBus and the first global data line YIO, and detects data currently transmitted by the external data line DataBus and data currently transmitted by the first global data line YIO bit by bit. If the data transmitted by the current bit external transmission line DataBus is different from the data transmitted by the current bit first global data line YIO, generating a first sub-control signal; if the data transmitted by the current bit external transmission line DataBus is the same as the data transmitted by the current bit first global data line YIO, the second sub-control signal is transmitted. Specifically, the manner of generating the first sub control signal and the second sub control signal refers to the following table:
the obtaining unit 202 is connected to the detecting unit 201, and is configured to obtain the first sub-control signal and the second sub-control signal. And if the number of the first sub-control signals exceeds a first preset value, generating a first control signal Flag, wherein the first preset value is a preset percentage of the sum of the number of the first sub-control signals and the number of the second sub-control signals. Specifically, the first control signal Flag is generated by referring to the following table (taking the sum of the numbers of the first sub-control signal and the second sub-control signal as 40 as an example, which is only schematic):
| predetermined percentage of | Number of first sub-control signals | Number of second sub-control signals | First control signal Flag |
| 40 | 18 | 22 | 1 |
| 50 | 23 | 17 | 1 |
| 60 | 22 | 18 | 0 |
It should be noted that, in this example, the preset percentage is 50%, and by setting the preset percentage to 50%, it is ensured that the first control signal is generated when the difference bit number between the currently transmitted data of the external data line DataBus and the currently transmitted data of the first global data line YIO is greater than the same bit number, and the external data line DataBus transmits the transmitted data into the second global data line YIO —, so that data inversion of the first global data line YIO and the second global data line YIO —, and thus energy consumption during data transmission is reduced.
With continued reference to fig. 1, for the conversion module 101, if the difference bit number between the data currently transmitted by the external data line DataBus and the data currently transmitted by the first global data line YIO exceeds a first preset value, the conversion module 101 is configured to transmit the data in the external data line DataBus to the second global data line YIO —; if the difference between the currently transmitted data of the external data line DataBus and the currently transmitted data of the first global data line YIO does not exceed the first preset value, the conversion module 101 is configured to transmit the data in the external data line DataBus to the first global data line YIO.
Specifically, referring to fig. 4, the conversion module 101 includes: a third transmission element 303 having one end connected to the external data line DataBus through an inverter and the other end connected to the first global data line YIO; a fourth transmission element 304 having one end connected to the external data line DataBus and the other end connected to the first global data line YIO; the third transmission element 303 and the fourth transmission element 304 are further configured to receive a first control signal Flag, and to select to turn on the third transmission element 303 or the fourth transmission element 304 according to the first control signal Flag.
It should be noted that the second transmission data line YIO — may be generated by serially connecting inverters to the first global data line YIO, or a transmission circuit similar to the external data line DataBus to connect the first global data line YIO may be adopted, and specifically, the transmission circuit includes: a fifth transmission element, one end of which is connected with the external data line DataBus and the other end of which is connected with the second global data line YIO-; a sixth transmission element, one end of which is connected to the external data line DataBus through an inverter and the other end of which is connected to the second global data line YIO-; the fifth transmission element and the sixth transmission element are further configured to receive a first control signal Flag, and to select to turn on the fifth transmission element or the sixth transmission element according to the first control signal Flag.
Referring to fig. 4, the embodiment takes the example of controlling the third transmission element 303 and the fourth transmission element 304 to be conductive at a low level as follows:
when the first control signal Flag is "1", the third transmission element 303 turns on the signal transmission line where the third transmission element is located, and at this time, the external data line DataBus is connected with the global data line YIO through the inverter, so that the external data line DataBus inverts transmitted data and transmits the inverted data to the first global data line YIO, and the external data line DataBus directly transmits the transmitted data to the second global data line YIO "because signals transmitted in the first global data line YIO and the second global data line YIO" are opposite-phase signals; the fourth transmission element 304 turns off the signal transmission line. When the control signal Flag is "0", the third transmission element 303 turns off the signal transmission line, the fourth transmission element 304 turns on the signal transmission line, and the external data line DataBus is directly connected to the first global data line YIO, so that the external data line DataBus directly transmits the transmitted data to the first global data line YIO.
In some embodiments, the external data line and the second global data line YIO-are also provided with a data conversion circuit similar to the conversion module 101, and the control process is opposite to that of the conversion module 101, that is, the control unit is configured to turn on a path for directly transmitting the external data line data DataBus to the second global data line YIO-when the first control signal Flag is "1", and turn on a path for transmitting the data of the external data line data DataBus to the second global data line YIO-after being inverted when the first control signal Flag is "0".
Secondly, it should be noted that in other embodiments, different control methods may also be adopted to control the third transmission element and the fourth transmission element to be turned on, so as to ensure that when a difference bit number between data currently transmitted by the external data line DataBus and data currently transmitted by the first global data line YIO or the second global data line YIO — exceeds a first preset value, the external data line DataBus turns over the transmitted data and then transmits the data to the second global data line YIO —; when the difference bit number between the data currently transmitted by the external data line DataBus and the data currently transmitted by the global data line YIO does not exceed the first preset value, the external data line DataBus directly transmits the transmitted data into the second global data line YIO-.
In some embodiments, an amplifying circuit may be disposed between the first global data line YIO and the second global data line YIO — to enable the first global data line YIO and the second global data line YIO-to transmit signals that are opposite to each other.
With continued reference to fig. 2, the dual ended data transmission circuit 100 further comprises: a statistic module 112, connected to the external data line DataBus, configured to output a second control signal 1 "more", where the second control signal 1 "more" is used for representing whether a bit number occupied by high-level data in the external data line DataBus exceeds a second preset value, and specifically, the following table is referred to in a manner of generating the second control signal 1 "more" (taking the second preset value as an example of 50% of a bit number of data transmitted by the external data line):
| number of high levels of external data lines | Number of low levels of external data lines | |
| 22 | 18 | 1 |
| 19 | 21 | 0 |
It should be noted that, in other embodiments, it may also be configured that when the number of high-level data of the external data line is greater than the number of low-level data of the external data line, the second control signal is 0; when the number of high level data of the external data line is less than the number of low level data of the external data line, the second control signal is 1.
In addition, the second control signal 1 "more" is stored as flag bit data in the memory cell to read out the second control signal 1 "more" in the process of reading out data.
In an example, referring to fig. 3, the controller is configured to detect data transmitted by the external data line DataBus bit by bit, and obtain the second control signal 1 "more" based on whether the number of bits occupied by high level data exceeds the second preset value.
It should be noted that, in this example, the second preset value is 50%, and by setting the second preset value to 50%, it is ensured that when data transmitted by the external data line DataBus is stored in the storage unit, the amount of data stored in the low level is not less than the amount of data stored in the high level, thereby improving the reliability of data storage and readout.
With continued reference to fig. 1, the dual ended data transmission circuit 100 further comprises: the write module 103 is connected among the first local data line LIO, the second local data line LIO-, the first global data line YIO and the second global data line YIO-, and controls the data in the first global data line YIO and/or the second global data line YIO-to be transmitted to the first local data line LIO and/or the second local data line LIO-, and determines, based on the third control signal WrEn, whether to transmit the data in the first global data line YIO to the first local data line LIO and the data in the second global data line YIO-to the second local data line LIO-, or to transmit the data in the first global data line YIO to the second local data line LIO-and the data in the second global data line YIO-to the first local data line LIO.
Wherein the third control signal WrEn is used to represent whether the value of the first control signal Flag and the value of the second control signal 1 "more" are the same.
In this embodiment, when the first control signal Flag is 1, the external data is represented to be transmitted to the second global data line YIO-; when the second control signal 1 'more' is 1, the data which is finally stored in the storage unit is represented to be an opposite value of the original data of the external data line; at this time, the data of the first global data line YIO can be directly stored in the memory cell if the first global data line YIO has transmitted the opposite value of the external original data, that is, the data of the first global data line YIO can be transmitted to the first local data line LIO and the data of the second global data line YIO-can be transmitted to the second local data line LIO-if the third control signal WrEn is 1. Correspondingly, when the first control signal Flag is 1, the external data is characterized to be transmitted to the second global data line YIO-; when the second control signal 1 'more' is 0, the data finally stored in the storage unit is represented as external data line original data; at this time, the first global data line YIO transmits the inverse value of the external original data, and the data of the second global data line YIO-is finally stored in the memory cell, i.e. when the third control signal WrEn is 0, it indicates that the data of the first global data line YIO is to be transmitted to the second local data line LIO-, and the data of the second global data line YIO-is to be transmitted to the first local data line LIO. The configuration of the third control signal WrEn is referenced to the following table:
| first control signal Flag | |
Third |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
| 0 | 1 | 0 |
| 0 | 0 | 1 |
It should be noted that, when the setting manners of the first control signal Flag and the second control signal 1 "more" are changed, the setting manner of the third control signal WrEn needs to be changed according to the setting manners of the first control signal Flag and the second control signal 1 "more" to ensure that the amount of data finally stored in the low level is not less than the amount of data stored in the high level.
Referring to fig. 1, the dual ended data transmission circuit 100 further comprises: the enable control module 133 is configured to receive the first control signal Flag and the second control signal 1 "more", and output a third control signal indicating whether the first control signal Flag and the second control signal 1 "more" are the same.
The second control signal 1 "more" is used to represent whether the bit number occupied by the high-level data in the external data line DataBus exceeds a second preset value.
Specifically, in the present embodiment, the enable control module 133 includes: the first enabling control module is used for generating a third control signal according to the first control signal Flag and the second control signal 1 'more'; the second enable control module is configured to receive the first control signal Flag and the inverted signal of the second control signal 1 "more", and generate a fourth control signal WrEn-, the third control signal WrEn and the fourth control signal WrEn-are inverted signals of each other according to the inverted signals of the first control signal Flag and the second control signal 1 "more".
In addition, the first enable control module is further configured to receive a write enable signal WriteEnable (refer to fig. 5), and generate a third control signal WrEn if the write enable signal WriteEnable is at an active level. The second enable control module is further configured to receive an inverted signal WriteEnable of the write enable signal WriteEnable, and generate a fourth control signal WrEn if the inverted signal WriteEnable of the write enable signal WriteEnable is at an active level.
In one example, referring to fig. 5, the first control signal Flag and the second control signal 1 "more" are connected through an exclusive or gate XOR, and an output terminal of the exclusive or gate XOR is connected to the same nor gate as an inverted signal WriteEnable of the write enable signal WriteEnable.
In this example, the data transmission circuit further includes: and the second enabling control module is used for receiving the first control signal Flag, the second control signal 1 'more' and the direction signal WriteEnable of the writing enabling signal, and generating a fourth control signal WrEn-, a third control signal WrEn and a fourth control signal WrEn-which are mutually opposite-phase signals when the inverted signal WriteEnable of the writing enabling signal WriteEnable is an effective level.
Specifically, the first control signal Flag and the second control signal 1 "more" are connected through an exclusive or gate XOR, an output terminal of which is connected to an inverter, and an inverted signal WriteEnable-connected to the write enable signal WriteEnable is connected to the same nor gate.
For the circuit for generating the third control signal WrEn and the fourth control signal WrEn-, when the write enable signal WriteEnable is 0, the inverted signal WriteEnable-of the write enable signal is 1, and at this time, the third control signal WrEn and the fourth control signal WrEn-are both 0, which is not satisfactory and cannot be applied; when the write enable signal WriteEnable is 1 and the inverse signal WriteEnable-of the write enable signal is 0, the circuit functions as follows:
if the first control signal Flag is 1 and the second control signal 1 'more' is 1, the XOR gate XOR has the same working principle of "0" and different working principle of "1", the output signal of the XOR gate XOR is 0, the generated third control signal WrEn is 1, and the fourth control signal WrEn-is 0.
If the first control signal Flag is 1 and the second control signal 1 'more' is 0, since the working principle of the XOR gate XOR is "same as 0, but different from 1", the output signal of the XOR gate XOR is 1, and at this time, the generated third control signal WrEn is 0 and the fourth control signal WrEn-is 1.
If the first control signal Flag is 0, the second control signal 1 'more' is 1, and since the working principle of the XOR gate XOR is "same as 0, but different from 1", the output signal of the XOR gate XOR is 1, and at this time, the generated third control signal WrEn is 0, and the fourth control signal WrEn-is 1.
If the first control signal Flag is 0, the second control signal 1 'more' is 0, and since the working principle of the XOR gate XOR is "same as 0, but different from 1", the output signal of the XOR gate XOR is 0, at this time, the generated third control signal WrEn is 1, and the fourth control signal WrEn-is 0.
Specifically, the writing module 103 includes: a first conversion circuit 113 and a second conversion circuit 123.
The first conversion circuit 113 is configured to control data transfer in the first global data line YIO to the first local data line LIO or to transfer data in the second global data line YIO-to the first local data line LIO.
In one example, referring to fig. 6, the first conversion circuit 113 includes: a first MOS transistor 401 and a second MOS transistor 402.
The gate of the first MOS transistor 401 receives the third control signal WrEn, the source is connected to the first global data line YIO, and the drain is connected to the first local data line LIO; the gate of the second MOS transistor 402 receives a fourth control signal WrEn-, the source is connected to the second global data line YIO-, the drain is connected to the first local data line LIO, and the third control signal WrEn and the fourth control signal are inverted signals WrEn-.
It should be noted that the term "source" or "drain" in the first MOS transistor 401 and the second MOS transistor 402 is only used to distinguish the ports of the MOS transistors, and is not limited at all, i.e., the concepts of source and drain may be interchanged.
The second conversion circuit 123 is configured to control the transfer of data in the first global data line YIO to the second local data line LIO-, or to transfer data in the second global data line YIO-to the second local data line LIO-.
In one example, referring to fig. 7, the second conversion circuit 123 includes: a third MOS transistor 403 and a fourth MOS transistor 404.
The gate of the third MOS transistor 403 receives the fourth control signal WrEn-, the source is connected to the first global data line YIO, the drain is connected to the second local data line LIO-, the third control signal WrEn and the fourth control signal WrEn-are opposite-phase signals; the gate of the fourth MOS transistor 404 receives the third control signal WrEn, the source is connected to the second global data line YIO, and the drain is connected to the second local data line LIO-.
It should be noted that the term "source" or "drain" in the third MOS transistor 403 and the fourth MOS transistor 404 is only used to distinguish the ports of the MOS transistors, and is not limited at all, i.e., the concepts of source and drain can be interchanged.
For the first conversion circuit 113 and the second conversion circuit 123, the operation principle is as follows:
when the third control signal WrEn is 1 and the fourth control signal WrEn-is 0, the data transmission among the first global data line YIO, the second global data line YIO, the first local data line LIO and the second local data line LIO-is controlled by the first conversion circuit 113 and the second conversion circuit 123. Specifically, when YIO is 1, at this time, the gates of the first MOS transistor 401 and the fourth MOS transistor 404 are turned on, the first global data line YIO and the first local data line LIO are connected through the first MOS transistor 401, and the first local data line LIO and the first global data line YIO are 1; the second global data line YIO-and the second local data line LIO-are connected through the fourth MOS transistor 404, and the second local data line LIO-and the second global data line YIO-are 0. When YIO is 0, at this time, the gates of the first MOS transistor 401 and the fourth MOS transistor 404 are turned on, the first global data line YIO and the first local data line LIO are connected through the first MOS transistor 401, and the first local data line LIO and the first global data line YIO are 0; the second global data line YIO-and the second local data line LIO-are connected through the fourth MOS transistor 404, and the second local data line LIO-and the second global data line YIO-are 1.
When the third control signal WrEn is 0 and the fourth control signal WrEn-is 1, the data transmission among the first global data line YIO, the second global data line YIO, the first local data line LIO and the second local data line LIO-is controlled by the first conversion circuit 113 and the second conversion circuit 123. Specifically, when YIO is 1, the gates of the second MOS transistor 402 and the third MOS transistor 403 are turned on, the second global data line YIO — and the first local data line LIO are connected through the second MOS transistor 402, and the first local data line LIO and the second global data line YIO — are 0; the first global data line YIO and the second local data line LIO-are connected through the third MOS transistor 403, and the second local data line LIO-and the first global data line YIO are 1. When YIO is 0, at this time, the gates of the second MOS transistor 402 and the third MOS transistor 403 are turned on, the second global data line YIO — and the first local data line LIO are connected through the second MOS transistor 402, and the first local data line LIO and the second global data line YIO — are 1; the first global data line YIO and the second local data line LIO-are connected through the third MOS transistor 403, and the second local data line LIO-and the first global data line YIO are 0.
The two-terminal data transmission circuit 100 further comprises: the readout module 102 is configured to control data transmission among the first local data line LIO, the second local data line LIO-, and the external data line DataBus according to the read second control signal 1 "more", and if the bit number occupied by the high-level data exceeds a second preset value, the readout module 102 is configured to finally transmit data in the second local data line LIO-to the external data line DataBus; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module 102 is configured to finally transmit the data in the first local data line LIO to the external data line DataBus.
Referring to fig. 1, in the present embodiment, the readout module 102 is connected between the first and second local data lines LIO and LIO-, the first and second global data lines YIO and YIO-, and is configured to control data transmission between the first and second local data lines LIO and LIO-and the first and second global data lines YIO and YIO-according to the second control signal 1 "more".
If the number of bits occupied by the high level data exceeds the second preset value, the readout module 102 is configured to transmit an opposite value of the data in the first local data line LIO to the first global data line YIO, and/or transmit an opposite value of the data in the second local data line LIO-to the second global data line YIO-; if the number of bits occupied by the high level data does not exceed the second preset value, the readout module 102 is configured to transmit an opposite value of the data in the first local data line LIO to the second global data line YIO —, and/or transmit an opposite value of the data in the second local data line LIO-to the first global data line YIO.
In one example, referring to fig. 8, the readout module 102 includes: a fifth MOS transistor 405, a sixth MOS transistor 406, a seventh MOS transistor 407, an eighth MOS transistor 408, a ninth MOS transistor 409, a tenth MOS transistor 410, an eleventh MOS transistor 411, a twelfth MOS transistor 412, a thirteenth MOS transistor 413, and a fourteenth MOS transistor 414.
The gate of the thirteenth MOS transistor 413 is connected to the first local data line LIO, the drain is connected to the second global data line YIO ", and the source is connected to the drain of the seventh MOS transistor 407; the gate of the fifth MOS transistor 405 is connected to the second local data line LIO-, the drain is connected to the second global data line YIO-, and the source is connected to the drain of the eighth MOS transistor 408; the gate of the seventh MOS transistor 407 is connected to the fifth control signal 1 "more" -, the source is connected to the drain of the eleventh MOS transistor 411, and the second control signal 1 "more" and the fifth control signal 1 "more" -are opposite signals; the gate of the eighth MOS transistor 408 is connected to the second control signal 1 "more", and the source is connected to the drain of the eleventh MOS transistor 411; the gate of the eleventh MOS 411 receives the read enable signal ReadEnable, and the source is grounded to GND (not shown); the gate of the fourteenth MOS 414 is connected to the second local data line LIO-, the drain is connected to the first global data line YIO, and the source is connected to the drain of the ninth MOS 409; the gate of the sixth MOS transistor 406 is connected to the first local data line LIO, the drain is connected to the first global data line YIO, and the source is connected to the drain of the tenth MOS transistor 410; the gate of the ninth MOS transistor 409 is connected to the fifth control signal 1 "more" -, and the source is connected to the drain of the twelfth MOS transistor 412; the gate of the tenth MOS transistor 410 is connected to the second control signal 1 "more", and the source is connected to the drain of the twelfth MOS transistor 412; the gate of the twelfth MOS transistor 412 receives the read enable signal ReadEnable, and the source is grounded to GND (not shown).
For the above conversion circuit, when the read enable signal ReadEnable is 0, it is equivalent to turning off the readout module 102, and the circuit cannot work; when the read enable signal ReadEnable is 1, the operation principle is as follows:
when the second control signal 1 "more" is 1, the fifth control signal 1 "more" -is 0, which corresponds to turning on only the intermediate circuit, representing that the opposite value of the data in the first local data line LIO is transferred to the first global data line YIO, and the opposite value of the data in the second local data line LIO-is transferred to the second global data line YIO-. When the first local data line LIO is 1, the sixth MOS transistor 406 is turned on, and at this time, the first global data line YIO is grounded, and the first global data line YIO is 0, so that the opposite value of the data in the first local data line LIO is transmitted to the first global data line YIO; when the second local data line LIO-is 1, the fifth MOS transistor 405 is turned on, and the second global data line YIO-is grounded, and the second global data line YIO-is 0, so that the opposite value of the data in the second local data line LIO-is transmitted to the second global data line YIO-.
When the second control signal 1 'more' is 0, the fifth control signal 1 'more' -is 1, which is equivalent to turning on only the edge circuit, representing that the opposite value of the data in the first local data line LIO is transferred to the second global data line YIO-, and the opposite value of the data in the second local data line LIO-is transferred to the first global data line YIO. When the first local data line LIO is 1, the thirteenth MOS transistor 413 is turned on, and at this time, the second global data line YIO-is grounded, and the second global data line YIO-is 0, so that the opposite value of the data in the first local data line LIO-is transmitted to the second global data line YIO —; when the second local data line LIO-is 1, the fourteenth MOS 414 is turned on, and at this time, the first global data line YIO is grounded, and the first global data line YIO is 0, so that the opposite value of the data in the second local data line LIO-is transmitted to the first global data line YIO.
It should be noted that the terms "source" or "drain" in the fifth MOS transistor 405, the sixth MOS transistor 406, the seventh MOS transistor 407, the eighth MOS transistor 408, the ninth MOS transistor 409, the tenth MOS transistor 410, the eleventh MOS transistor 411, the twelfth MOS transistor 412, the thirteenth MOS transistor 413, and the fourteenth MOS transistor 414 are only used to distinguish the ports of the MOS transistors, and are not limited at all, that is, the concepts of source and drain may be interchanged.
Compared with the related art, the first control signal is obtained by comparing the data difference between the external data line and the first global data line, and whether the data of the external data line is transmitted to the first global data line or the second global data line is judged, so that the data turnover frequency in the data transmission process is reduced, and the power consumption of data transmission is saved; acquiring a second control signal by comparing the number of low-level data and high-level data in an external data line, and acquiring a third control signal by the first control signal and the second control signal to judge whether the data of the first global data line is transmitted to the first local data line or the second local data line, and/or whether the data of the second global data line is transmitted to the first local data line or the second local data line, so as to ensure the reliability of data storage and readout; and judging whether the data of the first local data line or the second local data line is transmitted to an external data line during reading by acquiring the second control signal so as to ensure that the read data is the data originally written into the memory.
It should be noted that, in this embodiment, all units are logic units, and in practical application, one logic unit may be one physical unit, may also be a part of one physical unit, and may also be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, a unit that is not so closely related to solving the technical problem proposed by the present application is not introduced in the present embodiment, but this does not indicate that there is no other unit in the present embodiment.
The present application further relates to a data transmission line, and different from the first embodiment, the present embodiment provides another circuit implementation manner of a readout module, so as to further improve the data reading efficiency.
Fig. 9 and fig. 10 are schematic structural diagrams of the double-ended data transmission circuit provided in this embodiment, and fig. 11 is a schematic circuit diagram of the readout module provided in this embodiment; the following will describe the dual-ended data transmission circuit provided in this embodiment in detail with reference to the accompanying drawings, and details of the same or corresponding parts as those in the above embodiments will not be described below.
Referring to fig. 9 and 10, the readout module 102 is connected to the first global data line YIO, the second global data line YIO-, and the external data line DataBus, and controls data transmission among the first global data line YIO, the second global data line YIO-, and the external data line DataBus according to the second control signal 1 "more".
If the number of bits occupied by the high-level data exceeds the second preset value, the readout module 102 is configured to transmit an opposite value of the data in the first global data line YIO to the external data line DataBus, and/or transmit the data in the second global data line YIO-to the external data line DataBus; if the number of bits occupied by the high level data does not exceed the second preset value, the readout module 102 is configured to transmit the data in the first global data line YIO to the external data line DataBus and/or transmit the opposite value of the data in the second global data line YIO-to the external data line DataBus.
In one example, referring to fig. 11, the readout module 102 includes: a first transmission element 301 having one end connected to the first global data line YIO and the other end connected to the external data line DataBus; a second transmission element 302 having one end connected to the second global data line YIO "and the other end connected to the external data line DataBus; the first transmission element 301 and the second transmission element 302 are further configured to receive a second control signal 1 "more" for turning on the first transmission element 301 or the second transmission element 302 according to the second control signal 1 "more".
In this embodiment, the first transmission element 301 and the second transmission element 302 are controlled to be turned on at a low level, which is specifically as follows: when the second control signal 1 "more" is 1, the first transmission element turns on the signal transmission line, and at this time, the first global data line YIO is connected to the external data line DataBus, so that the first global data line YIO transmits the transmitted data to the external data line DataBus; the second transmission element 302 turns off the signal transmission line. When the second control signal 1 "more" is 0, the first transmission element 301 turns off the signal transmission line, the second transmission element 302 turns on the signal transmission line, and the second global data line YIO-is connected to the external data line DataBus, so that the second global data line YIO-transmits the transmitted data to the external data line DataBus.
Compared with the prior art, the first control signal is obtained by comparing the data difference between the external data line and the first global data line, and whether the data of the external data line is transmitted to the first global data line or the second global data line is judged, so that the data overturning frequency in the data transmission process is reduced, and the power consumption of data transmission is saved; acquiring a second control signal by comparing the number of low-level data and high-level data in an external data line, and acquiring a third control signal by the first control signal and the second control signal to judge whether the data of the first global data line is transmitted to the first local data line or the second local data line, and/or whether the data of the second global data line is transmitted to the first local data line or the second local data line, so as to ensure the reliability of data storage and readout; and judging whether the data of the first local data line or the second local data line is transmitted to an external data line during reading by acquiring the second control signal so as to ensure that the read data is the data originally written into the memory.
It should be noted that, in this embodiment, all units are logic units, and in practical application, one logic unit may be one physical unit, may also be a part of one physical unit, and may also be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, a unit that is not so closely related to solving the technical problem proposed by the present application is not introduced in the present embodiment, but this does not indicate that there is no other unit in the present embodiment.
Since the above embodiments correspond to the present embodiment, the present embodiment can be implemented in cooperation with the above embodiments. Related technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects that can be achieved in the above embodiments can also be achieved in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments.
Another embodiment of the present application relates to a memory, including the data transmission circuit provided in the foregoing embodiment, further including: and the memory unit is connected with the first local data line and the second local data line, and the first local data line and the second local data line are used for writing data into the memory unit and reading data out of the memory unit.
Fig. 12 and fig. 13 are schematic structural diagrams of the memory provided in the present embodiment; the memory provided in the present embodiment is described in further detail below with reference to the accompanying drawings.
Referring to fig. 12, a memory 500 includes:
the first global data line YIO and the second global data line YIO-, which are differential data transmission lines, the first global data line YIO and the second global data line YIO-transmit signals that are opposite in phase to each other.
The first local data line LIO and the second local data line LIO-of the differential data transmission lines transmit signals which are opposite in phase.
By providing the first local data line LIO, the second local data line LIO-, and the first global data line YIO and the second global data line YIO-for transmitting differential data, stability of data inversion between the first local data line LIO and the second local data line LIO-and the first global data line YIO and the second global data line YIO-is ensured.
A conversion module 101 connected among the external data line DataBus, the first global data line YIO and the second global data line YIO-, and configured to control data transmission between the external data line DataBus and the first global data line YIO and/or the second global data line YIO-according to a first control signal Flag; the first control signal Flag is used to indicate whether the difference bit number between the data currently transmitted by the external data line DataBus and the data currently transmitted by the first global data line YIO exceeds a first preset value.
For the conversion module 101, if the difference between the data currently transmitted by the external data line DataBus and the data currently transmitted by the first global data line YIO exceeds a first preset value, the conversion module 101 is configured to transmit the data in the external data line DataBus to the second global data line YIO-; if the difference between the currently transmitted data of the external data line DataBus and the currently transmitted data of the first global data line YIO does not exceed the first preset value, the conversion module 101 is configured to transmit the data in the external data line DataBus to the first global data line YIO.
And the statistical module 112 is connected with the external data line DataBus and is used for outputting a second control signal 1 'more', wherein the second control signal 1 'more' is used for representing, and whether the bit number occupied by high-level data in the external data line DataBus exceeds a second preset value or not.
In addition, the second control signal 1 "more" is stored as flag bit data in the memory cell to read out the second control signal 1 "more" in the process of reading out data.
A write module 103 connected between the first local data line LIO, the second local data line LIO-, the first global data line YIO and the second global data line YIO-, controlling the data in the first global data line YIO and/or the second global data line YIO-to be transmitted to the first local data line LIO and/or the second local data line LIO-, and determining, based on a third control signal WrEn, whether to transmit the data in the first global data line YIO to the first local data line LIO and the data in the second global data line YIO-to the second local data line LIO-, or to transmit the data in the first global data line YIO to the second local data line LIO-and the data in the second global data line YIO-to the first local data line LIO; wherein the third control signal WrEn is used to represent whether the value of the first control signal Flag and the value of the second control signal 1 "more" are the same.
The enable control module 133 is configured to receive the first control signal Flag and the second control signal 1 "more", and output a third control signal indicating whether the first control signal Flag and the second control signal 1 "more" are the same; the second control signal 1 "more" is used to represent whether the bit number occupied by the high-level data in the external data line DataBus exceeds a second preset value.
The readout module 102 is configured to control data transmission among the first local data line LIO, the second local data line LIO-, and the external data line DataBus according to the read second control signal 1 "more", and if the bit number occupied by the high-level data exceeds a second preset value, the readout module 102 is configured to finally transmit data in the second local data line LIO-to the external data line DataBus; if the number of bits occupied by the high-level data does not exceed the second preset value, the readout module 102 is configured to finally transmit the data in the first local data line LIO to the external data line DataBus.
With continued reference to fig. 12, the readout module 102 is connected between the first and second local data lines LIO and LIO-, the first and second global data lines YIO and YIO-, for controlling data transmission between the first and second local data lines LIO and LIO-and the first and second global data lines YIO and YIO-according to the second control signal 1 "more".
If the number of bits occupied by the high level data exceeds the second preset value, the readout module 102 is configured to transmit an opposite value of the data in the first local data line LIO to the first global data line YIO, and/or transmit an opposite value of the data in the second local data line LIO-to the second global data line YIO-; if the number of bits occupied by the high level data does not exceed the second preset value, the readout module 102 is configured to transmit an opposite value of the data in the first local data line LIO to the second global data line YIO —, and/or transmit an opposite value of the data in the second local data line LIO-to the first global data line YIO.
Referring to fig. 13, the readout module 102 is connected to the first global data line YIO, the second global data line YIO-, and the external data line DataBus, and controls data transmission among the first global data line YIO, the second global data line YIO-, and the external data line DataBus according to the second control signal 1 "more".
If the number of bits occupied by the high-level data exceeds the second preset value, the readout module 102 is configured to transmit an opposite value of the data in the first global data line YIO to the external data line DataBus, and/or transmit the data in the second global data line YIO-to the external data line DataBus; if the number of bits occupied by the high level data does not exceed the second preset value, the readout module 102 is configured to transmit the data in the first global data line YIO to the external data line DataBus and/or transmit the opposite value of the data in the second global data line YIO-to the external data line DataBus.
It should be noted that, in this embodiment, the first local data line LIO and the second local data line LIO — connection storage unit 501 includes: direct connection and indirect connection. In the present embodiment, the first local data line LIO and the second local data line LIO — are not directly connected to the memory cell 501, but the memory cell 501 is actually connected to a bit line BitLine, which is connected to the first local data line LIO and the second local data line LIO — by column selection.
Compared with the related art, the first control signal is obtained by comparing the data difference between the external data line and the first global data line, and whether the data of the external data line is transmitted to the first global data line or the second global data line is judged, so that the data turnover frequency in the data transmission process is reduced, and the power consumption of data transmission is saved; acquiring a second control signal by comparing the number of low-level data and high-level data in an external data line, and acquiring a third control signal by the first control signal and the second control signal to judge whether the data of the first global data line is transmitted to the first local data line or the second local data line, and/or whether the data of the second global data line is transmitted to the first local data line or the second local data line, so as to ensure the reliability of data storage and readout; and judging whether the data of the first local data line or the second local data line is transmitted to an external data line during reading by acquiring the second control signal so as to ensure that the read data is the data originally written into the memory.
It should be noted that, in this embodiment, all units are logic units, and in practical application, one logic unit may be one physical unit, may also be a part of one physical unit, and may also be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, a unit that is not so closely related to solving the technical problem proposed by the present application is not introduced in the present embodiment, but this does not indicate that there is no other unit in the present embodiment.
Since the above embodiments correspond to the present embodiment, the present embodiment can be implemented in cooperation with the above embodiments. Related technical details mentioned in the above embodiments are still valid in this embodiment, and the technical effects that can be achieved in the above embodiments can also be achieved in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice.
Claims (19)
1. A dual ended data transfer circuit for writing data to and reading data from a memory cell, comprising:
the first global data line and the second global data line are mutually differential data transmission lines, and the first global data line and the second global data line transmit signals which are mutually opposite in phase;
the first local data line and the second local data line are mutually differential data transmission lines, and the first local data line and the second local data line transmit signals which are mutually opposite in phase;
the conversion module is connected among an external data line, the first global data line and the second global data line and is used for controlling data transmission between the external data line and the first global data line and/or the second global data line according to a first control signal, wherein the first control signal is used for representing whether the difference bit number of the currently transmitted data of the external data line and the currently transmitted data of the first global data line exceeds a first preset value; if the difference bit number exceeds the first preset value, the conversion module is configured to transmit data in the external data line to the second global data line; if the difference bit number does not exceed the first preset value, the conversion module is configured to transmit data in the external data line to the first global data line;
the enabling control module is used for receiving the first control signal and the second control signal and outputting a third control signal for representing whether the first control signal and the second control signal are the same or not; the second control signal is used for representing whether the bit number occupied by high-level data in the external data line exceeds a second preset value;
and the writing module is connected among the first local data line, the second local data line, the first global data line and the second global data line, controls data in the first global data line and/or the second global data line to be transmitted to the first local data line and/or the second local data line, and judges whether to transmit data in the first global data line to the first local data line and data in the second global data line to the second local data line or transmit data in the first global data line to the second local data line and data in the second global data line to the first local data line based on a third control signal.
2. The double ended data transmission circuit of claim 1, wherein said write module comprises:
a first conversion circuit configured to control data in the first global data line to be transferred to the first local data line or to control data in the second global data line to be transferred to the first local data line;
a second conversion circuit configured to control data in the first global data line to be transferred to the second local data line or to transfer data in the second global data line to the second local data line.
3. The double ended data transmission circuit of claim 2, wherein the first switching circuit comprises: the MOS transistor comprises a first MOS transistor and a second MOS transistor;
the grid electrode of the first MOS tube receives the third control signal, the source electrode of the first MOS tube is connected with the first global data line, and the drain electrode of the first MOS tube is connected with the first local data line;
the gate of the second MOS transistor receives a fourth control signal, the source is connected to the second global data line, the drain is connected to the first local data line, and the third control signal and the fourth control signal are opposite-phase signals.
4. The double ended data transmission circuit of claim 2, wherein said second switching circuit comprises: a third MOS transistor and a fourth MOS transistor;
a grid electrode of the third MOS tube receives a fourth control signal, a source electrode of the third MOS tube is connected with the first global data line, a drain electrode of the third MOS tube is connected with the second local data line, and the third control signal and the fourth control signal are mutually opposite-phase signals;
and the grid electrode of the fourth MOS tube receives the third control signal, the source electrode of the fourth MOS tube is connected with the second global data line, and the drain electrode of the fourth MOS tube is connected with the second local data line.
5. The double ended data transmission circuit of claim 1, further comprising: and the counting module is connected with the external data line and used for outputting the second control signal, and the second control signal is stored in the storage unit as marking bit data so as to read the second control signal in the data reading process.
6. The double ended data transmission circuit of claim 5, further comprising: the read-out module is used for controlling data transmission among the first local data line, the second local data line and the external data line according to the read-out second control signal; if the bit number occupied by the high-level data exceeds the second preset value, the reading module is configured to finally transmit the data in the second local data line to the external data line; if the bit number occupied by the high-level data does not exceed the second preset value, the reading module is configured to finally transmit the data in the first local data line to the external data line.
7. The circuit of claim 6, wherein the readout module is connected between the first local data line, the second local data line, the first global data line, and the second global data line, and configured to control data transmission between the first local data line, the second local data line, and the first global data line, and the second global data line according to a second control signal, and if the occupied bit number of the high-level data exceeds the second preset value, the readout module is configured to transmit an opposite value of data in the first local data line to the first global data line, and/or transmit an opposite value of data in the second local data line to the second global data line; if the bit number occupied by the high-level data does not exceed the second preset value, the reading module is configured to transmit the opposite value of the data in the first local data line to the second global data line and/or transmit the opposite value of the data in the second local data line to the first global data line.
8. The double ended data transmission circuit of claim 7, wherein said readout module comprises: a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor and a fourteenth MOS transistor;
the grid electrode of the thirteenth MOS tube is connected with the first local data line, the drain electrode of the thirteenth MOS tube is connected with the second global data line, and the source electrode of the thirteenth MOS tube is connected with the drain electrode of the seventh MOS tube;
the grid electrode of the fifth MOS tube is connected with the second local data line, the drain electrode of the fifth MOS tube is connected with the second global data line, and the source electrode of the fifth MOS tube is connected with the drain electrode of the eighth MOS tube;
the grid electrode of the seventh MOS tube is connected with a fifth control signal, the source electrode of the seventh MOS tube is connected with the drain electrode of the eleventh MOS tube, and the second control signal and the fifth control signal are mutually inverse signals;
the grid electrode of the eighth MOS tube is connected with the second control signal, and the source electrode of the eighth MOS tube is connected with the drain electrode of the eleventh MOS tube;
a grid electrode of the eleventh MOS tube receives a read enabling signal, and a source electrode of the eleventh MOS tube is grounded;
the grid electrode of the fourteenth MOS tube is connected with the second local data line, the drain electrode of the fourteenth MOS tube is connected with the first global data line, and the source electrode of the fourteenth MOS tube is connected with the drain electrode of the ninth MOS tube;
the grid electrode of the sixth MOS tube is connected with the first local data line, the drain electrode of the sixth MOS tube is connected with the first global data line, and the source electrode of the sixth MOS tube is connected with the drain electrode of the tenth MOS tube;
the grid electrode of the ninth MOS tube is connected with the fifth control signal, and the source electrode of the ninth MOS tube is connected with the drain electrode of the twelfth MOS tube;
the grid electrode of the tenth MOS tube is connected with the second control signal, and the source electrode of the tenth MOS tube is connected with the drain electrode of the twelfth MOS tube;
and the grid electrode of the twelfth MOS tube receives a read enabling signal, and the source electrode of the twelfth MOS tube is grounded.
9. The dual-ended data transmission circuit of claim 6, wherein the readout module is connected to the first global data line, the second global data line and the external data line, and configured to control data transmission between the first global data line, the second global data line and the external data line according to a second control signal, and if the occupied bit number of the high-level data exceeds the second preset value, the readout module is configured to transmit an opposite value of data in the first global data line to the external data line and/or transmit data in the second global data line to the external data line; if the bit number occupied by the high-level data does not exceed the second preset value, the reading module is configured to transmit the data in the first global data line to the external data line and/or transmit the opposite value of the data in the second global data line to the external data line.
10. The double ended data transmission circuit of claim 9, wherein said readout module comprises:
one end of the first transmission element is connected with the first global data line, and the other end of the first transmission element is connected with the external data line;
a second transmission element, one end of which is connected with the second global data line and the other end of which is connected with the external data line;
the first transmission element and the second transmission element are further configured to receive the second control signal, and to turn on the first transmission element or the second transmission element according to the second control signal.
11. The double ended data transmission circuit of claim 6, wherein said second preset value is 50% of the number of bits of data transmitted by said external data line.
12. The double ended data transmission circuit of claim 1, wherein said conversion module comprises:
a third transmission element, one end of which is connected with the external data line through a phase inverter, and the other end of which is connected with the first global data line;
a fourth transmission element, one end of which is connected with the external data line and the other end of which is connected with the first global data line;
the third transmission element and the fourth transmission element are further configured to receive the first control signal, and to selectively turn on the third transmission element or the fourth transmission element according to the first control signal.
13. The double ended data transmission circuit of claim 1, further comprising: and the comparison module is connected with the external data line and the first global data line and used for generating the first control signal according to whether the difference digit of the data currently transmitted by the external data line and the data currently transmitted by the first global data line exceeds a first preset value.
14. The double ended data transmission circuit of claim 13, wherein said comparison module comprises:
the detection unit is used for connecting the external data line and the first global data line, detecting currently transmitted data of the external data line and currently transmitted data of the first global data line bit by bit, generating a first sub-control signal if the currently transmitted data of the external data line is different from the currently transmitted data of the first global data line, and generating a second sub-control signal if the currently transmitted data of the external data line is the same as the currently transmitted data of the first global data line;
and an obtaining unit, connected to the detecting unit, configured to obtain the first sub-control signal and the second sub-control signal, and if the number of the first sub-control signals exceeds the first preset value, generate the first control signal, where the first preset value is a preset percentage of a sum of the number of the first sub-control signals and the number of the second sub-control signals.
15. The double ended data transmission circuit of claim 14, wherein said predetermined percentage is 50%.
16. The double ended data transmission circuit of claim 1, wherein said enable control module comprises: the first enabling control module is used for generating the third control signal according to the first control signal and the second control signal.
17. The dual ended data transmission circuit of claim 16, wherein the first enable control module is further configured to receive a write enable signal and generate the third control signal if the write enable signal is active.
18. The double ended data transmission circuit of claim 16, wherein said enable control module further comprises: the second enable control module is configured to receive the first control signal, the second control signal, and an inverted signal of the write enable signal, and generate a fourth control signal if the inverted signal of the write enable signal is an active level, where the third control signal and the fourth control signal are inverted signals.
19. A memory comprising the double-ended data transmission circuit as claimed in any one of claims 1 to 18, further comprising: and the first local data line and the second local data line are used for writing data into the memory cell and reading data out of the memory cell.
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| CN212032138U (en) * | 2020-06-05 | 2020-11-27 | 长鑫存储技术(上海)有限公司 | Read-write conversion circuit and memory |
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| US5715210A (en) * | 1995-09-29 | 1998-02-03 | Samsung Electronics Co., Ltd. | Low power semiconductor memory device |
| US20110211407A1 (en) * | 2010-02-26 | 2011-09-01 | Elite Semiconductor Memory Technology Inc. | Semiconductor memory device and associated local sense amplifier |
| CN102870159A (en) * | 2010-04-26 | 2013-01-09 | 莫塞德技术公司 | Write scheme in phase change memory |
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