CN112840309A

CN112840309A - Command scheduling method, device and storage medium

Info

Publication number: CN112840309A
Application number: CN201880098676.5A
Authority: CN
Inventors: 裘来彬; 周杰; 苏杰; 李渠
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-10-15
Filing date: 2018-10-15
Publication date: 2021-05-25
Anticipated expiration: 2038-10-15
Also published as: WO2020077495A1; CN112840309B

Abstract

A command scheduling method for use in a UFS chip is used to schedule commands located in a command queue. The command scheduling method comprises the following steps: starting a timer when the read command in the command queue is available from the beginning, wherein the timer counts time before being cleared; after the execution of each write command is finished, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the scheduling command queue are preferentially executed, so that the read commands in the command queue are scheduled more quickly, and the normal operation of the host is ensured.

Description

Command scheduling method, device and storage medium

Technical Field

The present disclosure relates to communications technologies, and in particular, to a method and an apparatus for scheduling commands, and a storage medium.

Background

Generally, to ensure that power is not lost, the terminal device usually has a power-down nonvolatile storage medium built therein. Currently, the mainstream power-down nonvolatile Storage medium is a Universal Flash Storage (UFS) chip. In application, the host Computer performs read/write operations on the UFS chip through a Small Computer System Interface (SCSI) command defined by the UFS protocol. In particular, the UFS protocol provides a command queue of depth 32, i.e., the host can send up to 32 SCSI commands to the UFS chip simultaneously. The SCSI commands include read commands and write commands, among others.

For the SCSI commands in the command queue, the UFS chip processes according to a First-in First-out (FIFO) strategy, and processes the SCSI commands received First in priority. In addition, in the UFS chip application, the execution speed of the read command is much faster than the execution speed of the write command; moreover, it is generally desirable for the host to respond faster to read commands. Therefore, if a read command is located in the rear part of the command queue according to the FIFO policy, for example, the read command is located in the 29 th bit of the command queue, the delay of the read command is superimposed by the delay of the first 28 SCSI commands, which causes a large delay and affects the operation of the host.

Disclosure of Invention

The embodiment of the application provides a command scheduling method, a command scheduling device and a storage medium, so that read commands in a command queue can be scheduled more quickly, and normal operation of a host is guaranteed.

In a first aspect, an embodiment of the present application provides a command scheduling method, configured to schedule a command in a command queue, including: starting a timer when the read command in the command queue is available from the beginning, wherein the timer counts time before being cleared; after the execution of each write command is finished, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be preferentially executed.

When receiving a SCSI command, the UFS controller generates an interrupt signal, and in the effective process of the interrupt signal, the counter judges the type of the SCSI command currently received: and a read command or a write command, and when the currently received SCSI command is the read command, the counter is increased by 1. Note that the initial value of the counter is 0.

When the counter changes from 0 to 1, indicating that a read command is present in the command queue, the UFS controller starts a timer to time the first read command present in the command queue.

Optionally, the counter is decremented by 1 each time a read command in the command queue is scheduled to be executed preferentially.

The preset value can be set according to historical experience values or actual requirements.

In the process, when the read commands in the command queue are from nonexistence to existent, the timer is started, and after the execution of each write command is finished, when the read commands exist in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be preferentially executed, so that the response efficiency of the read commands in the UFS chip is improved, the time delay of the read commands in the command queue is reduced, and the normal operation of a host is ensured.

In a possible implementation, the command scheduling method may further include: after the execution of each write command is finished, when the read command does not exist in the command queue, or when the read command exists in the command queue but the value of the timer does not exceed the preset value, the commands in the command queue are executed by using the FIFO strategy. The scheme takes the characteristic that the time length of the UFS controller for executing the write command is longer than the time length of the read command into consideration, reduces the time delay of the read command after the write command when a large number of write commands exist in a command queue, and ensures that the read command can be quickly responded. In addition, because the execution speed of the read command is high, even if all the read commands in the command queue are scheduled preferentially, the write commands in the command queue are not subjected to large time delay.

Optionally, the duration of executing the write command is longer than the duration of executing the read command, so that all read commands in the command queue are scheduled preferentially, the time delay of the read command is reduced, and the response efficiency of the write command in the command queue is ensured.

In some embodiments, after all the read commands in the scheduling command queue are preferentially executed, the command scheduling method may further include: and executing other commands to be processed in the command queue according to the FIFO strategy.

After all the read commands in the command queue are preferentially executed, other commands to be processed in the command queue are executed according to the FIFO strategy, so that only the read commands which are currently put into the command queue are processed, and the newly-entered read commands cannot be preferentially scheduled in the processing process, so that the write commands which have originally entered the command queue cannot be blocked by the read commands which do not enter ceaselessly. And after the read commands in the command queue are completely executed, switching back to the FIFO strategy again, and ensuring that the write commands entering the command queue can be executed faster, so that the total time delay of the write commands is not particularly long, the time delay of the read commands can be reduced, the blockage that the write commands are scheduled due to the fact that the read priority strategy is adopted only can be avoided, and the execution of the read commands and the write commands in the command queue is ensured at the same time.

Further, since the host may issue SCSI commands all the time, or new SCSI commands enter all the time during the SCSI commands in the command queue are executed, the command scheduling method may further include: the UFS controller obtains a command to be processed sent by a host; and placing the commands to be processed into a command queue according to the sequence, and executing according to the FIFO strategy.

Optionally, after the execution of each write command is completed, when it is determined that a read command exists in the command queue and the value of the timer exceeds the preset value, before all read commands in the scheduling command queue are preferentially executed, the command scheduling method may further include: clearing or closing the timer. Through the scheme, the validity of the timing function of the timer is guaranteed. Further, when the read command in the command queue is from none to some time, the timer is started again, and the process is iterated.

In a second aspect, an embodiment of the present application provides a command scheduling apparatus, configured to schedule a command located in a command queue, including: and a processing module. Wherein,

the processing module is used for starting a timer when the read command in the command queue is available from none, wherein the timer counts time before being cleared; and after the execution of each write command is finished, when the read command is judged to exist in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be preferentially executed.

The command scheduler may be the UFS chip or a UFS controller within the UFS chip.

In a possible implementation, the processing module may be further configured to: after the execution of each write command is finished, when the read command does not exist in the command queue, or when the read command exists in the command queue but the value of the timer does not exceed the preset value, the commands in the command queue are executed by using the FIFO strategy.

In one possible implementation, the write command is executed for a duration greater than a duration of the read command.

In a possible implementation, the processing module may be further configured to: after all read commands in the scheduling command queue are preferentially executed, other commands to be processed in the command queue are executed according to the FIFO strategy.

In a possible implementation, the processing module may be further configured to: acquiring a command to be processed sent by a host; and placing the commands to be processed into a command queue according to the sequence, and executing according to the FIFO strategy.

In a possible implementation, the processing module may be further configured to: after the execution of each write command is finished, when the read command exists in the command queue and the value of the timer exceeds the preset value, clearing or closing the timer before all the read commands in the scheduling command queue are preferentially executed.

In a third aspect, an embodiment of the present application provides a command scheduling apparatus, configured to schedule a command located in a command queue. The command scheduling apparatus includes: a memory and a processor, and a computer program stored on the memory for execution by the processor. When the computer program is read and executed by a processor, the processor is caused to perform the following operations:

starting a timer when the read command in the command queue is available from the beginning, wherein the timer counts time before being cleared; and after the execution of each write command is finished, when the read command is judged to exist in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be preferentially executed.

The command scheduler may be the UFS chip or a UFS controller within the UFS chip. The processor here may be embodied as a CPU in the UFS controller.

Based on the same inventive concept, since the principle of the command scheduling apparatus to solve the problem corresponds to the scheme in the method design of the first aspect, the implementation of the command scheduling apparatus may refer to the implementation of the method, and repeated details are not repeated.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, in which a computer program is stored, the computer program including at least one piece of code, the at least one piece of code being executable by a processor to implement the method according to any one of the first aspect.

In a fifth aspect, an embodiment of the present application provides a UFS chip, including: UFS controllers and Nand Flash particles. Wherein the UFS controller includes a processor and a memory. The memory has stored thereon a computer program executable by the processor; when the computer program is read and executed by a processor, the processor is caused to perform the method of any of the first aspects above.

Alternatively, the memory may include at least one of a ROM and a RAM.

Optionally, the UFS chip may further include: UFS interface, Nand interface, and other related hardware modules.

In a sixth aspect, an embodiment of the present application provides an electronic device, including: the UFS chip of the fifth aspect.

In a seventh aspect, an embodiment of the present application provides a program, which when executed by a UFS controller of a UFS chip, is configured to perform the method of any of the above first aspects.

In an eighth aspect, an embodiment of the present application provides a computer program product, including the program of the seventh aspect.

These and other aspects of the present application will be more readily apparent from the following description of the embodiment(s).

Drawings

Fig. 1 is a schematic structural diagram of a UFS chip according to an embodiment of the present disclosure;

FIG. 2 is a diagram illustrating a command queue according to an embodiment of the present disclosure;

fig. 3 is a schematic flow chart of a command scheduling method according to an embodiment of the present application;

fig. 4 is another schematic flow chart of a command scheduling method according to an embodiment of the present application;

FIG. 5 is a diagram of an application example of a command scheduling method according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a command scheduling apparatus according to an embodiment of the present application;

fig. 7 is another schematic structural diagram of a command scheduling apparatus according to an embodiment of the present application.

Detailed Description

Fig. 1 is a schematic structural diagram of a UFS chip according to an embodiment of the present application. Referring to fig. 1, the UFS chip includes a UFS controller and Nand Flash particles, and a Central Processing Unit (CPU), a Read-Only Memory (ROM), a Random Access Memory (RAM), a UFS interface, a Nand interface, and other related hardware modules are integrated in the UFS controller.

The UFS controller interacts SCSI commands based on UFS protocol with the host through UFS interface, and puts the received SCSI commands into command queue. In addition, the UFS controller completes the analysis and processing of the SCSI command, and realizes the read-write operation of Nand Flash particles and the like by matching with a Nand interface.

The Firmware (Firmware) of the UFS chip mainly solves the problems of bad blocks, Data Retention (Data Retention), reading interference and the like inherent to Nand Flash particles, improves the use reliability of the Nand Flash particles, and shields the differences of the Nand Flash particles brought by various manufacturers and processes for a Host (Host).

As mentioned above, in application, the host performs read/write operations on the UFS chip through SCSI commands defined by the UFS protocol. At most 32 SCSI commands can be grouped into a command queue of 32 depth, wherein the command queue is schematically shown in FIG. 2. When the SCSI command in the command queue includes a read command and a write command, in order to schedule the read command in the command queue faster and ensure normal operation of the host, embodiments of the present application provide a command scheduling method, an apparatus, and a storage medium. The command scheduling method is explained as an example below.

Fig. 3 is a flowchart of a command scheduling method according to an embodiment of the present application. The embodiment of the application provides a command scheduling method, which is used for scheduling commands in a command queue, and the command scheduling method can be executed by a command scheduling device, and the command scheduling device can be realized in a hardware and/or software mode. Illustratively, the command scheduler may be firmware of the UFS chip, or the command scheduler may be the UFS controller. The UFS controller will be described as an execution subject.

Referring to fig. 3, the command scheduling method in the embodiment of the present application includes the following steps:

s301, starting a timer when the read command in the command queue is available from the beginning.

Wherein the timer counts until cleared.

In practical application, the host issues SCSI commands to the UFS chip, and the UFS chip counts the number of read commands in the SCSI commands issued by the host through a counter. When receiving a SCSI command, the UFS controller generates an interrupt signal, and in the effective process of the interrupt signal, the counter judges the type of the SCSI command currently received: and a read command or a write command, and when the currently received SCSI command is the read command, the counter is increased by 1. Note that the initial value of the counter is 0.

S302, after the execution of each write command is finished, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be preferentially executed.

In the initial stage, the UFS controller processes according to FIFO strategy. Because the sequence of the read command and the write command is random in the SCSI command issued by the host, but the timer records the detention duration of the first read command in the command queue, the first read command in the command queue may be scheduled to be executed first or may be scheduled to be executed last, and if there are many write commands sequenced in the command queue before the read command, the time delay of the read command is greatly increased.

Therefore, after each write command is executed, the UFS controller first determines whether a read command exists in the command queue, for example, whether the value of the counter is 0, and if the value of the counter is not 0, it indicates that a read command exists in the command queue; further, the UFS controller determines whether the value of the timer exceeds a preset value, and when the value of the timer exceeds the preset value, it indicates that the duration of the first read command in the command queue is longer, and the read command in the command queue needs to be preferentially processed, at this time, a read priority policy is forcibly adopted, so as to avoid the delay of the read command being longer, and ensure the normal operation of the host.

In the embodiment, the timer is started when the read commands in the command queue are available from the beginning, and after the execution of each write command is completed, when the read commands exist in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be preferentially executed, so that the response efficiency of the read commands in the UFS chip is improved, the time delay of the read commands in the command queue is reduced, and the normal operation of the host is ensured.

On the basis of the foregoing embodiment, optionally, the command scheduling method may further include: after the execution of each write command is finished, when the read command does not exist in the command queue, or when the read command exists in the command queue but the value of the timer does not exceed the preset value, the commands in the command queue are executed by using the FIFO strategy.

Specifically, in one implementation, after the write command is executed, when it is determined that there is no read command in the command queue, that is, all the write commands in the command queue are write commands, the commands in the command queue are executed using the FIFO policy.

In another implementation, after the write command is executed, when it is determined that the read command exists in the command queue but the value of the timer does not exceed the preset value, it is indicated that the time for the read command in the command queue to wait to be executed is still short, and scheduling does not need to be performed in advance, and the command in the command queue is executed by using an FIFO policy.

It should be noted that, in the embodiment of the present application, in consideration of the characteristic that the duration (e.g., 30ms) for executing the write command by the UFS controller is longer than the duration (e.g., 2ms) for executing the read command, when there are a large number of write commands in the command queue, the latency of the read command after the write command is reduced, and it is ensured that the read command can be responded quickly. In addition, because the execution speed of the read command is high, even if all the read commands in the command queue are scheduled preferentially, the write commands in the command queue are not subjected to large time delay.

Fig. 4 is another flowchart illustrating a command scheduling method according to an embodiment of the present application. As shown in fig. 4, on the basis of the flow shown in fig. 3, in S302, after the execution of each write command is completed, when it is determined that there is a read command in the command queue and the value of the timer exceeds the preset value, all read commands in the command queue are scheduled to be preferentially executed, and the command scheduling method in this embodiment may further include:

s401, executing other commands to be processed in the command queue according to the FIFO strategy.

If the issue of the new SCSI command in the process that all the read commands are preferentially executed is not considered, after all the read commands in the scheduling command queue are preferentially executed, the remaining other to-be-processed commands in the command queue are write commands, so that the other to-be-processed commands in the command queue are executed according to the FIFO policy.

If considering the issue of the new SCSI command in the process that all the read commands are preferentially executed, after all the read commands in the scheduling command queue are preferentially executed, the remaining other commands to be processed in the command queue include the remaining write commands and the new SCSI command, and the new SCSI command includes the read command and/or the write command, at this time, the other commands to be processed in the command queue are executed according to the FIFO policy first, and when a read command appears in the command queue, S301-S302 are repeated.

In this embodiment, after all the read commands in the command queue are preferentially executed, other commands to be processed in the command queue are executed according to the FIFO policy, so that only the read commands currently placed in the command queue are processed, and the newly entered read commands are not preferentially scheduled in this processing process, so that the write commands that have originally entered the command queue are not blocked by the read commands that have entered without interruption. And after the read commands in the command queue are completely executed, switching back to the FIFO strategy again, and ensuring that the write commands entering the command queue can be executed faster, so that the total time delay of the write commands is not particularly long, the time delay of the read commands can be reduced, the blockage that the write commands are scheduled due to the fact that the read priority strategy is adopted only can be avoided, and the execution of the read commands and the write commands in the command queue is ensured at the same time.

Further, since the host may issue SCSI commands all the time, or new SCSI commands enter all the time during the SCSI commands in the command queue are executed, the command scheduling method may further include: the UFS controller obtains a command to be processed sent by a host; and placing the commands to be processed into a command queue according to the sequence, and executing according to the FIFO strategy. It should be noted that, because of the randomness of issuing SCSI commands, the embodiment of the present application does not limit the execution sequence of the step of "the UFS controller obtains the command to be processed sent by the host" and other steps.

In some embodiments, the scheduling of all read commands in the command queue to be executed preferentially may include: scheduling all read commands in the command queue to a read command queue; and sequentially executing the read commands in the read command queue according to the FIFO strategy. Every time a read command is executed, the counter is decremented by 1 until the value of the counter becomes 0.

Optionally, after the execution of each write command is completed, when it is determined that a read command exists in the command queue and the value of the timer exceeds the preset value, before all read commands in the scheduling command queue are preferentially executed, the command scheduling method may further include: and resetting or closing the timer to ensure the validity of the timing function of the timer. Further, when the read command in the command queue is from none to some time, the timer is started again, and the process is iterated.

Next, the above command scheduling method will be described with reference to specific examples.

Example one

The preset value is set to 40 milliseconds (ms).

Referring to fig. 5, the command scheduling method may include:

the host issues 6 write commands to the UFS chip.

Correspondingly, the UFS chip receives these 6 write commands, i.e., write command W0, write command W1, write command W2, write command W3, write command W4, and write command W5, and puts them into the command queue.

And then, the UFS chip sequentially fetches the write commands to execute by using the FIFO strategy.

In this process, before the UFS chip executes the write command W1 (taken out and not yet started to execute), the host issues the read command R0, the read command R1, and the write command W6.

And the UFS chip determines that the read command in the command queue exists from nothing, starts a timer and starts timing.

The UFS chip executes the write command W1, taking 30 ms. After the write command W1 is executed, the UFS chip determines that there is a read command R1 in the command queue, but the value of the timer is 30ms, and does not exceed the preset value (40ms), and continues to execute the commands in the command queue using the FIFO policy.

The UFS chip executes the write command W2, taking 20 ms. After the write command W2 is executed, the UFS chip determines that there is a read command R1 in the command queue, but the value of the timer is 50ms, and exceeds the preset value (40ms), then all read commands in the command queue are scheduled to be executed preferentially, that is, the read command R0 and the read command R1 are sequentially fetched from the command queue and executed, and the timer is cleared or closed.

And after all the read commands are completely executed, switching the UFS chip back to the FIFO strategy, and sequentially taking out and executing the write command W3, the write command W4, the write command W5 and the write command W6 in the command queue.

Example two

The preset value is set to 40 ms.

The host issues 31 write commands to the UFS chip.

Correspondingly, the UFS chip receives these 31 write commands, i.e., write command W0, write command W1, write command W2, write command W3, write commands W4, … …, write command W30, and puts them into the command queue.

In this process, before the UFS chip executes the write command W0 (which has been taken out and has not yet started to execute), the host issues the read command R0. At this time, the UFS chip determines that there are no read commands in the command queue, starts a timer, and starts timing.

The UFS chip executes the write command W0, taking 25 ms. After the write command W0 is executed, the UFS chip determines that there is a read command R0 in the command queue, but the value of the timer is 25ms, and does not exceed the preset value (40ms), and continues to execute the commands in the command queue using the FIFO policy.

Before the UFS chip executes the write command W1 (fetched and not yet started to execute), the host issues a read command R1.

The UFS chip executes the write command W1, taking 20 ms. After the write command W1 is executed, the UFS chip determines that there are read command R0 and read command R1 in the command queue, but the value of the timer is 45ms, and exceeds the preset value (40ms), then all read commands in the command queue are scheduled to be executed preferentially, that is, the read command R0 and the read command R1 are sequentially fetched from the command queue and the timer is cleared or closed.

In the process of executing the read command R0 and the read command R1, the host issues a read command R2 again, and the UFS chip puts the read command R2 in the command queue. At this time, the UFS chip determines that there are no read commands in the command queue, starts the timer, and restarts the timing.

After the read command R1 is executed, the UFS chip switches back to the FIFO policy, and fetches and executes the write command W2 in the command queue. At this point, the host issues a read command R3.

The UFS chip executes the write command W2, taking 10 ms. After the write command W2 is executed, the UFS chip determines that there are read command R2 and read command R3 in the command queue, but the value of the timer is 10ms, and does not exceed the preset value (40ms), and continues to execute the commands in the command queue using the FIFO policy.

The UFS chip executes the write command W3, taking 20 ms. After the write command W3 is executed, the UFS chip determines that there are read command R2 and read command R3 in the command queue, but the value of the timer is 30ms, and does not exceed the preset value (40ms), and continues to execute the commands in the command queue using the FIFO policy.

The UFS chip executes the write command W4, taking 10 ms. After the write command W4 is executed, the UFS chip determines that there are read command R2 and read command R3 in the command queue, but the value of the timer is 40ms, which is equal to the preset value (40ms), and then schedules all read commands in the command queue to be executed preferentially, that is, sequentially fetches and executes read command R2 and read command R3 from the command queue, and clears or closes the timer.

After the read command R0 and the read command R1 are executed, the UFS chip switches back to the FIFO strategy, and sequentially fetches and executes the write commands W5 to W30 in the command queue.

The embodiment shows that when all read commands are scheduled to be preferentially executed, the newly received read commands are not included in all the read commands scheduled with priority currently, so as to ensure that the phenomena that the write commands are blocked too long and the write commands are overtime due to continuous read command priority scheduling are avoided.

The command scheduling method provided in the embodiment of the present application is described in detail above, and a command scheduling apparatus provided in the embodiment of the present application will be described below.

Fig. 6 is a schematic structural diagram of a command scheduling apparatus according to an embodiment of the present application. The embodiment of the application provides a command scheduling device, which is used for scheduling commands in a command queue. The command scheduling means may be implemented in hardware and/or software. Illustratively, the command scheduler may be firmware of the UFS chip, or the command scheduler may be the UFS controller.

Referring to fig. 6, the command scheduling apparatus 60 in the embodiment of the present application includes: a processing module 61 and a storage module 62. When the processing module 61 executes the computer program stored in the storage module 62, the processing module 61 is caused to implement the steps of:

starting a timer when the read command in the command queue is available from the beginning, wherein the timer counts time before being cleared;

after the execution of each write command is finished, when the read command exists in the command queue and the value of the timer exceeds the preset value, all the read commands in the command queue are scheduled to be preferentially executed.

The command scheduling apparatus of this embodiment may be configured to execute the steps of the command scheduling method provided in the foregoing embodiments, and the specific implementation principle and technical effect are similar, which are not described herein again.

Alternatively, when the processing module 61 executes the above computer program, the processing module 61 is further caused to implement the steps of:

after the execution of each write command is finished, when the read command does not exist in the command queue, or when the read command exists in the command queue but the value of the timer does not exceed the preset value, the commands in the command queue are executed by using the FIFO strategy.

Wherein the duration of executing the write command is longer than the duration of executing the read command.

In some embodiments, when the processing module 61 executes the computer program, the processing module 61 is further caused to: after all read commands in the scheduling command queue are preferentially executed, other commands to be processed in the command queue are executed according to the FIFO strategy.

Further, the processing module 61 may be further configured to: acquiring a command to be processed sent by a host; and placing the commands to be processed into a command queue according to the sequence, and executing according to the FIFO strategy.

Still further, the processing module 61 may be further configured to: after the execution of each write command is finished, when the read command exists in the command queue and the value of the timer exceeds the preset value, clearing or closing the timer before all the read commands in the scheduling command queue are preferentially executed.

Fig. 7 is another schematic structural diagram of a command scheduling apparatus according to an embodiment of the present application. The command scheduling device is used for scheduling commands in the command queue. Referring to fig. 7, the command scheduler 70 includes: a memory 71 and a processor 72, and computer programs (not shown) stored on the memory 71 for execution by the processor. The computer program, when read and executed by the processor 72, causes the processor 72 to perform the steps of any of the method embodiments described above.

The command scheduler may be the UFS chip or a UFS controller within the UFS chip. The processor 72 here may be embodied as a CPU in a UFS controller.

For a detailed description of each module or unit in the command scheduling apparatus and a technical effect brought by each module or unit after executing the method steps of any method embodiment of the present application, reference may be made to the related description in the method embodiment of the present application, and details are not described here again.

An embodiment of the present application provides a UFS chip, including: UFS controller and Nand Flash particles, for example, as shown in fig. 1. Wherein the UFS controller includes a processor and a memory. The memory has stored thereon a computer program executable by the processor; when the computer program is read and executed by a processor, the processor is caused to perform any of the methods described above.

Alternatively, the memory may include at least one of a ROM and a RAM.

An embodiment of the present application provides an electronic device, including: UFS chip as described above. Illustratively, the electronic device may be a smartphone, a tablet computer, a Personal Digital Assistant (PDA), a wearable device, or the like.

Embodiments of the present application provide a computer-readable storage medium, in which a computer program is stored, where the computer program includes at least one code, and the at least one code is executable by a processor to implement the method as described in any one of the above.

Embodiments of the present application provide a program or a computer program product comprising the program, which, when executed by a UFS controller of a UFS chip, is configured to perform any of the methods described above.

It should be understood that the Processor mentioned in the embodiments of the present Application may be a Central Processing Unit (CPU), and may also be other general purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will also be appreciated that the memory referred to in the embodiments of the application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be a ROM, a Programmable Read Only Memory (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash memory. Volatile memory can be RAM, which acts as external cache memory. By way of example, but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (DDR SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchronous link SDRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, a network device or a terminal device, etc.) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

Relevant parts among the method embodiments of the application can be mutually referred; the apparatus provided in the respective apparatus embodiments is adapted to perform the method provided in the respective method embodiments, so that the respective apparatus embodiments may be understood with reference to the relevant parts in the relevant method embodiments.

The device structure diagrams given in the device embodiments of the present application only show simplified designs of the corresponding devices. In practical applications, the apparatus may comprise any number of transmitters, receivers, processors, memories, etc. to implement the functions or operations performed by the apparatus in the embodiments of the apparatus of the present application, and all apparatuses that can implement the present application are within the scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

The word "if" or "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.

It will be understood by those skilled in the art that all or part of the steps in the method for implementing the above embodiments may be implemented by instructing the relevant hardware through a program, which may be stored in a storage medium readable by a device and includes all or part of the steps when executed, such as: FLASH, EEPROM, etc.

The above-mentioned embodiments, which further illustrate the objects, technical solutions and advantages of the present application, it should be understood that various embodiments may be combined, and the above-mentioned embodiments are only examples of the present application and are not intended to limit the scope of the present application, and any combination, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the present application.

Claims

A command scheduling method for scheduling commands in a command queue, comprising:

starting a timer when the read command in the command queue is from absent to present, wherein the timer counts time before being cleared;

after the execution of each write command is finished, when the read command exists in the command queue and the value of the timer exceeds a preset value, scheduling all the read commands in the command queue to be preferentially executed.
The method of claim 1, further comprising:

after the execution of each write command is finished, when the read command does not exist in the command queue, or when the read command exists in the command queue but the value of the timer does not exceed the preset value, executing the commands in the command queue by using a first-in first-out (FIFO) strategy.
The method according to claim 1 or 2,

the duration of executing the write command is greater than the duration of executing the read command.
The method of any of claims 1 to 3, wherein after scheduling all of the read commands in the command queue to be executed first, the method further comprises:

and executing other commands to be processed in the command queue according to a first-in first-out (FIFO) strategy.
The method according to any one of claims 1 to 4, further comprising:

acquiring a command to be processed sent by a host;

and placing the commands to be processed into the command queue according to the sequence, and executing according to a first-in first-out (FIFO) strategy.
The method according to any one of claims 1 to 5, wherein after the execution of each write command is completed, when it is determined that there is a read command in the command queue and the value of the timer exceeds a preset value, before all read commands in the scheduling command queue are preferentially executed, the method further comprises:

clearing or closing the timer.
A command scheduling apparatus for scheduling commands in a command queue, comprising: a memory and a processor, and a computer program stored on the memory for execution by the processor;

when the computer program is read and executed by the processor, the processor is caused to perform the following operations:

starting a timer when the read command in the command queue is from absent to present, wherein the timer counts time before being cleared;

after the execution of each write command is finished, when the read command exists in the command queue and the value of the timer exceeds a preset value, scheduling all the read commands in the command queue to be preferentially executed.
The apparatus of claim 7, wherein the computer program, when read and executed by the processor, causes the processor to further perform operations comprising:

after the execution of each write command is finished, when the read command does not exist in the command queue, or when the read command exists in the command queue but the value of the timer does not exceed the preset value, executing the commands in the command queue by using a first-in first-out (FIFO) strategy.
An apparatus as claimed in claim 7 or 8, wherein the computer program, when read and executed by the processor, causes the processor to perform the further operations of:

and after all the read commands in the command queue are scheduled to be executed preferentially, executing other commands to be processed in the command queue according to a first-in first-out (FIFO) strategy.
A universal flash storage UFS chip, comprising: UFS controller and Nand Flash particles; wherein the UFS controller comprises a processor and a memory;

the memory having stored thereon a computer program executable by the processor;

the computer program, when read and executed by the processor, causes the processor to perform the method of any of claims 1 to 6.
An electronic device, comprising: the UFS chip of claim 10.
A computer-readable storage medium, in which a computer program is stored, the computer program comprising at least one piece of code which is executable by a processor for implementing the method according to any one of claims 1 to 6.