CN112835323B - Programmable logic control language compiling method and device - Google Patents
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Abstract
The invention discloses a method and a device for compiling a programmable logic control language. Wherein, the method comprises the following steps: generating a corresponding first debugging information table according to a text language of a Programmable Logic Control (PLC) language, wherein the debugging information table comprises variables of the text language and a first syntax tree; generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language; and generating a coding instruction according to the first debugging information table and the second debugging information table. The invention solves the technical problems that the ST text language of the programmable logic control language in the related technology can not be directly identified and executed by the controller and the logic is poor.
Description
Technical Field
The invention relates to the field of industrial control, in particular to a method and a device for compiling a programmable logic control language.
Background
With the diversification of the requirements of industrial application, the traditional Programmable Logic Controller (PLC) is weak in the fields of calculation and motion control, and the emergence of ST structured text high-level language well meets the requirements. The structured text language ST (structured text) is a high-level language similar to passacal, and is easy to learn, flexible to use, quick and efficient for developers familiar with the high-level language of computers. However, the ST language in the related art cannot be recognized by the controller, needs to be converted into an IL instruction set, is similar to an assembly language for the controller, and has poor logic.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a method and a device for compiling a programmable logic control language, which are used for at least solving the technical problems that an ST text language of the programmable logic control language in the related art cannot be directly identified and executed by a controller and the logic performance is poor.
According to an aspect of an embodiment of the present invention, there is provided a programmable logic control language compiling method, including: generating a corresponding first debugging information table according to a text language of a Programmable Logic Control (PLC) language, wherein the debugging information table comprises variables of the text language and a first syntax tree; generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language; and generating a coding instruction according to the first debugging information table and the second debugging information table.
Optionally, the generating a corresponding first debugging information table according to the text language of the PLC language includes: generating a global variable table and a program variable table according to the text language; generating symbol tables of all variables of the text language according to the global variable table and the program variable table; performing lexical and syntactic analysis on the text language to generate a first syntax tree of the text language; and generating the first debugging information table according to the symbol table and the first syntax tree.
Optionally, performing lexical syntax analysis on the text language, and generating the first syntax tree of the text language includes: performing lexical analysis on an operational expression and a regular expression of the text language to determine a minimum keyword unit of the text language, wherein the operational expression comprises arithmetic operation, function calling and assignment operation, and the regular expression comprises variable analysis, special keywords and special symbols; parsing the text language to determine a first execution logic of the text language, wherein the text language comprises a plurality of logic statements; generating the first syntax tree according to the minimum key unit and the first execution logic.
Optionally, debugging information is inserted in the process of generating the first syntax tree according to the minimum keyword unit and the first execution logic; after generating the coding instruction according to the first debugging information table and the second debugging information table, the method further includes: compiling by the encoding instruction; and debugging the compiled coding instruction according to the debugging information.
Optionally, the generating a corresponding second debugging information table according to the graphic language of the PLC language includes: generating the second syntax tree according to the second execution logic and the graphic definition of the graphic language; and generating the second debugging information table according to the second syntax tree.
Optionally, generating a coding instruction according to the first debug information table and the second debug information table includes: mapping the variables of the text language and the soft elements corresponding to the variables in the graphic language according to the first debugging information table and the second debugging information table; converting the first debugging information table and the second debugging information table into a coding instruction list; and generating a coding instruction according to the compiling requirement and the coding instruction list.
Optionally, after generating the coding instruction according to the first debug information table and the second debug information table, the method includes: generating the encoding instruction into a binary file; and sending the binary file to a controller for executing the coding instruction.
According to another aspect of the embodiments of the present invention, there is also provided a programmable logic control language compiling apparatus, including: the device comprises a first generation module, a second generation module and a debugging module, wherein the first generation module is used for generating a corresponding first debugging information table according to a text language of a Programmable Logic Control (PLC) language, and the debugging information table comprises variables of the text language and a first syntax tree; the second generation module is used for generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language; and the third generation module is used for generating a coding instruction according to the first debugging information table and the second debugging information table.
According to another aspect of the embodiments of the present invention, there is also provided a computer storage medium, where the computer storage medium includes a stored program, and when the program runs, the apparatus where the computer storage medium is located is controlled to execute any one of the above methods for compiling a programmable logic control language.
According to another aspect of the embodiments of the present invention, there is also provided a processor, configured to execute a program, where the program executes the method for compiling a programmable logic control language according to any one of the above.
In the embodiment of the invention, a corresponding first debugging information table is generated by adopting a text language according to a Programmable Logic Control (PLC) language, wherein the debugging information table comprises variables of the text language and a first syntax tree; generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language; according to the mode of generating the coding instruction according to the first debugging information table and the second debugging information table, the first debugging information table is generated through a text language, the second debugging information table is generated through a graphic language, the first debugging information table and the second debugging information table generate the coding instruction for being controlled by the controller, the text language and the graphic language are cross-compiled, the purpose of ensuring the logic property of compiling is achieved, the coding instruction for being controlled by the controller of the text language is generated, the technical effect of the logic property of PLC language compiling is improved, and the technical problems that the ST text language of the programmable logic control language in the related technology cannot be directly identified and executed by the controller, and the logic property is poor are solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a flow chart of a method for compiling a programmable logic control language according to an embodiment of the invention;
FIG. 2 is a flow diagram of ladder diagram language and ST text language cross-compilation according to an embodiment of the present invention;
FIG. 3 is a flow diagram of ST text language precompilation according to an embodiment of the present invention;
FIG. 4 is a flow diagram of ladder diagram language compilation according to an embodiment of the present invention;
FIG. 5 is a diagram of ST text language lexical parsing according to an embodiment of the invention;
fig. 6 is a schematic diagram of a plc apparatus according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In accordance with an embodiment of the present invention, there is provided a method embodiment of a programmable logic control language compilation method, it being noted that the steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order different than presented herein.
Fig. 1 is a flowchart of a method for compiling a programmable logic control language according to an embodiment of the present invention, and as shown in fig. 1, the method includes the following steps:
step S102, generating a corresponding first debugging information table according to a text language of a Programmable Logic Control (PLC) language, wherein the debugging information table comprises variables of the text language and a first syntax tree;
step S104, generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language;
and step S106, generating a coding instruction according to the first debugging information table and the second debugging information table.
Through the steps, a corresponding first debugging information table is generated by adopting a text language according to a Programmable Logic Control (PLC) language, wherein the debugging information table comprises variables of the text language and a first syntax tree; generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language; according to the mode of generating the coding instruction according to the first debugging information table and the second debugging information table, the first debugging information table is generated through a text language, the second debugging information table is generated through a graphic language, the first debugging information table and the second debugging information table generate the coding instruction for being controlled by the controller, the text language and the graphic language are cross-compiled, the purpose of ensuring the logic property of compiling is achieved, the coding instruction for being controlled by the controller of the text language is generated, the technical effect of the logic property of PLC language compiling is improved, and the technical problems that the ST text language of the programmable logic control language in the related technology cannot be directly identified and executed by the controller, and the logic property is poor are solved.
The text language may be an ST text language of a PLC standard programming language, and the graphic language may be a ladder diagram of the PLC standard programming language. The ladder diagram is a graphic language widely applied to the field of automation control, the graphic language is similar to an electrical component, and control is realized by editing a graphic.
The ST text language cannot be recognized by the controller and needs to be converted to an IL instruction set, similar to assembly language, for use by the controller. The regular expression of the ST text Language sentence is analyzed through lexical grammar analysis, a corresponding symbol table, a variable table and an IL (Intermediate Language) instruction set are generated, and a function calling interface is provided, so that the function calling interface is convenient for a third party to call. The third party may be a controller.
And generating a corresponding first debugging information table according to the text language of the programmable logic control PLC language, wherein the debugging information table comprises variables of the text language and a first syntax tree, so that a coding instruction is generated according to the first debugging information table, the coding instruction can be the IL instruction set, and the ST text language is converted into the IL instruction for the controller to identify and execute. Thereby solving the problem that the ST text language cannot be recognized and executed by the controller.
And generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language, so that the coding instruction is generated according to the second debugging information. In the case of compiling the coded instruction according to the first debugging information of the text language, cross-compiling may be performed on a graphic language of a PLC language mapped by a preset variable in the first debugging information, where the PLC language includes the text language and the graphic language. Therefore, the cross compiling of the text language and the graphic language is realized, the compiling is more logical, and the problem that the compiling logic of a simple text language is weaker is solved.
Under the condition that the text language is compiled to the preset variable, before cross compiling the graphic language of the PLC language mapped by the preset variable, the method further comprises the following steps: and establishing a mapping relation between the preset variable and the graphic language through the address for the preset variable in the text language.
That is, the mapping relationship between the preset variable in the text language and the graphic language is predefined, and the mapping relationship and the graphic language are in one-to-one correspondence to form a shared memory region, so that the two languages can be accessed together.
Optionally, the generating a corresponding first debugging information table according to the text language of the PLC language includes: generating a global variable table and a program variable table according to the text language; generating symbol tables of all variables of the text language according to the global variable table and the program variable table; performing lexical and syntactic analysis on the text language to generate a first syntax tree of the text language; and generating a first debugging information table according to the symbol table and the first syntax tree.
Before generating a global variable table and a program variable table according to the text language, grammar check can be carried out on the text language; generating a global variable table and a program variable table under the condition that the text language passes the grammar check, wherein the variable table comprises the global variable of the text language and the program variable of the subprogram of the text language; generating symbol tables of all variables of the text language according to the global variable table and the program variable table, and performing syntactic analysis on the text language to generate a first syntactic tree; and generating a first debugging information table according to the symbol table and the first syntax tree.
The parsing of the text language includes at least one of: analyzing keywords of the text language, analyzing variables of the variable table, analyzing sentences of the text language and analyzing functions of the text language.
In this embodiment, the ST text language compiling process may first perform syntax checking before compiling, generate an error report if a syntax error is found, and then quit compiling. After the syntax check is passed, the global variable table is compiled firstly to generate a corresponding statement symbol table for all programs to use, then the compiling is carried out by sub-programs, and the local variable defined by each sub-program also corresponds to the generated symbol table and only allows the current program to access.
Optionally, performing lexical syntax analysis on the text language, and generating the first syntax tree of the text language includes: performing lexical analysis on an operational expression and a regular expression of a text language to determine a minimum keyword unit of the text language, wherein the operational expression comprises arithmetic operation, function calling and assignment operation, and the regular expression comprises variable analysis, special keywords and special symbols; performing syntactic analysis on a text language, and determining a first execution logic of the text language, wherein the text language comprises a plurality of logic statements; a first syntax tree is generated based on the minimum key unit and the first execution logic.
The method comprises the steps of analyzing phrase grammar of ST texts, analyzing variables, analyzing sentences including keyword analysis, variable analysis and IF. ELSE sentences, REPEAT sentences, WHILE sentences, FOR sentences and the like, analyzing user function tables, splitting each sentence into minimum keyword units, generating a binary grammar tree, namely a first grammar tree, comprising jump tags of ST programs and user function symbol tables, and inserting instruction debugging information in the process of phrase grammar analysis, wherein the phrase analysis is a mode of grammar analysis, so that breakpoint debugging can be conveniently carried out when a controller runs, and an IL instruction list, namely the list of coding instructions, is generated in the process of traversing the binary tree according to a certain sequence.
Optionally, during the process of generating the first syntax tree according to the minimum keyword unit and the first execution logic, debugging information is inserted; after generating the coding instruction according to the first debugging information table and the second debugging information table, the method further comprises the following steps: compiling through the coding instruction; and debugging the compiled coding instructions according to the debugging information.
The debugging information can be a breakpoint position, the debugging can be breakpoint debugging, each ST subprogram has a unique number and a unique variable table through the insertion debugging information, and text line number information of the subprogram is generated at the same time, so that a breakpoint debugging function can be realized while the program runs.
It should be noted that, during the process of generating the first syntax tree according to the minimum key unit and the first execution logic, debugging information is inserted, and the debugging information is written into the syntax tree or the global variable table along with the ST text language, so as to be written into the first debugging information table.
Inserting debugging information in the process of grammatical analysis of the text language; and debugging the text language according to the debugging information.
The debugging information can be breakpoint debugging information, the debugging information can be inserted into the text language in the compiling process, each subprogram of the text language has a unique number and a unique variable table, and the breakpoint debugging function can be realized while the program of the text language runs.
Carrying out syntactic analysis on the text language to generate a variable table of the text language; and generating a hash code corresponding to the variable according to the variable in the variable table, wherein the hash code is used for retrieving the variable.
The text language can generate a variable table after syntactic analysis, and local variables or global variables in each subprogram generate unique address code symbols, so that a user can monitor or force the variables to realize function debugging when debugging the program. The address code symbol may be a hash code.
Optionally, the generating a corresponding second debugging information table according to the graphic language of the PLC language includes: generating a second syntax tree according to a second execution logic of the graphic language and the graphic definition; and generating a second debugging information table according to the second syntax tree.
Analyzing the graphic language, and generating a second syntax tree according to a second execution logic and graphic definition of the graphic language; and traversing the second syntax tree to generate a second debugging information table of the graphic language.
The graphic language cannot be directly identified and executed by the controller, and therefore, the graphic language is converted into coded instructions for the controller to identify and execute. According to the second debugging information, an IL instruction set can be generated, namely the encoding instruction, and the graphic language is converted into the IL instruction for the controller to recognize and execute.
The graphic language can be checked before compiling, when the graphic language is the ladder diagram language, firstly, the double-coil output of the ladder diagram language or the ladder diagram disconnection and the like are checked to ensure the correctness of the ladder diagram language, then, according to the execution logic of the graphic language, soft elements such as parallel contacts, series contacts, normally open contacts, normally closed contacts, output coils, timers and the like are analyzed to generate a second syntax tree, and in the process of traversing the second syntax tree, a corresponding IL instruction list, namely the coding instruction list, is generated and can be directly provided for a controller to execute.
Parsing the graphical language, generating a second syntax tree comprising: checking the correctness of the graphic language; determining a soft element of the graphical language in case the graphical language is correct, wherein the soft element comprises at least one of: the system comprises a graph execution logic, a parallel contact, a series contact, a normally open contact, a normally closed contact, an output coil and a timer; and analyzing the soft element of the graphic language to generate a second syntax tree corresponding to the graphic language.
Generating a symbol table of the subprogram according to the local variables in the variable table; generating a control file according to the first coding instruction list, the symbol table and the second coding instruction list; and sending the control file to a controller for PLC control.
The control file can be an HEX binary file, the HEX file is sent to the controller, the controller analyzes the HEX file and loads an IL instruction code into FLASH, when a program is executed, the HEX code is analyzed instruction by instruction, and variables read from the instruction are loaded into a memory RAM, so that the program is executed. Optionally, the method further includes: generating a control instruction set according to the coding instruction corresponding to the text language and the coding instruction corresponding to the graphic language; addressing is carried out according to the length of the control instruction in the control instruction set, and PLC control is carried out through the control instruction.
Specifically, after syntactic analysis is performed on the text language, a generated coding instruction set is independent of an instruction set of the graphic language, independent binary coding is arranged between the instruction set of the text language and the instruction set of the graphic language, the number of bytes occupied by each coding instruction is kept unchanged, addressing is performed according to the length of the coding instruction in the program running process, and the control program can be realized.
Optionally, generating the encoding instruction according to the first debugging information table and the second debugging information table includes: mapping variables of a text language and soft elements corresponding to the variables in a graphic language by using the first debugging information table and the second debugging information table; converting the first debugging information table and the second debugging information table into a coding instruction list; and generating the coding instruction according to the compiling requirement and the coding instruction list.
When the text language is compiled, the text language is compiled into a list of coding instructions corresponding to the first debugging information, which can be a first coding instruction list, and when the graphic language is compiled, the graphic language is compiled into a list of coding instructions corresponding to the second debugging information, which can be called a second coding instruction list. And generating a coding instruction according to the compiling requirement and the coding instruction list to generate the coding instruction, thereby realizing the cross compiling of the text language and the graphic language.
Or when the variables compiled into the text language correspond to the soft elements corresponding to the variables in the graphic language, compiling the corresponding contents in the second debugging information table of the soft elements of the graphic language corresponding to the variables, converting the compiling into the graphic language at the moment, and converting the contents corresponding to the soft elements of the graphic language into coding instructions, thereby realizing the cross compiling of the text language and the graphic language.
Optionally, after generating the encoding instruction according to the first debug information table and the second debug information table, the method includes: generating a binary file by the encoding instruction; and sending the binary file to a controller for executing the coding instruction.
Combining an IL instruction list generated by a text language, namely a coding instruction, and a symbol list of each program with an IL instruction list coding instruction generated by a ladder diagram, generating an HEX binary file, and finally completing compiling; and when the program is executed, analyzing the HEX code instruction by instruction, and loading the variable read from the instruction into the RAM, thereby completing the execution of the program.
It should be noted that the present application also provides an alternative implementation, and the details of the implementation are described below.
The embodiment relates to a specific method for generating an instruction set which can be executed by a controller by cross compiling a PLC standard programming language, a ladder diagram and an ST text language and generating a corresponding debugging information document.
The ladder diagram is a graphic language widely applied to the field of automation control, the graphic language is similar to an electrical component, and control is realized by editing a graphic. The ladder diagram can not be directly identified by the controller, and needs to be converted into an IL instruction and then provided to the controller for analysis and execution.
The embodiment provides a method for converting a graphical language ladder diagram into an IL instruction, which mainly aims to convert a graphical language into an IL instruction similar to assembly language, provide the IL instruction for a controller to analyze, debug and operate, and convert the converted instruction.
In order to solve the problem of high-level language compiling, the embodiment of the invention provides a lexical grammar analysis function, which is used for analyzing the ST text language sentence regular expression, generating a corresponding symbol table, a variable table and an IL instruction set, and providing a function call interface, so that the function call interface is convenient for a third party to call.
In order to solve the problem of mixed calling of the ladder diagram and the ST language, in the process of compiling the ST language, defined variables can be in one-to-one correspondence with soft elements in the ladder diagram through address mapping to form a shared memory area, and the two languages can be ensured to be accessed together.
After ST language syntax analysis, the generated IL instruction set is independent of the instruction set of the ladder diagram, independent binary codes are arranged between the instruction set and the instruction set, the number of bytes occupied by each IL instruction is kept unchanged, addressing is carried out according to the length of the instruction in the program running process, and the control program can be realized.
The ladder diagram and the ST text language are finally converted into an IL instruction list, the two languages can be nested and used with each other, the advantages of the two languages can be effectively complemented, the PLC not only comprises the strict logic control of the ladder diagram, but also has the characteristics of high-level language, convenient calculation and modular programming, and the industrial automation control can be more effectively completed.
Debugging information can be inserted into the ST text in the compiling process, each ST subprogram has a unique number and a unique variable table, and the breakpoint debugging function can be realized while the program runs.
The ST language can generate a variable table after syntactic analysis, and local variables or global variables in each subprogram generate unique address code symbols, so that a user can monitor or force the variables to realize function debugging when debugging the program.
Fig. 2 is a flowchart of cross-compiling a ladder diagram language and an ST text language according to an embodiment of the present invention, where as shown in fig. 2, both the ST text language and the ladder diagram language conform to IEC61131-3 standard and are the most common languages for industrial control, both of them can generate an IL instruction list after compiling and can be mutually invoked during use, and both of them can be mixed and compiled to generate an IL instruction, that is, an encoding instruction list;
fig. 4 is a flowchart of ladder diagram language compiling according to an embodiment of the present invention, and as shown in fig. 4, the ladder diagram graphical language compiling is performed, before the ladder diagram compiling, whether a ladder diagram is output in a dual coil mode or a ladder diagram is broken, etc. is checked, so as to ensure the correctness of a program, and then a second syntax tree is generated by parsing according to a graphic execution logic, a parallel contact, a series contact, a normally open contact, a normally closed contact, an output coil, a timer, etc. in a process of traversing the second syntax tree, a corresponding IL instruction list, that is, a second encoding instruction list is generated, which can be directly provided for a controller to execute;
FIG. 3 is a flow chart of ST text language precompilation according to an embodiment of the present invention, as shown in FIG. 3, when ST text language is compiled, firstly syntax check is performed before compiling, and if syntax error is found, an error report is generated first, and then compiling is exited;
after the grammar check is passed, firstly compiling the global variable table to generate a corresponding statement symbol table for all programs to use, then compiling the statement symbol table by sub-programs, wherein the local variable defined by each sub-program also corresponds to the generated symbol table and only allows the current program to access;
fig. 5 is a schematic diagram of ST text language lexical grammar analysis according to an embodiment of the present invention, as shown in fig. 5, the ST text language performs syntax analysis including keyword analysis and variable analysis, and includes IF.. statement analysis such as an ELSE statement, a REPEAT statement, a WHILE statement, a FOR statement, and the like, user function table analysis, splits each statement into minimum keyword units, and generates a binary syntax tree, i.e., a first syntax tree, which includes a jump tag of an ST program and a user function symbol table, and inserts instruction debugging information during the lexical analysis, so that a controller can perform breakpoint debugging when operating conveniently, and an IL instruction list is generated in a certain order during traversal of the binary syntax tree;
combining the generated IL instruction list, namely a first coding instruction list, and the symbol list of each program with the IL instruction list generated by the ladder diagram, namely a second coding instruction list, and generating an HEX binary file, namely a control file, and finally completing compiling;
and when the program is executed, analyzing the HEX code instruction by instruction, and loading the variable read from the instruction into the RAM, thereby completing the execution of the program.
Fig. 6 is a schematic diagram of a plc apparatus according to an embodiment of the present invention, and as shown in fig. 6, according to another aspect of the embodiment of the present invention, there is further provided a plc apparatus including: a first generation module 62, a second generation module 64 and a third generation module 66, which will be described in detail below.
The first generating module 62 is configured to generate a corresponding first debugging information table according to the text language of the PLC language, where the debugging information table includes variables of the text language and a first syntax tree; the second generating module 64 is connected with the first generating module 62 and is used for generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language; and a third generating module 66, connected to the second generating module 64, for generating a coding instruction according to the first debugging information table and the second debugging information table.
By the device, a corresponding first debugging information table is generated by adopting a text language according to a Programmable Logic Control (PLC) language, wherein the debugging information table comprises variables of the text language and a first syntax tree; generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language; according to the mode of generating the coding instruction according to the first debugging information table and the second debugging information table, the first debugging information table is generated through a text language, the second debugging information table is generated through a graphic language, the first debugging information table and the second debugging information table generate the coding instruction for being controlled by the controller, the text language and the graphic language are cross-compiled, the purpose of ensuring the logic property of compiling is achieved, the coding instruction for being controlled by the controller of the text language is generated, the technical effect of the logic property of PLC language compiling is improved, and the technical problems that the ST text language of the programmable logic control language in the related technology cannot be directly identified and executed by the controller, and the logic property is poor are solved.
According to another aspect of the embodiments of the present invention, there is also provided a computer storage medium, where the computer storage medium includes a stored program, and the program, when executed, controls an apparatus in which the computer storage medium is located to execute any one of the above methods for compiling a programmable logic control language.
According to another aspect of the embodiments of the present invention, there is also provided a processor, configured to execute a program, where the program executes the method for compiling a programmable logic control language according to any one of the above.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and amendments can be made without departing from the principle of the present invention, and these modifications and amendments should also be considered as the protection scope of the present invention.
Claims (9)
1. A method for compiling a programmable logic control language, comprising:
generating a corresponding first debugging information table according to a text language of a Programmable Logic Control (PLC) language, wherein the first debugging information table comprises variables of the text language and a first syntax tree;
generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language;
generating a coding instruction according to the first debugging information table and the second debugging information table;
generating a coding instruction according to the first debug information table and the second debug information table comprises:
mapping variables of the text language and soft elements corresponding to the variables in the graphic language;
converting the first debugging information table and the second debugging information table into a coding instruction list according to the mapping relation between the variables of the text language and the soft elements of the graphic language;
and generating the coding instruction according to the compiling requirement and the coding instruction list.
2. The method of claim 1, wherein generating the corresponding first debug information table according to the text language of the PLC language comprises:
generating a global variable table and a program variable table according to the text language;
generating symbol tables of all variables of the text language according to the global variable table and the program variable table;
performing lexical and syntactic analysis on the text language to generate a first syntax tree of the text language;
and generating the first debugging information table according to the symbol table and the first syntax tree.
3. The method of claim 2, wherein lexically parsing the text language and generating the first syntax tree for the text language comprises:
performing lexical analysis on an operational expression and a regular expression of the text language to determine a minimum keyword unit of the text language, wherein the operational expression comprises arithmetic operation, function calling and assignment operation, and the regular expression comprises variable analysis, special keywords and special symbols;
parsing the text language to determine a first execution logic of the text language, wherein the text language comprises a plurality of logic statements;
generating the first syntax tree according to the minimum key unit and the first execution logic.
4. The method of claim 3, wherein debugging information is inserted during the generation of the first syntax tree based on the minimum key unit and the first execution logic;
after generating the coding instruction according to the first debugging information table and the second debugging information table, the method further includes:
compiling by the encoding instruction;
and debugging the compiled coding instruction according to the debugging information.
5. The method of claim 1, wherein generating a corresponding second debugging information table according to a graphical language of the PLC language comprises:
generating the second syntax tree according to the second execution logic and the graphic definition of the graphic language;
and generating the second debugging information table according to the second syntax tree.
6. The method of claim 1, wherein after generating the coded instructions according to the first debug information table and the second debug information table, the method comprises:
generating the encoding instruction into a binary file;
and sending the binary file to a controller for executing the coding instruction.
7. A programmable logic control language compiling apparatus comprising:
the device comprises a first generation module, a second generation module and a third generation module, wherein the first generation module is used for generating a corresponding first debugging information table according to a text language of a Programmable Logic Control (PLC) language, and the first debugging information table comprises variables of the text language and a first syntax tree;
the second generation module is used for generating a corresponding second debugging information table according to the graphic language of the PLC language, wherein the second debugging information table comprises a second syntax tree of the graphic language;
the third generation module is used for generating a coding instruction according to the first debugging information table and the second debugging information table;
generating a coding instruction according to the first debugging information table and the second debugging information table comprises:
mapping variables of the text language and soft elements corresponding to the variables in the graphic language;
converting the first debugging information table and the second debugging information table into a coding instruction list according to the mapping relation between the variables of the text language and the soft elements of the graphic language;
and generating the coding instruction according to the compiling requirement and the coding instruction list.
8. A computer storage medium, comprising a stored program, wherein,
controlling a device on which the computer storage medium is located to execute the method for compiling a programmable logic control language according to any one of claims 1 to 6 when the program runs.
9. A processor, configured to run a program, wherein the program is configured to execute the plc compiling method according to any one of claims 1 to 6 when the program is run.
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| CN118069219A (en) * | 2022-11-23 | 2024-05-24 | 深圳市汇川技术股份有限公司 | Hybrid execution method, device, equipment and medium of programmable logic controller |
| CN116360788A (en) * | 2023-02-17 | 2023-06-30 | 深圳市亿维自动化技术有限公司 | Compiling method, compiler and electronic device for structured text programming language |
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