CN112821885A - Relative time delay measurement calibration method and device for chips of each channel of ATE (automatic test equipment) - Google Patents
Relative time delay measurement calibration method and device for chips of each channel of ATE (automatic test equipment) Download PDFInfo
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Abstract
The invention provides a relative delay measurement calibration method for chips of each channel of ATE equipment, which relates to the technical field of delay measurement and control, and comprises the steps that a Driver0 port outputs an electric pulse signal to detection chips, namely, a Driver0, a Driver 1, a Driver …, a Driver N-1 and a Driver N; isometric processing is carried out on the electric pulse signals of each channel; calculating a delay parameter; and inputting the calculated delay parameters into the FPGA to perform delay correction compensation. The invention has the beneficial effects that: the delay measuring device has simple structure, the measuring method can realize automatic measurement of relative delay, the delay is automatically compensated by using the delay control unit in the FPGA device after the relative delay is measured, the number of channels can be freely selected, and the configuration is simple.
Description
Technical Field
The invention belongs to the technical field of delay measurement and control, and particularly relates to a method and a device for calibrating relative delay measurement of chips of each channel of ATE (automatic test equipment).
Background
In ATE digital devices, a multi-channel arbitrary digital waveform generator is a functional block of a core. In the process of generating, transmitting and level-converting multi-channel digital waveforms and finally reaching the tested chip, due to the influences of factors such as devices and different paths, the digital signals finally reaching the tested chip have ns-level delay.
Similarly, in the process that the feedback signal of the tested chip is collected, transmitted and finally reaches the CPU for analysis, the collected signal has ns-level delay.
For high-level chip testing, a tested chip is very sensitive to multi-channel digital signal delay, and the required precision is high. Therefore, effective compensation of signal delay of each channel plays a crucial role in success or failure of chip testing.
Disclosure of Invention
The invention provides a relative delay measurement calibration method and device for chips of each channel of ATE (automatic test equipment), which solve the problems that ns-level delay of digital signals in the transmission process during chip test in the prior art influences the success or failure of the chip test and the like.
In a first aspect of the present invention, a method for calibrating relative delay measurement of chips of each channel of an ATE device is provided, including:
(1) the Driver0 port outputs electric pulse signals to the Receiver0, the Receiver1, …, the Receiver N-1 and the Receiver N;
(2) carrying out isometric processing on paths of all channels through which the electric pulse signals pass;
(3) calculating a delay parameter;
(4) and (4) inputting the delay parameters calculated in the step (3) into the FPGA to perform delay correction compensation.
The method for processing the output electric pulse signals with equal length comprises the steps that an ATE device is externally connected with an equal-length board card, and each channel signal is processed with equal length through the board card, so that the signals of a Driver0 are transmitted to a Receiver0, a Receiver1, a Receiver …, a Receiver N-1 and a Receiver N with equal length.
The delay parameter calculated in the step (3) of the invention comprises:
(3.1) measuring delay values T0, T1, …, TN-1 and TN of Receiver0, Receiver1, …, Receiver n-1 and Receiver n at Receiver0, Receiver1, …, Receiver n-1 and Receiver n ports, respectively;
(3.2) calculating delay differences delta T1, delta T2, …, delta TN-1 and delta TN of the channels Receiver1, Receiver2, …, Receiver N-1 and Receiver N relative to the channel Receiver 0.
The method for calculating the delay values T0, T1, …, TN-1 and TN of the Receiver0, the Receiver1, …, the Receiver N-1 and the Receiver N is a TMU algorithm,
the method for calculating the delay difference values delta T1, delta T2, …, delta TN-1 and delta TN specifically comprises the steps of delta T1-T1-T0, delta T2-T2-T0, … and delta TN-T0.
The FPGA is internally provided with a delay correction unit for correcting and compensating delay.
In a second aspect of the present invention, there is provided an ATE device for calibrating relative delay measurement of chips in each channel, comprising:
the equal-length board card is externally connected with ATE equipment and used for ensuring that each channel signal is subjected to equal-length processing in time through the equal-length board card, and signals output by the Driver0 are simultaneously sent to the Receiver0, the receivers 1, …, the Receiver N-1 and the Receiver N;
the TMU delay parameter measurement module is arranged in an FPGA chip of the ATE equipment and is used for measuring delay values of each channel Receiver0, Receiver1, …, Receiver N-1 and Receiver N and delay difference values delta T1, delta T2, …, delta TN-1 and delta TN of each channel Receiver1, Receiver2, …, Receiver N-1 and Receiver N relative to a channel Receiver 0;
and the Delay correction unit is arranged in an FPGA chip of the ATE equipment, mainly comprises a Delay compensation circuit and is used for correcting and compensating the Delay calculated by the TMU Delay parameter measurement module.
The Delay compensation circuit comprises a Delay compensation circuit 1, Delay compensation circuits 1 and …, a Delay compensation circuit N-1 and a Delay compensation circuit N, which are respectively compensated with a Receiver0, receivers 1 and …, a Receiver N-1 and a Receiver N.
In a third aspect of the invention, an electronic device is provided. The electronic device includes: a memory having a computer program stored thereon and a processor implementing the method according to the first aspect of the invention when executing the program.
In a fourth aspect of the invention, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the method according to the first aspect of the invention.
It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of any embodiment of the invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.
The invention has the beneficial effects that: compared with other measurement schemes, the relative delay measurement calibration method and device for each channel chip of ATE equipment are simple in structure, the measurement method can achieve automatic measurement of relative delay, automatic compensation of delay is achieved by using a delay control unit inside an FPGA device after the relative delay is measured, the number of channels can be freely selected, and configuration is simple.
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FIG. 1 is a schematic diagram of a method and apparatus for calibrating relative delay measurement of chips of channels of an ATE device according to the present invention;
FIG. 2 is a schematic flow chart of a calibration method for measuring relative delays of chips of channels of an ATE device according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Fig. 1 is a schematic diagram illustrating a method and apparatus for calibrating relative delay measurement of chips of channels of an ATE device. Taking a method for calculating relative delay of a detection chip acquisition channel as an example, in particular to a method for measuring and calibrating relative delay of each channel chip of ATE equipment, which comprises the following steps:
(1) the Driver0 port outputs electrical pulse signals to the output ports Receiver0, Receiver1, …, Receiver N-1 and Receiver N;
(2) an isometric board card is externally connected to ATE equipment, signals of each channel are subjected to board card time isometric processing, and signals output by a Driver0 are sent to a Receiver0, a Receiver1, a Receiver …, a Receiver N-1 and a Receiver N, so that the signals are ensured to be routed in the isometric board card: length0 Length1 Length … … Length n-1 Length n;
(3) calculating a delay parameter: respectively measuring delay values T0, T1, …, TN-1 and TN of the Receiver0, the Receiver1, …, the Receiver N-1 and the Receiver N by simultaneously applying a TMU measurement algorithm on the Receiver0, the Receiver1, …, the Receiver N-1 and the Receiver N ports; calculating delay differences delta T1, delta T2, …, delta TN-1 and delta TN of the channels Receiver1, Receiver2, …, Receiver N-1 and Receiver N relative to the channel Receiver0, specifically, delta T1-T1-T0, delta T2-T2-T0, … and delta TN-T0;
(4) and (4) inputting the delay parameters calculated in the step (3) into a delay correction unit of the FPGA to perform delay correction compensation.
The relative delay measurement calibration method of the output channel of the detection chip is similar to the relative delay measurement calibration method of the acquisition channel.
The TMU (time Measurement unit) is a time Measurement unit, is a prior art, and is a semiconductor Automatic Test Equipment (ATE) responsible for measuring the interval time between two events or calculating the number of events, and in this patent, a person skilled in the art can perform delay detection according to the existing TMU algorithm.
A relative delay measurement calibration device for chips of each channel of ATE equipment comprises:
the equal-length board card is externally connected with ATE equipment and used for ensuring that each channel signal is subjected to equal-length processing in time through the equal-length board card, and signals output by the Driver0 are simultaneously sent to the Receiver0, the receivers 1, …, the Receiver N-1 and the Receiver N;
the TMU delay parameter measurement module is arranged in an FPGA chip of the ATE equipment and is used for measuring delay values of each channel Receiver0, Receiver1, …, Receiver N-1 and Receiver N and delay difference values delta T1, delta T2, …, delta TN-1 and delta TN of each channel Receiver1, Receiver2, …, Receiver N-1 and Receiver N relative to a channel Receiver 0;
the Delay correction unit is arranged in an FPGA chip of ATE equipment, mainly comprises a Delay compensation circuit and is used for correcting and compensating the Delay calculated by the TMU Delay parameter measurement module, wherein the Delay compensation circuit comprises a Delay compensation circuit 1, Delay compensation circuits 1 and …, a Delay compensation circuit N-1 and a Delay compensation circuit N which are respectively compensated corresponding to a Receiver0, a Receiver1, a Receiver …, a Receiver N-1 and a Receiver N.
An electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to realize the relative delay measurement calibration method of each channel chip of the ATE device.
A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method for calibrating relative delay measurements of chips of channels of an ATE device as described above.
Program code for implementing the methods of the present invention may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Further, while operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the invention. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (10)
1. A relative time delay measurement calibration method for chips of each channel of ATE equipment is characterized by comprising the following steps:
(1) the Driver0 port outputs electric pulse signals to the Receiver0, the Receiver1, …, the Receiver N-1 and the Receiver N;
(2) carrying out isometric processing on paths of all channels through which the electric pulse signals pass;
(3) calculating a delay parameter;
(4) and (4) inputting the delay parameters calculated in the step (3) into the FPGA to perform delay correction compensation.
2. The method as claimed in claim 1, wherein the method for processing the paths of the electrical pulse signals through the channels in equal length is to connect an equal length board card to the ATE device, and the signals of the channels are processed in equal length in time by the board card, so that the signals of Driver0 are transmitted to the Driver0, the drivers 1, …, the drivers n-1, and the drivers n are equal in length.
3. The method of claim 1, wherein the delay parameters calculated in step (3) comprise:
(3.1) measuring delay values T0, T1, …, TN-1 and TN of Receiver0, Receiver1, …, Receiver n-1 and Receiver n at Receiver0, Receiver1, …, Receiver n-1 and Receiver n ports, respectively;
(3.2) calculating delay differences delta T1, delta T2, …, delta TN-1 and delta TN of the channels Receiver1, Receiver2, …, Receiver N-1 and Receiver N relative to the channel Receiver 0.
4. The method of claim 1, wherein the method for calculating the delay values T0, T1, …, TN-1 and TN of Receiver0, Receiver1, …, Receiver n-1 and Receiver n is TMU algorithm.
5. The method for calibrating relative delay measurement of chips of ATE equipment according to claim 3, characterized in that the delay difference Δ T1, Δ T2, …, Δ TN-1, Δ TN is calculated by a method specifically including Δ T1-T1-T0, Δ T2-T2-T0, …, Δ TN-T0.
6. The method of claim 1, wherein a delay correction unit is provided within the FPGA to correct and compensate for delay.
7. A relative delay measurement calibration device for chips of each channel of ATE equipment is characterized by comprising:
the equal-length board card is externally connected with ATE equipment and used for ensuring that each channel signal is subjected to equal-length processing in time through the equal-length board card, and signals output by the Driver0 are simultaneously sent to the Receiver0, the receivers 1, …, the Receiver N-1 and the Receiver N;
the TMU delay parameter measurement module is arranged in an FPGA chip of the ATE equipment and is used for measuring delay values of each channel Receiver0, Receiver1, …, Receiver N-1 and Receiver N and delay difference values delta T1, delta T2, …, delta TN-1 and delta TN of each channel Receiver1, Receiver2, …, Receiver N-1 and Receiver N relative to a channel Receiver 0;
and the Delay correction unit is arranged in an FPGA chip of the ATE equipment, mainly comprises a Delay compensation circuit and is used for correcting and compensating the Delay calculated by the TMU Delay parameter measurement module.
8. The calibration apparatus as claimed in claim 8, wherein the Delay compensation circuit comprises a Delay compensation circuit 1, a Delay compensation circuit …, a Delay compensation circuit N-1, and a Delay compensation circuit N, which are compensated corresponding to a Receiver0, a Receiver1, a Receiver …, a Receiver N-1, and a Receiver N, respectively.
9. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program, wherein the processor, when executing the program, implements the method of any of claims 1-6.
10. A computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, carries out the method of any one of claims 1 to 6.
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Cited By (5)
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| CN113539350A (en) * | 2021-06-17 | 2021-10-22 | 杭州加速科技有限公司 | ATE equipment self-checking based method and system |
| CN115291090A (en) * | 2022-10-09 | 2022-11-04 | 苏州华兴源创科技股份有限公司 | Chip tester signal delay measuring method and device and computer equipment |
| CN115327330A (en) * | 2022-07-27 | 2022-11-11 | 上海精积微半导体技术有限公司 | Automatic calibration circuit, device and method for ATE channel time delay |
| CN115792769A (en) * | 2023-01-29 | 2023-03-14 | 苏州华兴源创科技股份有限公司 | Signal calibration method and system of semiconductor test equipment and computer equipment |
| CN116032406A (en) * | 2022-11-30 | 2023-04-28 | 三维通信股份有限公司 | Multi-channel time delay alignment method, device, communication equipment and storage medium |
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