CN112816773B - A current sampling circuit - Google Patents

Abstract

The invention relates to the technical field of current sampling, and discloses a current sampling circuit which comprises a current mirror circuit, a voltage clamping circuit and an output cascode current mirror circuit; the current mirror circuit comprises a sampling circuit and a mirror circuit, the sampling circuit comprises a plurality of first MOS (metal oxide semiconductor) tubes connected in parallel, the mirror circuit comprises a plurality of second MOS tubes connected in series, the drain electrode of the first second MOS tube inputs a first mirror current to the output mirror current mirror circuit, the output mirror current mirror circuit converts the proportion of the first mirror current into a second mirror current, and the second mirror current is input to the sampling resistor Rsense; the voltage clamping circuit clamps the drain voltage of the first MOS tube and the drain voltage of the first second MOS tube to the same potential, and when the voltage clamping circuit is in actual use, the sampling proportion of the current mirror circuit can be ensured due to the fact that the drain voltages of the first MOS tube and the first second MOS tube are the same, and the precision requirement of the sampling resistor Rsense can be reduced when the sampling proportion is required to be high.

Description

A current sampling circuit

Technical Field

The present invention relates to the technical field of current sampling, and in particular to a current sampling circuit.

Background Art

At present, sampling and detecting current is a necessary condition for many DC brush motors or stepper motors to work. For brush motors, sampling and detecting current information can determine the change of load conditions and can also be used to limit the starting current or stall current. When the motor is in the starting period, it is usually necessary to maintain a certain current condition before reaching the steady-state condition. If there is no current regulation function, it may not be able to meet this specific condition, resulting in failure to start normally. At the same time, when the motor drive generates overcurrent, the current sampling and current regulation can also be used to adjust the current of the chip or perform overcurrent protection. Therefore, a high-precision current sampling circuit and the corresponding current regulation function are very important for the motor driver chip. The traditional motor current adopting method is mostly to limit the current by connecting a parallel resistor to the ground outside the motor, generating a shunt to detect the voltage drop of the motor, and then comparing it with the reference voltage inside or outside the chip. Because this current sampling method is for sampling the full-load current, the external parallel resistor often uses a high-precision power resistor, which occupies a large area and generates a high cost while meeting the high precision. In addition, most of the existing current sampling circuits use a conventional current mirror architecture, so when detecting very small currents, the accuracy of the sampling resistor is very high, and it is difficult to achieve a high sampling ratio. In addition, the existing current sampling circuits are generally performed on the sampling tube through which the current passes. The accuracy of current sampling will be affected by the sampling ratio. The larger the sampling ratio, the worse the accuracy. Reducing the sampling ratio will not only increase the area of the circuit, but also bring too much additional power consumption to the circuit.

Summary of the invention

In view of the shortcomings of the background technology, the present invention provides a current sampling circuit with adjustable sampling ratio and high precision.

To solve the above technical problems, the present invention provides the following technical solutions: a current sampling circuit, comprising a current mirror circuit, a voltage clamping circuit and an output cascode current mirror circuit; the current mirror circuit comprises a sampling circuit and a mirror circuit, the sampling circuit comprises at least two first MOS tubes, the drains of all the first MOS tubes are respectively input with a detection current, the gates of all the first MOS tubes are respectively input with a first driving voltage VIN, and the sources of all the first MOS tubes are grounded; the mirror circuit comprises at least two second MOS tubes, all the second MOS tubes are sequentially connected in series, the series connection means that the source of the previous second MOS tube is electrically connected to the drain of the next second MOS tube, the drain of the first second MOS tube inputs the first mirror current to the output cascode current mirror circuit, the source of the last second MOS tube is grounded, and the gates of all the second MOS tubes are respectively input with the first driving voltage VIN; the output cascode current mirror circuit converts the first mirror current ratio into a second mirror current, and the second mirror current is input to the sampling resistor Rsense; the voltage clamping circuit clamps the drain voltage of the first MOS tube and the drain voltage of the first second MOS tube to a target potential.

In a certain implementation, the sampling circuit includes four first MOS transistors, and the mirror circuit includes three second MOS transistors.

In a certain embodiment, the voltage clamping circuit includes an error amplifier AMP and an output tube MN1, the positive electrode of the error amplifier AMP is electrically connected to the drain of the first MOS tube, the negative electrode of the error amplifier is electrically connected to the drain of the first second MOS tube, the output signal of the error amplifier is input to the gate of the output tube MN1, and the first mirror current is input to the output cascode current mirror circuit through the source and drain of the output tube MN1.

In a certain embodiment, the error amplifier includes a primary amplifier circuit, a secondary amplifier circuit, a tertiary amplifier circuit and a bias current generating circuit;

The bias current generating circuit generates a first bias current, a second bias current and a third bias current;

The first-stage amplifier circuit includes MOS tubes M1, M2, M3, M4 and M13, the first bias current is input to the source electrodes of the MOS tubes M1 and M2, the gate electrode of the MOS tube M1 is the negative electrode of the error amplifier AMP, the gate electrode of the MOS tube M2 is the positive electrode of the error amplifier AMP, the drain electrode of the MOS tube M1 is electrically connected to the drain electrode of the MOS tube M3, the drain electrode of the MOS tube M2 is electrically connected to the drain electrode of the MOS tube M4, the sources of the MOS tubes M3, M4 and M13 are grounded respectively, and the gate electrode of the MOS tube M3, the gate electrode of the MOS tube M4, and the gate electrode and drain electrode of the MOS tube M13 are electrically connected to the power supply V1 respectively;

The secondary amplifier circuit includes MOS tubes M14, M15, M16, M17, M18 and M19. The sources of MOS tubes M14 and M15 are electrically connected to the power supply V2 respectively. The gate of MOS tube M14 is electrically connected to the drain of MOS tube M14, the gate of MOS tube M15 and the drain of MOS tube M16 respectively. The drain of MOS tube M15 is electrically connected to the drain of MOS tube M17. The gates of MOS tubes M16 and M17 input the second bias current respectively. The source of MOS tube M16 is electrically connected to the drain of MOS tube M2 and the source of MOS tube M18 respectively. MOS tube M17 The source of the MOS tube M1 is electrically connected to the drain of the MOS tube M1 and the source of the MOS tube M19 respectively, the gates of the MOS tubes M18 and M19 are respectively input with the enable voltage V3 and the enable voltage V4, and the drains of the MOS tubes M18 and M19 are respectively grounded; the three-stage amplification circuit includes MOS tubes M20 and M21, the source of the MOS tube M20 is electrically connected to the power supply V2, the gate of the MOS tube M20 is electrically connected to the drain of the MOS tube M15, the drain of the MOS tube M20 is respectively electrically connected to the gate of the output tube MN1, the third bias current is input to the gate of the MOS tube M21, and the source of the MOS tube M21 is grounded.

In a certain embodiment, the drains of the MOS tubes M18 and M19 are grounded through the trimming module, and the trimming module includes MOS tubes M60, M61, M62, M63, M64, M65, M66 and M67. The drains of the MOS tubes M60, M61, M62 and M63 are electrically connected to the drains of the MOS tubes M18 and M19, respectively. The gates of the MOS tubes M60, M61, M62 and M63 are respectively connected to the first control signal EN1, the second control signal EN2, the third control signal EN3 and the fourth control signal EN4. The sources of the MOS tubes M60, M61, M62 and M63 are respectively electrically connected to the drains of the MOS tubes M64, M65, M66 and M67, respectively. The gates of the MOS tubes M64, M65, M66 and M67 are respectively connected to the voltage Vbias, and the sources of the MOS tubes M64, M65, M66 and M67 are grounded.

In a certain embodiment, the output cascode current mirror circuit includes power tubes MP1, MP2, MP3 and MP4, the sources of the power tubes MP1 and MP2 are electrically connected to the power supply VDD respectively, the drain of the power tube MP1 is electrically connected to the drain of the power tube MP3, the drain of the power tube MP2 is electrically connected to the drain of the power tube MP4, the gate of the power tube MP1 is electrically connected to the gate of the power tube MP2, the source of the power tube MP3 and the drain of the output tube MN1 respectively, the gates of the power tubes MP3 and MP4 are electrically connected to the driving voltage V5 respectively, the source of the power tube MP4 is electrically connected to one end of the sampling resistor Rsense, and the other end of the sampling resistor Rsense is grounded.

In a certain implementation manner, the ungrounded end of the sampling resistor Rsense is electrically connected to a digital-to-analog conversion interface of the MCU, and the MCU performs analog-to-digital conversion on the voltage of the sampling resistor Rsense.

Compared with the prior art, the present invention has the following beneficial effects:

1: The sampling circuit is composed of at least two first MOS tubes connected in parallel. Under the premise of ensuring a high sampling ratio, it avoids the size of a single sampling tube being too large when a higher sampling ratio is required, and also has better layout matching;

2: The drain voltage of the first MOS tube and the drain voltage of the first and second MOS tubes are clamped to the same potential through the error amplifier. When the gate voltage of the first MOS tube and the gate voltage of the second MOS tube are the same, the first MOS tube and the second MOS tube can be linearly turned on, thereby ensuring the sampling accuracy of the current mirror circuit. In this way, there is no need to set an additional high-precision sampling resistor when a high sampling ratio is required;

3: In actual use, by adjusting the current conversion ratio of the output cascode current mirror circuit, the requirements for the sampling resistor at a high sampling ratio can be reduced; in addition, by adjusting the output impedance of the power tubes MP3 and MP4 of the output cascode current mirror circuit, the power supply rejection ratio can be improved, and the sampling accuracy of the output cascode current mirror circuit can be increased;

4: In actual use, the present invention can be applied to the motor driver chip to perform current sampling on the low side. When the motor is in an independent PWM mode and the two low-side MOSFETs are sensing current at the same time, the currents of the two low-side MOSFETs can be input into the output cascode current mirror circuit for detection. Only one current sampling circuit is needed to detect the currents of the two low-side MOSFETs, thereby reducing power consumption and reducing costs. At the same time, it also allows the motor winding current to be detected during the slow decay of the driving and braking low sides, thereby being able to detect the current in a bidirectional brushed DC motor.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention has the following accompanying drawings:

Fig. 1 is a circuit diagram of the present invention;

FIG2 is a circuit diagram of an error amplifier of the present invention;

FIG3 is a circuit diagram of a trimming module of the present invention;

FIG. 4 is a simulation diagram of the present invention.

DETAILED DESCRIPTION

The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

As shown in FIG1 , a current sampling circuit includes a current mirror circuit 1, a voltage clamp circuit 2 and an output cascode current mirror circuit 3; the current mirror circuit 1 includes a sampling circuit 10 and a mirror circuit 11, the sampling circuit 10 includes at least two first MOS tubes M101, the drains of all the first MOS tubes M101 are respectively input with a detection current, the gates of all the first MOS tubes M101 are respectively input with a first driving voltage VIN, and the sources of all the first MOS tubes M101 are grounded; the mirror circuit 11 includes at least two second MOS tubes M102, all the second MOS tubes M102 are connected in series in sequence, and the series connection refers to the connection of the previous second MOS tube M102 with the previous second MOS tube M102. The source of the first MOS tube M101 is electrically connected to the drain of the next second MOS tube M102, the drain of the first second MOS tube M102 inputs the first mirror current to the output cascode current mirror circuit 3, the source of the last second MOS tube M102 is grounded, and the gates of all the second MOS tubes M102 are respectively connected to the input first driving voltage VIN; the output cascode current mirror circuit 3 converts the first mirror current into a second mirror current in proportion, and the second mirror current is input to the sampling resistor Rsense; the voltage clamping circuit 2 clamps the drain voltage of the first MOS tube M101 and the drain voltage of the first second MOS tube M102 to the same potential.

Specifically, in this embodiment, the sampling circuit 10 includes four first MOS transistors M101, and the mirror circuit 11 includes three second MOS transistors M102. By connecting the four first MOS transistors M101 in parallel and the three second MOS transistors M102 in series, the current ratio is 1:K, so that the ideal current value mirrored by the mirror circuit is I _sense =I _in /K. In an ideal case, the drain current of the MOS transistor in the linear region should be: Therefore, if the current of the second MOS tube M102 and the first MOS tube M101 is to be proportional to the size, the drain voltage and gate voltage of the two tubes need to be the same, and the difference in the drain potential of the two tubes will lead to different drain currents, and will also lead to a serious channel length modulation effect, resulting in low accuracy of the sampled current. Therefore, it is necessary to use a voltage clamping circuit 2 to clamp the drain voltage of the first MOS tube M101 and the second MOS tube M102 to the target potential to ensure a high sampling ratio of the current mirror circuit 1.

Specifically, in the present embodiment, the output cascode current mirror circuit 3 includes power tubes MP1, MP2, MP3 and MP4, the sources of the power tubes MP1 and MP2 are electrically connected to the power supply VDD respectively, the drain of the power tube MP1 is electrically connected to the drain of the power tube MP3, the drain of the power tube MP2 is electrically connected to the drain of the power tube MP4, the gate of the power tube MP1 is electrically connected to the gate of the power tube MP2, the source of the power tube MP3 and the drain of the output tube MN1 respectively, the gates of the power tubes MP3 and MP4 are electrically connected to the driving voltage V5 respectively, the source of the power tube MP4 is electrically connected to one end of the sampling resistor Rsense, and the other end of the sampling resistor Rsense is grounded, wherein the power tubes MP1 and MP2 form a current mirror structure, and the ratio thereof is 1:1. In actual use, if the current value to be sampled is too small, the ratio of the current mirror structure can be appropriately adjusted to reduce the accuracy requirement on the sampling resistor Rsense.

Specifically, in this embodiment, the voltage clamping circuit 2 includes an error amplifier AMP and an output tube MN1, the positive electrode of the error amplifier AMP is electrically connected to the drain of the first MOS tube M101, the negative electrode of the error amplifier AMP is electrically connected to the drain of the first second MOS tube M102, the output signal of the error amplifier AMP is input to the gate of the output tube MN1, and the first mirror current is input to the output cascode current mirror circuit through the source and drain of the output tube MN1.

As shown in FIG. 2 , in this embodiment, the error amplifier AMP includes a primary amplifier circuit 21 , a secondary amplifier circuit 22 , a tertiary amplifier circuit 23 and a bias current generating circuit 20 ;

The bias current generating circuit 20 generates a first bias current, a second bias current and a third bias current;

The bias current generating circuit 20 includes MOS tubes M5, M6, M7, M8, M9, M10, M11, M12, M22, M23 and two resistors, wherein the MOS tubes M5, M6, M7 and M8 form a common source and common gate current mirror, the bias current is provided by the power supply I2, the common source and common gate current mirror generates a first bias current and a second bias current, and increases the power supply rejection ratio of the error amplifier AMP, wherein the first bias current is input to the first-stage amplifier circuit 21 through the drain of the MOS tube M5, and the second bias current is input to the second-stage amplifier circuit 22 through the drain of the MOS tube M7;

The first-stage amplifier circuit 21 includes MOS tubes M1, M2, M3, M4 and M13, the first bias current is input to the source electrodes of the MOS tubes M1 and M2, the gate of the MOS tube M1 is the negative electrode of the error amplifier AMP, the gate of the MOS tube M2 is the positive electrode of the error amplifier AMP, the drain of the MOS tube M1 is electrically connected to the drain of the MOS tube M3, the drain of the MOS tube M2 is electrically connected to the drain of the MOS tube M4, the sources of the MOS tubes M3, M4 and M13 are grounded respectively, and the gate of the MOS tube M3, the gate of the MOS tube M4, the gate and the drain of the MOS tube M13 are electrically connected to the power supply V1 respectively;

In addition, in this embodiment, in order to ensure the frequency characteristics and stability of the first-stage amplifier circuit 20 when in use, the drains of the MOS tubes M1 and M2 are respectively connected to compensation capacitors;

The secondary amplifier circuit 22 includes MOS tubes M14, M15, M16, M17, M18 and M19. The sources of the MOS tubes M14 and M15 are electrically connected to the power supply V2 respectively. The gate of the MOS tube M14 is electrically connected to the drain of the MOS tube M14, the gate of the MOS tube M15 and the drain of the MOS tube M16 respectively. The drain of the MOS tube M15 is electrically connected to the drain of the MOS tube M17. The gates of the MOS tubes M16 and M17 are respectively input with a second bias current. The source of the MOS tube M16 is electrically connected to the drain of the MOS tube M2 and the drain of the MOS tube M18 respectively. The source electrodes of the MOS tube M17 are electrically connected to the drain electrodes of the MOS tube M1 and the source electrodes of the MOS tube M19, respectively; the gate electrodes of the MOS tubes M18 and M19 are respectively input with the enable voltage V3 and the enable voltage V4, the enable voltage V3 and the enable voltage V4 turn on the MOS tubes M18 and M19, and the drain electrodes of the MOS tubes M18 and M19 are respectively grounded; in actual use, the double-terminal output voltage of the first-stage amplifier circuit 21 is input to the source electrodes of the MOS tubes M16 and M17, and the second-stage amplifier circuit 22 converts the double-terminal input into a single voltage and outputs it to the third-stage amplifier circuit 23;

The three-stage amplifier circuit 23 includes MOS tubes M20 and M21. The MOS tubes M21 and M22 form a current mirror structure. The power supply I2 provides a third bias current to the three-stage amplifier circuit 23. The third bias current is input to the gate of the MOS tube M21. The source of the MOS tube M20 is electrically connected to the power supply V2. The gate of the MOS tube M20 is electrically connected to the drain of the power tube M15. The drain of the MOS tube M20 is electrically connected to the gate of the output tube MN1 respectively. The third bias current is input to the gate of the MOS tube M21. The source of the MOS tube M21 is grounded.

During the design process, all MOS tubes in the error amplifier AMP can be NMOS tubes or PMOS tubes.

As an improvement, in the present embodiment, the drains of the MOS tubes M18 and M19 are grounded through the trimming module, and the trimming module includes N-type MOS tubes M60, M61, M62, M63, M64, M65, M66 and M67. The drains of the MOS tubes M60, M61, M62 and M63 are electrically connected to the drains of the MOS tubes M18 and M19, respectively. The gates of the MOS tubes M60, M61, M62 and M63 are respectively connected to the first control signal EN1, the second control signal EN2, the third control signal EN3 and the fourth control signal EN4. The sources of the MOS tubes M60, M61, M62 and M63 are respectively electrically connected to the drains of the MOS tubes M64, M65, M66 and M67, respectively. The gates of the MOS tubes M64, M65, M66 and M67 are respectively connected to the voltage Vbias, and the sources of the MOS tubes M64, M65, M66 and M67 are grounded.

In actual use, the corresponding MOS tubes can be turned on or off by controlling the high and low levels of the first control signal EN1, the second control signal EN2, the third control signal EN3 and the fourth control signal EN4. When one or more of the MOS tubes M60, M61, M62 and M63 are turned off, the bias current of the secondary amplifier circuit 22 will be changed, thereby reducing the offset of the error amplifier.

The working principle of the voltage clamping circuit of the present invention is as follows: in actual use, if the voltage V_SENSE decreases, the voltage input to the secondary amplifier circuit 22 will increase, and the increased voltage is input to the gate of the MOS tube M15, so that the voltage input to the gate of the MOS tube M20 becomes smaller, and the MOS tube M20 has a smaller input voltage at its gate, and the drain output voltage of the MOS tube M20 increases, that is, the gate voltage input to the output tube MN1 by the error amplifier AMP increases, thereby increasing the reduced voltage V_SENSE, achieving the effect of voltage clamping; if the voltage V_SENSE decreases, the voltage input to the gate of the MOS tube M15 decreases, and the gate of the MOS tube M20 decreases, so that the gate of the MOS tube M20 decreases, and the gate of the output tube MN1 decreases, thereby increasing the reduced voltage V_SENSE, and achieving the effect of voltage clamping; If SENSE increases, then conversely, the gate voltage input from the drain of the MOS tube M20 to the output tube MN1 becomes smaller; if the voltage V_DRV increases, the voltage input from point A to the secondary amplifier circuit 22 will become smaller, and the voltage input from the secondary amplifier circuit 22 to the tertiary amplifier circuit 23 will become smaller, that is, the gate voltage of the MOS tube M20 will become smaller, so the gate voltage input to the output tube MN1 will become larger, so that the drain voltage of the first MOS tube M101 becomes larger, and the drain voltage of the second MOS tube M102 is kept the same, so that the voltage clamping effect can be achieved.

In a certain implementation, the ungrounded end of the sampling resistor Rsense is electrically connected to the digital-to-analog conversion interface of the MCU, and the MCU performs analog-to-digital conversion on the voltage of the sampling resistor Rsense to achieve current detection.

In FIG4 , IDRV is the current to be detected, Isense is the detection current flowing through the sampling resistor Rsense, MNDRV is the drain voltage of the first power tube M101, and MNsense is the drain voltage of the second power tube M102. It can be seen from FIG4 that during simulation, the drain voltage difference between the first power tube M101 and the second power tube M102 is only 0.7MV, Isense is the sampling current after the sampling ratio is 1:1000, which is 1.0339mA, and IDRV is the current to be sampled, which is 969.72mA. The absolute accuracy of the sampled current is about 6%.

In summary, the present invention has the following effects when actually used:

1: The sampling circuit 10 is composed of at least two first MOS tubes M101 connected in parallel. Under the premise of ensuring a high sampling ratio, it avoids the size of a single sampling tube being too large when a higher sampling ratio is required, and also has better layout matching;

2: The drain voltage of the first MOS tube M101 and the drain voltage of the first and second MOS tubes M102 are clamped to the same potential through the error amplifier AMP. When the gate voltage of the first MOS tube M101 and the gate voltage of the second MOS tube M102 are the same, the first MOS tube M101 and the second MOS tube M102 can be linearly turned on, thereby ensuring the sampling accuracy of the current mirror circuit 1. In this way, there is no need to set an additional high-precision sampling resistor Rsense when a high sampling ratio is required;

3: In actual use, by adjusting the current conversion ratio of the output cascode current mirror circuit 3, the requirement for the sampling resistor Rsene at a high sampling ratio can be reduced; in addition, by adjusting the output impedance of the power tubes MP3 and MP4 of the output cascode current mirror circuit 3, the power supply rejection ratio can be improved, thereby increasing the sampling accuracy of the current mirror circuit;

4: In actual use, the present invention can be applied to the motor driver chip to perform current sampling on the low side, which reduces power consumption and costs, and also allows the detection of motor winding current during the slow decay of the driving and braking low sides, so that the detection current can be connected in the bidirectional brushed DC motor. When the motor driver chip is in an independent PWM mode and the two low-side MOSFETs are transmitting current at the same time, both sampling currents can be input into the output cascode current mirror circuit. At this time, the detection current flowing through the sampling resistor Rsense is the sum of the currents of the two low-side MOSFETs, which can achieve a sampling ratio of 1:1000 and the absolute error between the induced current and the sampled current is 6%.

The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims (4)

1. A current sampling circuit, characterized by: the circuit comprises a current mirror circuit, a voltage clamping circuit and an output cascode current mirror circuit; the current mirror circuit comprises a sampling circuit and a mirror circuit, the sampling circuit comprises at least two first MOS tubes, the drains of all the first MOS tubes are respectively input with detection current, the gates of all the first MOS tubes are input with a first driving voltage VIN, and the sources of all the first MOS tubes are grounded; the mirror circuit comprises at least two second MOS tubes, all the second MOS tubes are sequentially connected in series, wherein the series connection means that the source electrode of the last second MOS tube is electrically connected with the drain electrode of the next second MOS tube, the drain electrode of the first second MOS tube inputs a first mirror current to the output cascoded current mirror circuit, the source electrode of the last second MOS tube is grounded, and the grid electrodes of all the second MOS tubes respectively input the first driving voltage VIN; the output cascode current mirror circuit converts the first image current proportion into a second image current, and the second image current is input to a sampling resistor Rsense; the voltage clamping circuit clamps the drain voltage of the first MOS tube and the drain voltage of the second MOS tube to a target potential;

The voltage clamping circuit comprises an error amplifier AMP and an output pipe MN1, wherein the positive electrode of the error amplifier AMP is electrically connected with the drain electrode of the first MOS tube, the negative electrode of the error amplifier is electrically connected with the drain electrode of the first second MOS tube, an output signal of the error amplifier is input to the grid electrode of the output pipe MN1, and the first mirror current is input to the output cam current mirror circuit through the source electrode and the drain electrode of the output pipe MN 1;

The error amplifier comprises a primary amplifying circuit, a secondary amplifying circuit, a tertiary amplifying circuit and a bias current generating circuit; the bias current generating circuit generates a first bias current, a second bias current and a third bias current; the first-stage amplifying circuit comprises MOS tubes M1, M2, M3, M4 and M13, wherein the first bias current is input to sources of the MOS tubes M1 and M2, a grid electrode of the MOS tube M1 is a negative electrode of an error amplifier AMP, a grid electrode of the MOS tube M2 is a positive electrode of the error amplifier AMP, a drain electrode of the MOS tube M1 is electrically connected with a drain electrode of the MOS tube M3, a drain electrode of the MOS tube M2 is electrically connected with a drain electrode of the MOS tube M4, sources of the MOS tubes M3, M4 and M13 are respectively grounded, and a grid electrode of the MOS tube M3, a grid electrode of the MOS tube M4, a grid electrode of the MOS tube M13 and a drain electrode are respectively electrically connected with a power supply V1; the secondary amplifying circuit comprises MOS tubes M14, M15, M16, M17, M18 and M19, wherein the sources of the MOS tubes M14 and M15 are respectively and electrically connected with a power supply V2, the grid electrode of the MOS tube M14 is respectively and electrically connected with the drain electrode of the MOS tube M14, the grid electrode of the MOS tube M15 and the drain electrode of the MOS tube M16, the drain electrode of the MOS tube M15 is electrically connected with the drain electrode of the MOS tube M17, the grid electrodes of the MOS tubes M16 and M17 are respectively and electrically connected with the drain electrode of the MOS tube M2 and the source electrode of the MOS tube M18, the source electrode of the MOS tube M17 is respectively and electrically connected with the drain electrode of the MOS tube M1 and the source electrode of the MOS tube M19, the grid electrodes of the MOS tubes M18 and M19 are respectively and electrically connected with an enabling voltage V3 and an enabling voltage V4, and the drain electrodes of the MOS tubes M18 and M19 are respectively grounded; the three-stage amplifying circuit comprises MOS tubes M20 and M21, wherein the source electrode of the MOS tube M20 is electrically connected with a power supply V2, the grid electrode of the MOS tube M20 is electrically connected with the drain electrode of the MOS tube M15, the drain electrodes of the MOS tube M20 are respectively electrically connected with the grid electrode of an output tube MN1, a third bias current is input to the grid electrode of the MOS tube M21, and the source electrode of the MOS tube M21 is grounded;

The output cascode current mirror circuit comprises power tubes MP1, MP2, MP3 and MP4, wherein the sources of the power tubes MP1 and MP2 are respectively and electrically connected with a power supply VDD, the drain of the power tube MP1 is electrically connected with the drain of the power tube MP3, the drain of the power tube MP2 is electrically connected with the drain of the power tube MP4, the grid of the power tube MP1 is respectively and electrically connected with the grid of the power tube MP2, the source of the power tube MP3 and the drain of the output tube MN1, the grids of the power tubes MP3 and MP4 are respectively and electrically connected with a driving voltage V5, the source of the power tube MP4 is electrically connected with one end of a sampling resistor Rsense, and the other end of the sampling resistor Rsense is grounded.

2. A current sampling circuit according to claim 1, wherein: the sampling circuit comprises four first MOS tubes, and the mirror image circuit comprises three second MOS tubes.

3. A current sampling circuit according to claim 1, wherein: the drains of the MOS tubes M18 and M19 are grounded through a trimming module, the trimming module comprises MOS tubes M60, M61, M62, M63, M64, M65, M66 and M67, the drains of the MOS tubes M60, M61, M62 and M63 are respectively electrically connected with the drains of the MOS tubes M18 and M19, the gates of the MOS tubes M60, M61, M62 and M63 are respectively connected with a first control signal EN1, a second control signal EN2, a third control signal EN3 and a fourth control signal EN4, the sources of the MOS tubes M60, M61, M62 and M63 are respectively electrically connected with the drains of the MOS tubes M64, M65, M66 and M67, the gates of the MOS tubes M64, M65, M66 and M67 are respectively connected with a voltage Vbias, and the sources of the MOS tubes M64, M65, M66 and M67 are grounded.

4. A current sampling circuit according to claim 1, wherein: and one end of the sampling resistor Rsense which is not grounded is electrically connected with a digital-to-analog conversion interface of the MCU, and the MCU carries out analog-to-digital conversion on the voltage of the sampling resistor Rsense.