CN112786588A - One-time programmable memory unit and manufacturing method thereof and one-time programmable memory - Google Patents
One-time programmable memory unit and manufacturing method thereof and one-time programmable memory Download PDFInfo
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Abstract
本发明公开了一种一次可编程存储单元及其制作方法和一次可编程存储器，涉及半导体器件领域。该一次可编程存储单元，所述存储单元包括串联的控制MOS管和存储MOS管，所述存储MOS管的栅极处于浮置状态，且所述存储MOS管的栅极中包括P型栅和N型栅，所述P型栅和N型栅的接触区形成PN结二极管，以减少所述栅极内的空穴或电子的扩散。本发明技术方案的存储MOS管的栅极中同时包括P型栅和N型栅，P型栅和N型栅的接触区形成了稳定的PN结二极管；在对存储单元进行编程以后，存储在栅极上的电荷因为PN结二极管的存在，改变了栅极上电荷的自由扩散能力，当栅极周围的电介质出现漏电途径时，栅极上的电荷不会轻易的流失，因此可以提高存储单元数据保持的能力。
The invention discloses a one-time programmable storage unit, a manufacturing method thereof, and a one-time programmable memory, and relates to the field of semiconductor devices. In the one-time programmable storage unit, the storage unit includes a control MOS transistor and a storage MOS transistor connected in series, the gate of the storage MOS transistor is in a floating state, and the gate of the storage MOS transistor includes a P-type gate and a storage MOS transistor. The N-type gate, the contact region of the P-type gate and the N-type gate forms a PN junction diode to reduce the diffusion of holes or electrons in the gate. The gate of the storage MOS transistor of the technical solution of the present invention includes both a P-type gate and an N-type gate, and the contact area between the P-type gate and the N-type gate forms a stable PN junction diode; Because of the existence of the PN junction diode, the charge on the gate changes the free diffusion ability of the charge on the gate. When a leakage path occurs in the dielectric around the gate, the charge on the gate will not be easily lost, so the memory cell can be improved. The ability to keep data.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a one-time programmable memory unit, a manufacturing method thereof and a one-time programmable memory.
Background
An OTP (One Time Programmable) device is a non-volatile memory, and the stored information can be stored for a long Time after power is off. The OTP device has the characteristics of supporting one-time information programming, and has wide application range due to simple manufacturing process and lower cost.
The basic principle of the OTP device is to inject charges (electrons or holes) into the floating gate by Hot Carrier Injection (HCI) or FN tunneling, and the change of the charges on the floating gate will cause the change of the threshold voltage Vt of the MOS transistor, so as to achieve the purpose of changing the on and off states of the storage MOS transistor, thereby implementing the storage of "1" and "0". Typically, the floating gate is surrounded by a dielectric layer, such as a silicon oxide, silicon nitride material, or the like. However, due to various defects in these dielectric materials, there is a certain probability that the charges in the floating gate will pass through these defects and leave the floating gate, resulting in the loss of stored information. Furthermore, the floating gate is made of polysilicon (typically single heavy doping, P + or N +), which is conductive and corresponds to a conductor material, i.e. the charges are free to move on the floating gate. Thus, once there is some charge leakage, the charge on the entire floating gate gradually disappears. The existing OTP technology generally focuses on how to optimize the dielectric material, such as changing the elemental composition of silicon (Si), oxygen (O), and nitrogen (N), for example, increasing the thickness of the dielectric layer. But these methods increase process dependence, manufacturing costs and throughput output.
Disclosure of Invention
The invention mainly aims to provide a one-time programmable memory cell, a manufacturing method thereof and a one-time programmable memory, aiming at improving the data retention capability of the memory cell.
In order to achieve the above object, the present invention provides a one-time programmable memory cell, where the memory cell includes a control MOS transistor and a storage MOS transistor connected in series, a gate of the storage MOS transistor is in a floating state, the gate of the storage MOS transistor includes a P-type gate and an N-type gate, the P-type gate and the N-type gate are diffused and contacted with each other, and a contact region between the P-type gate and the N-type gate forms a PN junction diode to reduce diffusion of holes or electrons in the gate.
Preferably, the electrodes connected with the control MOS tube and the storage MOS tube share one doping region.
Preferably, the control MOS transistor and the storage MOS transistor are PMOS transistors.
Preferably, a PN junction diode formed by the P-type gate and the N-type gate in the gate of the storage MOS transistor divides the gate into a P + region and an N + region, wherein majority and minority carriers in the P + region are holes and minority carriers in the P + region are electrons, and majority and minority carriers in the N + region are holes.
The invention also provides a manufacturing method of the one-time programmable memory unit, wherein the one-time programmable memory unit comprises a control MOS tube and a storage MOS tube which are connected in series, and the manufacturing method of the storage MOS tube comprises the following steps:
providing a substrate;
sequentially forming a dielectric layer and a gate layer on a substrate;
simultaneously injecting P-type doping and N-type doping in a gate layer to simultaneously form a P-type gate and an N-type gate in the gate layer, wherein the P-type doping and the N-type doping are in contact with each other in the gate layer to form a PN junction diode so as to reduce the diffusion of holes or electrons in the gate;
and doping the substrate by taking the grid and the grid dielectric layer as masks to form a doped region.
Preferably, the electrodes connected with the control MOS tube and the storage MOS tube share one doping region.
Preferably, the control MOS transistor and the storage MOS transistor are PMOS transistors.
Preferably, a PN junction diode formed by the P-type gate and the N-type gate in the gate of the storage MOS transistor divides the gate into a P + region and an N + region, wherein majority and minority carriers in the P + region are holes and minority carriers in the P + region are electrons, and majority and minority carriers in the N + region are holes.
The invention also provides a one-time programmable memory, which comprises the one-time programmable storage unit.
The grid electrode of the storage MOS tube in the technical scheme of the invention simultaneously comprises a P-type grid and an N-type grid, the P-type grid and the N-type grid are mutually diffused and contacted, and a contact area forms a stable PN junction diode; after the memory cell is programmed, the charge stored on the grid electrode changes the free diffusion capacity of the charge on the grid electrode due to the existence of the PN junction diode, and when a dielectric medium around the grid electrode has a leakage path, the charge on the grid electrode cannot be easily lost, so that the data retention capacity of the memory cell can be improved.
Drawings
Fig. 1 is a top view of a one-time programmable memory cell according to an embodiment of the invention.
Fig. 2 is a cross-sectional view taken along a-a of fig. 1.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is further described below with reference to the accompanying drawings.
The embodiment of the invention provides a one-time programmable memory unit, which comprises a control MOS tube 1 and a storage MOS tube 2 which are connected in series, wherein a grid 201 of the storage MOS tube 2 is in a floating state, the grid 201 of the storage MOS tube 2 comprises a P-type grid and an N-type grid, the P-type grid and the N-type grid are diffused and contacted with each other, and a contact region of the P-type grid and the N-type grid forms a PN junction diode so as to reduce the diffusion of holes or electrons in the grid 201.
Since the gate 201 (i.e. floating gate) of the memory MOS transistor 2 has both a P-type gate (hole, P +) and an N-type gate (electron, N +), since the hole is positive charge and the electron is negative charge, the P-type gate and the N-type gate are diffused on the gate 201 of the memory MOS transistor 2 and form a stable PN junction diode at the contact region of the two, and the gate 201 of the memory MOS transistor 2 can be divided into a P + region 202 and an N + region 203 by taking the contact region of the two as a boundary. The majority and minority carriers in the P + region 202 are holes and the minority carrier is an electron; while the majority and minority carriers in the N + region 203 are electrons and holes. Due to the concentration difference, holes in the P + region 202 will diffuse towards the N + region 203, electrons in the N + region 203 will diffuse towards the P + region 202, and the fixed charges in the contact region of holes and electrons will form a built-in electric field, preventing further diffusion of electrons/holes in the N + region 203/P + region 202 towards another region, and when diffusion and drift under the electric field reach a dynamic balance, the holes and electrons will form a stable diode.
Unlike the one-time programmable memory cell in the prior art, after the memory cell is programmed, the charge stored on the gate 201 of the memory MOS transistor 2 changes the free diffusion capability of the charge due to the presence of the PN junction diode in the embodiment of the present invention. When a leakage path occurs in the dielectric around the gate 201 of the memory MOS transistor 2, the stored charges will not be easily lost due to the blocking of the PN junction diode, so that the data retention capability of the memory cell can be improved.
Preferably, the control MOS transistor 1 and the storage MOS transistor 2 are PMOS transistors.
Specifically, the control MOS transistor 1 and the storage MOS transistor 2 are located on the same N-type substrate 4, the doped regions 102, 103, 204, and 205 are P-type, and the gate 101 of the control MOS transistor 1 is P-type.
Preferably, the drain electrode 103 of the control MOS transistor 1 and the source electrode 204 of the storage MOS transistor 2 share a P-type doped region. In other embodiments, when the control MOS transistor and the storage MOS transistor are NMOS transistors, the source of the control MOS transistor and the drain 204 of the storage MOS transistor share one N-type doped region.
In a specific embodiment, the gate 101 of the control MOS transistor 1 is a word line of a memory cell, and the source 102 is a source of the memory cell; the drain 205 of the memory MOS transistor 2 is a bit line terminal of the memory cell.
Preferably, a PN junction diode formed by the P-type gate and the N-type gate in the gate 201 of the storage MOS transistor 2 divides the gate 201 into a P + region 202 and an N + region 203, wherein majority and minority carriers in the P + region 202 are holes and minority carriers in the N + region 203 are electrons and minority carriers in the N + region 203 are holes.
The embodiment of the invention also provides a manufacturing method of the one-time programmable memory unit, the one-time programmable memory unit comprises a control MOS tube 1 and a storage MOS tube 2 which are connected in series, and the manufacturing method of the storage MOS tube 2 comprises the following steps:
providing a substrate 4;
sequentially forming a dielectric layer and a gate layer on the substrate 4;
simultaneously injecting P-type doping and N-type doping in a gate layer to simultaneously form a P-type gate and an N-type gate in the gate layer, wherein the P-type doping and the N-type doping are in contact with each other in the gate layer to form a PN junction diode so as to reduce the diffusion of holes or electrons in the gate;
and doping the substrate by taking the grid and the grid dielectric layer as masks to form a doped region.
Preferably, the control MOS transistor 1 and the storage MOS transistor 2 are PMOS transistors.
Preferably, the drain electrode 103 of the control MOS transistor 1 and the source electrode 204 of the storage MOS transistor 2 share a P-type doped region. In other embodiments, when the control MOS transistor and the storage MOS transistor are NMOS transistors, the source of the control MOS transistor and the drain 204 of the storage MOS transistor share one N-type doped region.
Preferably, a PN junction diode formed by the P-type gate and the N-type gate in the gate 201 of the storage MOS transistor 2 divides the gate 201 into a P + region 202 and an N + region 203, wherein majority and minority carriers in the P + region 202 are holes and minority carriers in the N + region 203 are electrons and minority carriers in the N + region 203 are holes.
The embodiment of the invention also provides a one-time programmable memory, which comprises the one-time programmable storage unit.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. The one-time programmable memory unit is characterized by comprising a control MOS tube and a storage MOS tube which are connected in series, wherein the grid electrode of the storage MOS tube is in a floating state, the grid electrode of the storage MOS tube comprises a P-type grid and an N-type grid, the P-type grid and the N-type grid are diffused and contacted with each other, and a contact region of the P-type grid and the N-type grid forms a PN junction diode so as to reduce the diffusion of holes or electrons in the grid electrode.
2. One-time programmable memory cell according to claim 1, characterized in that the poles to which the control MOS transistor and the memory MOS transistor are connected share one doped region.
3. The one-time programmable memory cell of claim 2, wherein the control MOS transistor and the storage MOS transistor are PMOS transistors.
4. The one-time programmable memory cell according to claim 1, wherein a PN junction diode formed by the P-type gate and the N-type gate in the gate of the memory MOS transistor divides the gate into a P + region and an N + region, wherein majority electrons and minority electrons in the P + region and majority electrons and minority holes in the N + region.
5. A manufacturing method of a one-time programmable memory unit is characterized in that the one-time programmable memory unit comprises a control MOS tube and a storage MOS tube which are connected in series, and the manufacturing method of the storage MOS tube comprises the following steps:
providing a substrate;
sequentially forming a dielectric layer and a gate layer on a substrate;
simultaneously injecting P-type doping and N-type doping in a gate layer to simultaneously form a P-type gate and an N-type gate in the gate layer, the P-type doping and the N-type doping contacting each other in the gate layer to form a PN junction diode to reduce diffusion of holes or electrons in the gate layer;
and doping the substrate by taking the grid and the grid dielectric layer as masks to form a doped region.
6. One-time programmable memory cell according to claim 5, characterized in that the poles of the control MOS transistor and the storage MOS transistor which are connected share one doped region.
7. The one-time programmable memory cell of claim 6, wherein the control MOS transistor and the storage MOS transistor are PMOS transistors.
8. The one-time programmable memory cell according to claim 5, wherein a PN junction diode formed by the P-type gate and the N-type gate in the gate of the memory MOS transistor divides the gate into a P + region and an N + region, wherein majority electrons and minority electrons in the P + region and majority electrons and minority holes in the N + region.
9. One-time programmable memory, characterized in that it comprises a plurality of one-time programmable memory cells according to any one of claims 1 to 4.
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| CN103594519A (en) * | 2013-11-11 | 2014-02-19 | 苏州智权电子科技有限公司 | Tunneling field effect floating gate transistor and manufacturing method thereof |
| CN105097953A (en) * | 2014-05-13 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semi-floating gate transistor structure |
| CN109712978A (en) * | 2017-10-25 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
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2019
- 2019-11-07 CN CN201911079651.3A patent/CN112786588A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1637798A (en) * | 2004-01-05 | 2005-07-13 | 精工爱普生株式会社 | Display driver and electronic instrument including display driver |
| CN103137626A (en) * | 2011-11-29 | 2013-06-05 | 中国科学院微电子研究所 | Planar floating gate flash memory device and preparation method thereof |
| CN102522408A (en) * | 2011-12-22 | 2012-06-27 | 上海宏力半导体制造有限公司 | One-time programmable memory and manufacturing method |
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Application publication date: 20210511 |