CN112784520B - Integrated circuit time delay detection method and device, storage medium and electronic equipment - Google Patents
Integrated circuit time delay detection method and device, storage medium and electronic equipment Download PDFInfo
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Abstract
The application provides an integrated circuit time delay detection method, an integrated circuit time delay detection device, a storage medium and electronic equipment. The integrated circuit time delay detection method comprises the following steps: obtaining a circuit netlist and a circuit layout of a target integrated circuit to be detected; acquiring a selected target wiring, and acquiring a specified circuit area in the circuit layout based on the target wiring; extracting parasitic parameters of the appointed circuit area according to the circuit netlist to obtain a simplified DSPF netlist file; simulating according to the reduced DSPF netlist file to obtain a first time delay of the target trace in the appointed circuit region; and calculating the target time delay when the target routing is of any length according to the first time delay. Therefore, the target time delay of the target wiring after any length or length change can be calculated by only one simulation, the simulation times can be reduced, and the efficiency is improved.
Description
Technical Field
The present application relates to the field of integrated circuit simulation testing, and in particular, to a method and apparatus for detecting integrated circuit delay, a storage medium, and an electronic device.
Background
In IC design, there are parasitic parameters between interconnect lines that are not required by the design, i.e., the parasitic parameters. The parasitic parameters include parasitic resistance, capacitance, and inductance. In the circuit layout (layout), the distribution of parasitic resistance and parasitic capacitance is complex and dense. Along with the continuous expansion and promotion of the scale and complexity of circuit layout and layout wiring, parasitic parameter files extracted by EDA tools are also larger and larger. In particular, for Memory, there are various repeated units in the circuit layout, and each unit has many traces and MOS transistors, and if the layout is not reduced, the parasitic parameter file extracted will be very large, resulting in long post-imitation (postsim) time.
To obtain the delay of each trace of the Memory circuit, a clock signal is provided as an excitation, although the timing delay of the circuit can be obtained by post-simulation. However, when the length of the wiring changes, the time delay is simulated again, which increases the burden of the simulation flow and is unfavorable for improving the efficiency.
Disclosure of Invention
The embodiment of the application aims to provide an integrated circuit time delay detection method, an integrated circuit time delay detection device, a storage medium and electronic equipment, wherein the target time delay of a target wiring with any length can be calculated by only one simulation, so that the simulation times can be reduced, and the efficiency is improved.
The embodiment of the application provides an integrated circuit time delay detection method, which comprises the following steps:
Obtaining a circuit netlist and a circuit layout of a target integrated circuit to be detected;
Acquiring a selected target wiring, and acquiring a specified circuit area in the circuit layout based on the target wiring;
Extracting parasitic parameters of the appointed circuit area according to the circuit netlist to obtain a simplified DSPF netlist file;
simulating according to the reduced DSPF netlist file to obtain a first time delay of the target trace in the appointed circuit region;
And calculating the target time delay when the target routing is of any length according to the first time delay.
The method provided by the embodiment of the application can calculate the target time delay of the target wiring after any length or length change by only one simulation, can reduce the simulation times and improve the efficiency.
Optionally, in the method for detecting an integrated circuit delay according to the embodiment of the present application, the obtaining the selected target trace, obtaining the specified circuit area in the circuit layout based on the target trace includes:
Acquiring a selected target wiring;
and performing reduction processing on the circuit layout based on the target routing to obtain a designated circuit area, wherein the reduction processing does not influence the first time delay of the target routing on the designated circuit area.
The method provided by the embodiment of the application improves the efficiency of the simulation through the reduction processing, and can reduce the calculated amount.
Optionally, in the integrated circuit delay detection method according to the embodiment of the present application, the simplifying the circuit layout based on the target trace to obtain a specified circuit area includes:
Performing duplicate removal processing on a plurality of functional units on the circuit layout;
And deleting target electronic elements in the preset area, wherein the time delay of the preselected target routing is not influenced, and obtaining a designated circuit area.
Optionally, in the integrated circuit delay detection method according to the embodiment of the present application, the simplifying the circuit layout based on the target trace to obtain a specified circuit area includes:
And deleting target electronic elements in the preset area, wherein the time delay of the preselected target routing is not influenced, and obtaining a designated circuit area.
Optionally, in the method for detecting an integrated circuit delay according to the embodiment of the present application, deleting the target electronic component in the preset area, which does not affect the delay of the preselected target trace, obtains a designated circuit area, including:
acquiring a config configuration file, wherein the config configuration file comprises coordinates of a plurality of electronic elements connected with the target wiring;
and deleting the electronic components which are not connected with the target wiring and are out of the plurality of electronic components as target electronic components according to the config configuration file to obtain a designated circuit area.
Optionally, in the integrated circuit delay detection method according to the embodiment of the present application, the method further includes:
Extracting parasitic parameters of the circuit layout according to the circuit netlist to obtain an original DSPF netlist file; simulating according to the original DSPF netlist file to obtain delay information of the target routing from the input end to the output end;
after the first delay of the target trace in the specified circuit area is obtained by simulation according to the reduced DSPF netlist file, the method further includes:
judging whether the first time delay is correct or not according to the time delay information;
if the target time delay is correct, jumping to the step of calculating the target time delay when the target routing is of any length according to the first time delay;
and if the electronic components are not connected with the target wiring, calibrating the config configuration file, and returning to the step of deleting the electronic components which are not connected with the target wiring and are out of the plurality of electronic components according to the config configuration file as target electronic components.
Optionally, in the method for detecting an integrated circuit delay according to the embodiment of the present application, the calculating, according to the first delay, a target delay when the target trace is of an arbitrary length includes:
Calculating the unit time delay of the unit length of the target wiring according to the first time delay;
and calculating the target time delay of the target routing when the target routing is of any length according to the unit time delay.
Optionally, in the method for detecting an integrated circuit delay according to the embodiment of the present application, the calculating a unit delay of a unit length of the target trace according to the first delay includes:
Calculating the unit time delay of the unit length of the target trace according to a formula t2=t+l×t0, wherein t2 is a first time delay, t is a fixed time delay constant, L is the length of the target trace in the preset area, and t0 is the unit time delay of the unit length of the target trace.
Optionally, in the method for detecting delay of an integrated circuit according to the embodiment of the present application, the target integrated circuit is a memory; the target electronic component is a MOS tube.
In a second aspect, an embodiment of the present application further provides an integrated circuit delay detection device, including:
The first acquisition module is used for acquiring a circuit netlist and a circuit layout of a target integrated circuit to be detected;
The simplifying module is used for acquiring the selected target routing and acquiring a specified circuit area in the circuit layout based on the target routing;
The extraction module is used for extracting parasitic parameters of the appointed circuit area according to the circuit netlist to obtain a simplified DSPF netlist file;
The first simulation module is used for simulating according to the reduced DSPF netlist file to obtain a first time delay of the target wire in the appointed circuit region;
and the calculation module is used for calculating the target time delay when the target routing is of any length according to the first time delay.
In a third aspect, embodiments of the present application also provide an electronic device comprising a processor and a memory storing computer readable instructions which, when executed by the processor, perform the steps of any of the methods described above.
In a fourth aspect, embodiments of the present application also provide a storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of any of the methods described above.
As can be seen from the above, the method and apparatus for detecting integrated circuit delay according to the embodiments of the present application obtain a circuit netlist and a circuit layout of a target integrated circuit to be detected; acquiring a selected target wire, and performing reduction processing on a circuit layout based on the target wire to obtain a designated circuit area, wherein the reduction processing does not affect the first time delay of the target wire on the designated circuit area; extracting parasitic parameters of the appointed circuit area according to the circuit netlist to obtain a simplified DSPF netlist file; simulating according to the reduced DSPF netlist file to obtain a first time delay of the target trace in the appointed circuit region; and calculating the target time delay when the target wire is of any length according to the first time delay, so that the target time delay of the target wire with any length or the target wire with the length changed can be calculated by only one simulation, the simulation times can be reduced, and the efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a first flowchart of an integrated circuit delay detection method in some embodiments of the application.
Fig. 2 is a second flowchart of an integrated circuit delay detection method in some embodiments of the application.
Fig. 3 is a first block diagram of an integrated circuit delay detection device in some embodiments of the application.
Fig. 4 is a second block diagram of an integrated circuit delay detection device in some embodiments of the application.
Fig. 5 is a block diagram of an electronic device in some embodiments of the application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.
In the description of the present application, it should be noted that, the azimuth or positional relationship indicated by the terms "inner", "outer", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship that is commonly put in use of the product of this application, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
It should also be noted that the terms "disposed," "coupled," and "connected" are to be construed broadly, and may be, for example, fixedly coupled, detachably coupled, or integrally coupled, unless otherwise specifically defined and limited; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1, fig. 1 is a flowchart of a method for detecting delay of an integrated circuit according to some embodiments of the application. The integrated circuit time delay detection method comprises the following steps:
s101, obtaining a circuit netlist and a circuit layout of a target integrated circuit to be detected.
S102, acquiring a selected target wiring, and acquiring a specified circuit area in the circuit layout based on the target wiring.
S103, extracting parasitic parameters of the designated circuit area according to the circuit netlist to obtain a simplified DSPF netlist file.
S104, simulating according to the reduced DSPF netlist file to obtain a first time delay of the target trace in the specified circuit area.
S105, calculating the target time delay when the target routing is of any length according to the first time delay.
In the step S101, the target integrated circuit may be a memory array based on MOS transistors, and of course, may be other integrated circuits formed by arranging a plurality of functional units. Such as a liquid crystal display panel or a pixel circuit of an OLED display panel.
In step S102, a local area may be directly framed based on the selected target trace, so as to obtain the specified circuit area. If the target integrated circuit is a memory array based on MOS transistors, the target electronic component is a MOS transistor. The target trace may be one of a plurality of word lines or one of a plurality of bit lines. Of course, the target trace may be formed with a length of a part of the region of one trace.
In step S103, calibre XRC may be used and combined with the circuit netlist to extract parasitic parameters of the specified circuit region, thereby obtaining a reduced DSPF netlist file. Wherein the DSPF (DETAILED STANDARD PARASITIC Format) netlist file describes the actual parasitic capacitance and resistance of each small segment on a wire net in SPICE Format.
In step S104, the reduced DSPF netlist is adopted and combined with the external stimulus to make post-simulation, so as to obtain a time delay t2 of the clock signal from the target trace in the specified circuit area.
In step S105, the unit delay of the unit length of the target trace may be calculated according to the first delay and the length of the target trace in the designated circuit area, so that the target delay under any length condition is calculated according to the unit delay of the unit length of the target trace.
In some embodiments, to increase the simulation speed for the specified circuit area and reduce the calculation amount, the step S101 may further use: and obtaining a selected target wire, and performing reduction processing on the circuit layout based on the target wire to obtain a specified circuit area, wherein the reduction processing does not influence the first time delay of the target wire on the specified circuit area. The compaction process may include deleting target electronic components within the designated circuit area that are independent of the latency of the target trace. Wherein the target trace is determined based on the external stimulus, i.e. to which trace the external stimulus is applied, the trace is determined to be the target trace. When the target electronic component is deleted, a config configuration file is often used.
Wherein, in some embodiments, this step S102 may comprise the sub-steps of: s1021, performing de-duplication processing on a plurality of functional units on the circuit layout; s1022, deleting the target electronic elements in the preset area, wherein the delay of the preselected target routing is not influenced, and obtaining the designated circuit area.
In some embodiments, the step S102 may include only: step S1022, deleting the target electronic components in the preset area, which do not affect the time delay of the preselected target routing, to obtain the designated circuit area. I.e. this step S1021 is not essential.
In this step S1021, if the memory has a plurality of memory arrays, for example, the memory arrays that are repeated therein need to be deleted, thereby reducing the subsequent workload.
In some embodiments, in this step S1022, the following sub-steps may be specifically adopted: s10221, acquiring a config configuration file, wherein the config configuration file comprises coordinates of a plurality of electronic elements connected with the target wiring; s10222, deleting the electronic components which are not connected with the target wiring and are out of the plurality of electronic components as target electronic components according to the config configuration file, and obtaining a designated circuit area. Wherein, the target wire is not connected, i.e. the time delay of the target wire is not influenced.
The combination processing of the circuit netlist and the circuit layout can be adopted, so that the coordinates of each MOS tube of the target integrated circuit on the circuit layout can be obtained. The config configuration file comprises coordinates of a plurality of electronic elements connected with the target wire; then, the electronic components other than these electronic components are deleted as target electronic components. The combination processing of the circuit netlist and the circuit layout can be adopted, so that the coordinates of each MOS tube of the target integrated circuit on the circuit layout can be obtained. Of course, it will be appreciated that the deduplication process is also performed based on the config profile.
Wherein, in some embodiments, this step S105 may comprise the steps of: s1051, calculating unit time delay of unit length of the target wire according to the first time delay; s1052, calculating the target time delay of the target routing when the target routing is of any length according to the unit time delay.
In this step S1051, a unit delay of a unit length of the target trace may be calculated according to a formula t2=t+l×t0, where t2 is a first delay, t is a fixed delay constant, and L is a length of the target trace on the specified circuit area or the target trace of the access simulation. Wherein the fixed delay constant t refers to the delay of the clock. In this step S1052, the actual length of the target trace to be detected may be substituted into the formula t3=t+l×t0, so as to calculate the target delay t3 of the target trace when the target trace is of any length.
For example, in one memory, one memory array thereof has 256 WL (word) word lines and 128 BL (bit line) bit lines. After the circuit layout is simplified to obtain a designated circuit area and parasitic parameters are extracted, a simplified DSPF netlist file is obtained. Then, performing post-simulation of time delay based on the DSPF netlist file to obtain a first time delay t2. Based on the formula t2=t+t0×length (WL), length (WL) =128, where since the word lines and the bit lines are vertically crossed and distributed, the distances between two adjacent bit lines are equal, and thus the length of the word line can be measured by the number of bit lines. The unit delay t0, t0= (t 2-t)/128 of the word line per unit length is calculated. The length of the word line WL is changed to 32, and simulation is not needed, so that new time delay is directly calculated through a formula.
As can be seen from the above, the integrated circuit delay detection method provided by the embodiment of the application obtains the circuit netlist and the circuit layout of the target integrated circuit to be detected; acquiring a selected target wiring, and acquiring a specified circuit area in the circuit layout based on the target wiring; extracting parasitic parameters of the appointed circuit area according to the circuit netlist to obtain a simplified DSPF netlist file; simulating according to the reduced DSPF netlist file to obtain a first time delay of the target trace in the appointed circuit region; and calculating the target time delay when the target wire is of any length according to the first time delay, so that the target time delay of the target wire of any length or the target time delay of the target wire after the length is changed can be calculated by only one simulation, the simulation times can be reduced, and the efficiency is improved.
Referring to fig. 2, fig. 2 is a flowchart of a method for detecting delay of an integrated circuit according to another embodiment of the application. The integrated circuit time delay detection method comprises the following steps:
S201, obtaining a circuit netlist and a circuit layout of a target integrated circuit to be detected.
S2021, performing deduplication processing on the plurality of functional units on the circuit layout.
S20221, acquiring a config configuration file, wherein the config configuration file comprises coordinates of a plurality of electronic elements connected with the target routing.
S20222, deleting the electronic components which are not connected with the target wire and are out of the plurality of electronic components as target electronic components according to the config configuration file, so as to obtain a specified circuit area.
S203, extracting parasitic parameters of the designated circuit area according to the circuit netlist to obtain a simplified DSPF netlist file.
S204, simulating according to the reduced DSPF netlist file to obtain a first time delay of the target trace in the specified circuit area.
S205, extracting parasitic parameters of the circuit layout according to the circuit netlist to obtain an original DSPF netlist file; and simulating according to the original DSPF netlist file to obtain time delay information of the target routing from the input end to the output end.
S206, judging whether the first time delay is correct or not according to the time delay information.
If yes, step S207 is skipped to step S209.
And S208, if the electronic components are incorrect, calibrating the config configuration file, and returning to the step of deleting the electronic components which are not connected with the target wire and are out of the plurality of electronic components according to the config configuration file as target electronic components.
S209, calculating the target time delay of the target trace when the circuit layout is of any length according to the first time delay.
The steps S201 to S204 correspond to the steps S101 to S104 in the above embodiment, and the step S209 corresponds to the step S105, respectively, and thus the description will not be repeated. Here, this step S2021 is not an indispensable step.
In step S205, since the circuit layout is not reduced, the parasitic parameters extracted by the circuit layout are not reduced. The delay information may be delay t1 corresponding to the target trace when the circuit layout is not subjected to reduction processing, that is, when simulation is performed, external excitation is only applied to the target trace, so as to measure delay t1 of the target trace. Of course, the delay information may also include delay t1 corresponding to each trace on the circuit layout when the circuit layout is not reduced.
In step S206, the delay t1 may be used as a criterion for determining whether the reduction process is correct or whether the first delay t2 is correct. If the first delay t2 of the target trace is equal to the delay t1, the simplifying process is not problematic, and the first delay t2 is correct.
In step S207, if the compaction operation is correct, the first delay t1 detected is also correct, so that the process jumps directly to the last step, and the target delay at any length is calculated based on the first delay.
If the description is incorrect, the electronic component associated with the target trace is deleted in step S208, and therefore the config profile needs to be calibrated. And returning to the step of deleting the electronic components which are not connected with the target wire and are out of the plurality of electronic components according to the config configuration file as target electronic components after the calibration is completed.
According to the embodiment of the application, the parasitic parameters of the non-reduced circuit layout are extracted to obtain the original DSPF netlist file, so that the delay information of the target routing from the input end to the output end can be simulated based on the original DSPF netlist file, and whether the previous reduced operation is wrong or not is verified based on the delay information, thereby ensuring the accuracy of the second delay and further ensuring the accuracy of the calculated target delay.
Referring to fig. 3, fig. 3 is a block diagram of some embodiments of the application. The integrated circuit delay detection device comprises: the device comprises an acquisition module 301, a reduction module 302, an extraction module 303, a first simulation module 304 and a calculation module 305.
The acquiring module 301 is configured to acquire a circuit netlist and a circuit layout of a target integrated circuit to be detected. The target integrated circuit can be a storage array based on MOS tubes, and of course, the target integrated circuit can also be other integrated circuits formed by arranging a plurality of functional units. Such as a liquid crystal display panel or a pixel circuit of an OLED display panel.
The reduction module 302 is configured to obtain a selected target trace, and obtain a specified circuit area in the circuit layout based on the target trace. A local area may be selected based on the selected target trace direct frame to obtain the designated circuit area. Of course, in some embodiments, to increase the simulation speed for the specified circuit area and reduce the calculation amount, it is also possible to use: and performing reduction processing on the circuit layout based on the target routing to obtain a designated circuit area, wherein the reduction processing does not influence the first time delay of the target routing on the designated circuit area. The compaction process may include deleting target electronic components within the predetermined area that are not related to the delay of the target trace. If the target integrated circuit is a memory array based on MOS transistors, the target electronic component is a MOS transistor. The target trace may be one of a plurality of word lines or one of a plurality of bit lines. Wherein the target trace is determined based on the external stimulus, i.e. to which trace the external stimulus is applied, the trace is determined to be the target trace. When the target electronic component is deleted, a config configuration file is often used.
The extracting module 303 is configured to extract parasitic parameters of the specified circuit area according to the circuit netlist, so as to obtain a reduced DSPF netlist file. Calibre XRC may be employed in combination with the circuit netlist to extract the parasitic parameters of the specified circuit region, resulting in a reduced DSPF netlist file. Wherein the DSPF (DETAILED STANDARD PARASITIC Format) netlist file describes the actual parasitic capacitance and resistance of each small segment on a trace in SPICE Format.
The first simulation module 304 is configured to simulate, according to the reduced DSPF netlist file, to obtain a first delay of the target trace in the specified circuit area. And adopting the simplified DSPF netlist file and combining the external stimulus to perform post-simulation to obtain the time delay t2 of the clock signal from the target routing in the appointed circuit area.
The calculating module 305 is configured to calculate, according to the first delay, a target delay of the target trace when the circuit layout is of an arbitrary length. The unit time delay of the unit length of the target wire can be calculated according to the first time delay and the length of the target wire in the designated circuit area, so that the target time delay under any length condition can be calculated according to the unit time delay of the unit length of the target wire.
Wherein, in some embodiments, the reduction module 302 is configured to: performing duplicate removal processing on a plurality of functional units on the circuit layout; and deleting target electronic elements in the preset area, wherein the time delay of the preselected target routing is not influenced, and obtaining a designated circuit area.
Or in some embodiments, the compaction module 302 is configured to: and deleting target electronic elements in the preset area, wherein the time delay of the preselected target routing is not influenced, and obtaining a designated circuit area.
Wherein if the memory has multiple memory arrays, then the repeated memory arrays need to be deleted, thereby reducing the subsequent workload. When deleting the target electronic component, acquiring a config configuration file, wherein the config configuration file comprises coordinates of a plurality of electronic components connected with the target wiring; and deleting the electronic components which are not connected with the target wiring and are out of the plurality of electronic components as target electronic components according to the config configuration file to obtain a designated circuit area. Wherein, the target wire is not connected, i.e. the time delay of the target wire is not influenced.
The combination processing of the circuit netlist and the circuit layout can be adopted, so that the coordinates of each MOS tube of the target integrated circuit on the circuit layout can be obtained. The config configuration file comprises coordinates of a plurality of electronic elements connected with the target wire; then, the electronic components other than these electronic components are deleted as target electronic components. The combination processing of the circuit netlist and the circuit layout can be adopted, so that the coordinates of each MOS tube of the target integrated circuit on the circuit layout can be obtained.
Wherein in some embodiments, the computing module 305 is specifically configured to: calculating the unit time delay of the unit length of the target wiring according to the first time delay; and calculating the target time delay of the target routing when the target routing is of any length according to the unit time delay. The unit delay of the unit length of the target trace may be calculated according to a formula t2=t+l×t0, where t2 is a first delay, t is a fixed delay constant, and L is the length of the target trace on the specified circuit area or the target trace of the access simulation. Wherein the fixed delay constant t refers to the delay of the clock. The actual length of the target trace to be detected may be substituted into the formula t3=t+l×t0, so as to calculate the target time delay t3 of the target trace when the target trace is of any length. For example, in one memory, one memory array thereof has 256 WL (word) word lines and 128 BL (bit line) bit lines. After the circuit layout is simplified to obtain a designated circuit area and parasitic parameters are extracted, a simplified DSPF netlist file is obtained. Then, performing post-simulation of time delay based on the DSPF netlist file to obtain a first time delay t2. Based on the formula t2=t+t0×length (WL), length (WL) =128, where since the word lines and the bit lines are vertically crossed and distributed, the distances between two adjacent bit lines are equal, and thus the length of the word line can be measured by the number of bit lines. The unit delay t0, t0= (t 2-t)/128 of the word line per unit length is calculated. The length of the word line WL is changed to 32, and simulation is not needed, so that new time delay is directly calculated through a formula.
In some embodiments, as shown in fig. 4, the integrated circuit delay detection device further includes: a second simulation module 306, a determination module 307, a jump module 308, and a calibration module 309.
The second simulation module 306 is configured to extract parasitic parameters of the circuit layout according to the circuit netlist, so as to obtain an original DSPF netlist file; and simulating according to the original DSPF netlist file to obtain time delay information of the target routing from the input end to the output end.
The judging module 307 is configured to judge whether the first delay is correct according to the delay information.
The skip module 308 is configured to skip to the calculation module if the skip is correct.
The calibration module 309 is configured to calibrate the config configuration file if the configuration file is incorrect, and return to the reduction module 302, so that the reduction module 302 performs reduction on electronic components, which are not connected to the target trace, other than the plurality of electronic components as target electronic components according to the config configuration file.
As can be seen from the above, the integrated circuit delay detection device provided by the embodiment of the application obtains the circuit netlist and the circuit layout of the target integrated circuit to be detected; acquiring a selected target wiring, and acquiring a specified circuit area in the circuit layout based on the target wiring; extracting parasitic parameters of the appointed circuit area according to the circuit netlist to obtain a simplified DSPF netlist file; simulating according to the reduced DSPF netlist file to obtain a first time delay of the target trace in the appointed circuit region; and calculating the target time delay when the target wire is of any length according to the first time delay, so that the target time delay of the target wire of any length or the target time delay of the target wire after the length is changed can be calculated by only one simulation, the simulation times can be reduced, and the efficiency is improved.
Please refer to fig. 5, fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and the present application provides an electronic device 4, including: a processor 401 and a memory 402, the processor 401 and the memory 402 being interconnected and in communication with each other by a communication bus 403 and/or other form of connection mechanism (not shown), the memory 402 storing a computer program executable by the processor 401, which, when run by a computing device, is executed by the processor 401 to perform the method in any of the alternative implementations of the embodiments described above.
The present application provides a storage medium that, when executed by a processor, performs the method of any of the alternative implementations of the above embodiments. The storage medium may be implemented by any type of volatile or non-volatile Memory device or combination thereof, such as static random access Memory (Static Random Access Memory, SRAM), electrically erasable Programmable Read-Only Memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-Only Memory, EEPROM), erasable Programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), programmable Read-Only Memory (PROM), read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic disk, or optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (9)
1. An integrated circuit delay detection method, comprising:
Obtaining a circuit netlist and a circuit layout of a target integrated circuit to be detected;
Acquiring a selected target wiring, and acquiring a specified circuit area in the circuit layout based on the target wiring;
Extracting parasitic parameters of the appointed circuit area according to the circuit netlist to obtain a simplified DSPF netlist file;
simulating according to the reduced DSPF netlist file to obtain a first time delay of the target trace in the appointed circuit region;
calculating the target time delay when the target routing is of any length according to the first time delay;
The method for obtaining the specified circuit area in the circuit layout based on the target routing comprises the following steps:
Deleting target electronic elements which do not affect the time delay of a preselected target wiring in a preset area to obtain a designated circuit area, wherein the target electronic elements are electronic elements which are not connected with the target wiring;
The deleting the target electronic element in the preset area, which does not affect the time delay of the preselected target routing, obtains a designated circuit area, and includes:
acquiring a config configuration file, wherein the config configuration file comprises coordinates of a plurality of electronic elements connected with the target wiring;
and deleting the electronic components which are not connected with the target wiring and are out of the plurality of electronic components as target electronic components according to the config configuration file to obtain a designated circuit area.
2. The method of claim 1, wherein prior to deleting target electronic components within the predetermined area that do not affect the delay of the preselected target trace, the method further comprises:
and performing duplicate removal processing on a plurality of functional units on the circuit layout.
3. The integrated circuit delay detection method of claim 1, wherein the method further comprises:
Extracting parasitic parameters of the circuit layout according to the circuit netlist to obtain an original DSPF netlist file; simulating according to the original DSPF netlist file to obtain delay information of the target routing from the input end to the output end;
after the first delay of the target trace in the specified circuit area is obtained by simulation according to the reduced DSPF netlist file, the method further includes:
judging whether the first time delay is correct or not according to the time delay information;
if the target time delay is correct, jumping to the step of calculating the target time delay when the target routing is of any length according to the first time delay;
and if the electronic components are not connected with the target wiring, calibrating the config configuration file, and returning to the step of deleting the electronic components which are not connected with the target wiring and are out of the plurality of electronic components according to the config configuration file as target electronic components.
4. The method for detecting a delay of an integrated circuit according to claim 1, wherein calculating the target delay when the target trace is of an arbitrary length according to the first delay comprises:
Calculating the unit time delay of the unit length of the target wiring according to the first time delay;
and calculating the target time delay of the target routing when the target routing is of any length according to the unit time delay.
5. The method of claim 4, wherein calculating the unit delay per unit length of the target trace according to the first delay comprises:
Calculating the unit time delay of the unit length of the target trace according to a formula t2=t+L×t0, wherein t2 is the first time delay, t is a fixed time delay constant, t0 is the unit time delay of the unit length of the target trace, and L is the length of the target trace in the designated circuit area.
6. The method of claim 1 or 2, wherein the target integrated circuit is a memory; the target electronic component is a MOS tube.
7. An integrated circuit delay detection device, comprising:
The first acquisition module is used for acquiring a circuit netlist and a circuit layout of a target integrated circuit to be detected;
The simplifying module is used for acquiring the selected target routing and acquiring a specified circuit area in the circuit layout based on the target routing;
The extraction module is used for extracting parasitic parameters of the appointed circuit area according to the circuit netlist to obtain a simplified DSPF netlist file;
The first simulation module is used for simulating according to the reduced DSPF netlist file to obtain a first time delay of the target wire in the appointed circuit region;
The calculation module is used for calculating the target time delay when the target routing is of any length according to the first time delay;
wherein, the simplifying module is used for:
deleting target electronic elements which do not affect time delay of a preselected target wiring in a preset area to obtain a designated circuit area, wherein the target electronic elements are electronic elements which are not connected with the target wiring
The deleting the target electronic element in the preset area, which does not affect the time delay of the preselected target routing, obtains a designated circuit area, and includes:
acquiring a config configuration file, wherein the config configuration file comprises coordinates of a plurality of electronic elements connected with the target wiring;
and deleting the electronic components which are not connected with the target wiring and are out of the plurality of electronic components as target electronic components according to the config configuration file to obtain a designated circuit area.
8. An electronic device comprising a processor and a memory storing computer readable instructions that, when executed by the processor, perform the method of any of claims 1-6.
9. A storage medium having stored thereon a computer program which, when executed by a processor, performs the method of any of claims 1-6.
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| CN113283212A (en) * | 2021-05-24 | 2021-08-20 | 海光信息技术股份有限公司 | Method and device for analyzing winding quality of integrated circuit, electronic equipment and storage medium |
| CN113609812B (en) * | 2021-08-03 | 2024-02-23 | 湖南大学 | Method, equipment and medium for predicting line delay at netlist level based on LightGBM |
| CN114071127A (en) * | 2021-11-10 | 2022-02-18 | 深圳Tcl新技术有限公司 | Live video delay testing method and device, storage medium and electronic equipment |
| CN114357925A (en) * | 2022-01-10 | 2022-04-15 | 长鑫存储技术有限公司 | Parasitic parameter acquisition method and device |
| CN118468766B (en) * | 2024-05-23 | 2024-12-06 | 南京集成电路设计服务产业创新中心有限公司 | Electromagnetic side channel safety assessment method |
| CN118607456B (en) * | 2024-08-07 | 2025-01-03 | 杭州广立微电子股份有限公司 | Method and device for generating integrated circuit post-simulation layout and readable storage medium |
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