CN112783810B - Application-oriented multi-channel SRIO DMA transmission system and method - Google Patents

Abstract

The invention discloses an application-oriented multichannel SRIO DMA transmission system, which comprises a DSP subsystem and an FPGA subsystem, wherein the DSP subsystem comprises a DSP, an SRIO receiving and transmitting hardware module, a plurality of DMA downlink source buffer memories and a plurality of DMA uplink destination buffer memories; the FPGA subsystem comprises an SRIO control module, a DMA downlink virtual control module, a DMA uplink virtual control module, an external interface, a plurality of DMA downlink destination buffer memories and a plurality of DMA uplink source buffer memories; the method can be flexibly configured according to application bandwidth, priority, instantaneity and the like, various requirements of an application layer are met, and the transmission efficiency of the system is improved.

Description

An application-oriented multi-channel SRIO DMA transmission system and method

technical field

The invention relates to the field of data processing and transmission of the test and simulation of the secondary system of an intelligent substation, in particular to an application-oriented multi-channel SRIO DMA transmission system and an application-oriented multi-channel SRIO DMA transmission method.

Background technique

With the large-scale promotion and application of smart substations, the testing and simulation of secondary equipment in substations such as merging units, protection devices, intelligent terminals, and measurement and control devices are becoming more and more extensive. Relay testers, merged unit testers and other test instruments are used. Due to the small number of interfaces, weak data calculation capabilities, and low bus bandwidth, these testers can only test a single device, but not a whole interval or multiple protection devices or Overall testing and simulation of protection devices, merging units, and intelligent terminals. The overall test and simulation of the whole interval or multiple devices is more complete and sufficient for the test and simulation, and can be closer to the actual operation of the substation. However, the overall testing and simulation of multiple secondary devices, such as merging units, protection devices, intelligent terminals, and measurement and control devices, put forward higher requirements for the computing power, data transmission capacity, and real-time processing time of the entire test simulation platform. .

DSPs with strong computing power and FPGAs with data transmission capabilities are often the most suitable solutions. DSP is responsible for the calculation, state control, and grouping of each message task (SV, Goose, FT3, analog power source, etc.), while The FPGA is responsible for receiving or sending these messages to the corresponding optical network port, FT3 port, DA converter, etc. in a certain real-time manner. When the test simulation system needs to simulate these IEDs of the whole interval or the whole station, the calculation amount and data transmission amount of each message task (SV, Goose, FT3, analog power source, etc.) will also be relatively large, and the bandwidth of each message will be relatively large. The estimation is as follows: the data volume of SV is 1Gbps according to the limit bandwidth; Goose shift events are shifted according to the limit of 2 milliseconds, and each event is up to 800 bytes, then the limit flow of Goose is 160Mbps; the flow of FT3 interface is 28.8Mbps according to 18 interfaces; According to 24 channels of voltage and 27 channels of current configuration, the bandwidth is 261.12Mbps; the overall bandwidth is 1.449Gbs. Therefore, the data communication between DSP and FPGA becomes the key to the performance of the whole system.

Generally, DSP and FPGA use SRIO bus for mass data transmission, which has the characteristics of large bus bandwidth and low protocol overhead. The SRIO bus can be the data read and write initiated by the DSP actively, or the data read and write initiated by the FPGA. Often the existing DMA transmission of these SRIOs adopts a layered mode, that is, the message sending and receiving tasks at the application layer arrange the data calculation and put them in the memory space of the respective application side, and the data is sent and received by the SRIO at the driver layer. The program copies the data of each application layer to the driver layer and repackages them one by one and adds the necessary label fields; when receiving data from the FPGA side, the FPGA first informs the DSP through an interrupt, and then the driver layer SRIO on the DSP side receives the program to actively read The data on the FPGA side, and the data corresponding to the application layer is decoded according to a certain packet format, and copied to the application layer memory space. This processing method of multiple copies, multiple groups of packets, and multiple packet classifications takes up a lot of DSP processing time, and cannot guarantee application requirements such as SV and analog quantities with large amounts of data and high real-time performance.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an application-oriented multi-channel SRIODMA transmission system and an application-oriented multi-channel SRIO DMA transmission method in view of the above-mentioned defects in the prior art.

The above-mentioned purpose of the present invention is achieved through the following technical solutions:

An application-oriented multi-channel SRIO DMA transmission system includes a DSP subsystem and an FPGA subsystem,

The DSP subsystem includes: DSP, SRIO transceiver hardware module, multiple DMA downstream source buffer memories and multiple DMA upstream destination buffer memories;

The FPGA subsystem includes: SRIO control module, DMA downstream virtual control module, DMA upstream virtual control module, external interface, multiple DMA downstream destination buffer memories and multiple DMA upstream source buffer memories,

Each application corresponds to a DMA virtual channel. The DMA virtual channel includes a DMA downlink virtual channel and a DMA uplink virtual channel.

The DMA downlink virtual channel includes the DMA downlink source buffer memory, the DMA downlink virtual control module, and the DMA downlink destination buffer memory corresponding to the application program, respectively.

The DMA downlink virtual control module includes a first downlink channel register for storing the state of the DMA downlink source buffer memory, a second downlink channel register for storing the transmission length of the transmit data to be transmitted in the DMA downlink source buffer memory, and a It is used to store the first address of the transmit data to be transmitted in the DMA downlink source buffer memory,

The DMA upstream virtual channel includes the DMA upstream source buffer memory, the DMA upstream virtual control module, and the DMA upstream destination buffer memory corresponding to the application program, respectively.

The DMA upstream virtual control module includes a first upstream channel register for storing the storage state of the DMA upstream destination buffer memory, a second upstream channel register for storing the transmission length of the received data to be transmitted in the DMA upstream source buffer memory, and a The third upstream channel register for storing the first address of the received data to be transmitted in the DMA upstream source buffer memory.

The DMA downlink source buffer memory includes a first downlink source ping-pong memory and a second downlink source ping-pong memory,

The 0th bit and the 1st bit of the first downlink channel register respectively correspond to the current state of the first downlink source ping-pong memory and the second downlink source ping-pong memory of the DMA downlink source buffer memory,

The DMA upstream destination buffer memory includes a first upstream destination ping-pong memory and a second upstream destination ping-pong memory,

Bit 0 and bit 1 of the first upstream channel register respectively correspond to the idle states of the first upstream destination ping-pong memory and the second upstream destination ping-pong memory.

An application-oriented multi-channel SRIO DMA transmission method, comprising the steps of data transmission:

In step 100, after the DSP is started, the sending task of the DSP acquires and initializes the DMA downlink source buffer memory,

Step 101, when the sending task has to send data to send, the DSP uses the register bus EMIF to query the first downlink channel register of the DMA downlink virtual control module to determine that the DMA downlink source buffer memory is in a transmission completion state;

Step 102: The sending task fills multiple sending data packets into the DMA downlink source buffer memory in turn. The first send data packet starts from the 5th byte until the DMA downlink source buffer memory is filled, and the last one is guaranteed. The integrity of the sending data packet, when the sending data packet to be transmitted fills the DMA downstream source buffer memory, modify the 32 bits of the first 4 bytes of the DMA downstream source buffer memory to the following definition:

The 7th to 0th bits: the serial number of the sending data packet to be sent, plus 1 after each packet is completed;

The 15th to 8th bits: the number of sending packets currently to be transmitted;

Bits 31 to 16: The total number of bytes of the currently transmitted packet to be transmitted,

Step 103: The transmission task writes the transmission length of the transmission data to be transmitted into the second downlink channel register of the DMA downlink virtual control module through the register bus EMIF, and uses the first address of the DMA downlink source buffer memory as the first address of the transmission data source to be transmitted. Write the third downlink channel register of the DMA downlink virtual control module, and modify the first downlink channel register of the DMA downlink virtual control module to not complete the transmission,

Step 104: The DMA downlink virtual control module polls according to the sending cycle, determines that the DMA downlink virtual channel that has data needs to be scheduled has data, and matches the preset channel bandwidth value, priority, and effective bandwidth of the SRIO bus of the DMA downlink virtual channel. The send data to be transmitted of each DMA downlink virtual channel is sent, that is, according to the channel bandwidth value of the DMA downlink virtual channel, the number of bytes to be sent by the DMA downlink virtual channel in the transmission cycle is calculated, and the number of bytes to be sent by the DMA downlink virtual channel in the transmission cycle is calculated. According to the number of bytes and the effective bandwidth of the SRIO bus, calculate the scheduling time occupied by the DMA downlink virtual channel in the transmission cycle, and send the data to be sent according to the calling time corresponding to the DMA downlink virtual channel according to the priority of the DMA downlink virtual channel;

When sending the data to be sent, the DMA downlink virtual control module first reads the first downlink channel register corresponding to the DMA downlink virtual channel to confirm whether the DMA downlink virtual channel has send data to be transmitted, and if there is send data to be transmitted , then read the transmission length of the transmission data to be transmitted recorded in the second downlink channel register, read the first address of the transmission data to be transmitted recorded in the third downlink channel register, according to the transmission length of the transmission data to be transmitted and The first address of the transmitted data to be transmitted, the AVALONE bus timing for generating the DMA read request,

Step 105: The DMA downlink virtual control module sends the AVALONE bus timing of the DMA read request to the SRIO control module, and the SRIO control module packages the AVALONE bus timing of the DMA read request into an SRIO NREAD command and sends it to the DSP side through the SRIO bus in a serial data format SRIO transceiver hardware module;

Step 106: After the SRIO transceiver hardware module on the DSP side receives the SRIO NREAD command, it parses out the corresponding transmission length of the transmission data to be transmitted and the first address of the transmission data to be transmitted, and uses the transmission data to be transmitted on the DSP side. The transmission length and the first address of the transmission data to be transmitted are based on reading the corresponding transmission data to be transmitted from the DMA downstream source buffer memory, and according to the RESP packet format of the SRIO protocol, the corresponding RESP data packet is generated and responded to the FPGA side. SRIO control module;

Step 107: After the SRIO control module on the FPGA side receives the RESP data packet of the SRIO transceiver hardware module on the DSP side, it parses it into an AVALONE bus read response sequence;

Step 108, after the DMA downlink virtual control module obtains the AVALONE bus read response sequence from the SRIO control module, the corresponding transmission data to be transmitted is written into the DMA downlink destination buffer memory;

Step 109 , the sending module corresponding to the FPGA side reads the sending data to be transmitted by checking the non-empty identifier of the DMA downstream destination buffer memory of the DMA downstream virtual channel, and sends the sending data to be transmitted through the external interface corresponding to the FPGA side.

An application-oriented multi-channel SRIO DMA transmission method, further comprising a data receiving step:

Step 200, after the DSP is started, the receiving task of the DSP acquires and initializes the DMA uplink destination buffer memory,

Step 201, the receiving task clears the first upstream channel register of the DMA upstream virtual control module through the register bus EMIF,

Initialize the third upstream channel register as the first address of the DMA upstream destination buffer memory,

The receiving task on the DSP side will poll each DMA upstream virtual channel corresponding to the first upstream channel register, if the first upstream channel register reflects that the DMA upstream destination buffer memory has received data buffered, then enter step 207, otherwise enter step 202;

In step 202, the receiving module on the FPGA side receives the received data packets from the external interface in real time, and marks the received data packets with a timestamp, and buffers them in the DMA upstream source buffer memory,

The received data packets are filled in the DMA upstream source buffer memory in turn. The first received data packet starts from the 5th byte, and the subsequent received data packets are arranged in sequence until the DMA upstream source buffer memory is full, and finally When a received data packet is complete, when the received data packet to be transmitted is filled, modify the 32 bits of the first 4 bytes of the DMA upstream source buffer memory to the following definition:

The 7th to 0th bits: the serial number of the received data packet to be transmitted, plus 1 after each packet is completed;

Bits 15 to 8: the number of received packets currently to be transmitted;

Bits 31 to 16: the total number of bytes of the received data packet currently to be transmitted;

The total number of bytes of the received data packets currently to be transmitted is updated to the second upstream channel register,

Step 203, the DMA uplink virtual control module polls according to the receiving period, determines the DMA uplink virtual channel that needs to be scheduled, and performs virtual uplink virtual channels for each DMA according to the preset channel bandwidth value, priority, and effective bandwidth of the SRIO bus of the DMA uplink virtual channel. The received data of the channel to be transmitted is received, that is, according to the channel bandwidth value of the DMA upstream virtual channel, the number of bytes of received data that needs to be transmitted by the DMA upstream virtual channel in the receiving cycle is calculated, and the number of bytes of the received data that needs to be received by the DMA upstream virtual channel in the receiving cycle is calculated. The number of bytes and the effective bandwidth of the SRIO bus, calculate the scheduling time occupied by the DMA uplink virtual channel in the receiving cycle, and receive the received data to be transmitted according to the priority of the DMA uplink virtual channel and the corresponding calling time of the DMA uplink virtual channel. ,

When receiving the received data to be transmitted, the DMA uplink virtual control module checks whether the corresponding DMA uplink source buffer memory has received data to be transmitted according to the priority of the DMA uplink virtual channel. If there is received data to be transmitted, set the third The value of the upstream channel register is the first address of the received data to be transmitted in the DMA upstream source buffer memory,

Set the value of the second upstream channel register as the received data length to be transmitted in the DMA upstream source buffer memory;

Determine the first address of the DMA upstream destination buffer memory,

The DMA upstream virtual control module generates a DMA write request after obtaining the transmission length of the received data to be transmitted in the DMA upstream source buffer memory, the first address of the received data to be transmitted in the DMA upstream source buffer memory, and the first address of the DMA upstream destination buffer memory. AVALONE bus timing,

Step 204, the DMA uplink virtual control module sends the AVALONE bus timing of the DMA write request to the SRIO control module, and the SRIO control module packages the AVALONE bus timing of the DMA write request of the application into an SRIO NWRITE command in a serial data format through the SRIO bus Sent to the SRIO transceiver hardware module on the DSP side,

Step 205: After the SRIO transceiver hardware module on the DSP side receives the SRIO NWRITE command, it parses and recognizes the DMA write request of the SRIO, and parses out the transmission length and DMA of the received data to be transmitted in the DMA upstream source buffer memory of the DMA write request. After the first address of the received data to be transmitted in the upstream source buffer memory and the first address of the DMA upstream destination buffer memory, the received data to be transmitted is sequentially written to the DMA upstream destination buffer memory,

Step 206, after the DMA upstream virtual control module completes the transmission of the received data to be transmitted of the DMA upstream virtual channel, the value of the first upstream channel register is modified to represent that the DMA upstream destination buffer memory is a full state,

Step 207, the receiving task processes the received data of the DMA uplink destination buffer memory,

Step 208: The receive task in the DMA uplink virtual channel is processed to complete the received data of the DMA uplink destination buffer memory, and the value of the first uplink channel register is modified to indicate that the DMA uplink destination buffer memory is empty.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

First, the application-oriented multi-channel SRIO DMA transmission system proposed by the present invention can virtualize multiple transmission logical channels, with small coupling between applications and between channels and high independence, which is convenient for independent application and management. ;

Second, the multi-channel SRIO DMA transmission system and method adopted in the present invention can be flexibly configured according to application bandwidth, priority, real-time performance, etc., to meet various requirements of the application layer;

Third, the application-oriented SRIO DMA transmission method proposed by the present invention reduces the number of times of encapsulation, unpacking and data copying in data transmission, and improves the transmission efficiency of the system.

Description of drawings

Fig. 1 is a schematic diagram of SRIO DMA transmission hardware;

Fig. 2 is the overall structure schematic diagram of the present invention;

Fig. 3 is a schematic diagram of the composition of the DMA downlink virtual channel corresponding to the SV sending task;

Fig. 4 is a schematic diagram of the composition of the DMA upstream virtual channel corresponding to the SV receiving task;

5 is a schematic diagram of a DMA downlink multi-application scheduling process;

Fig. 6 is the AVALON-MM Read sequence diagram of SRIO control module (SRIO IP);

7 is a schematic diagram of a DMA uplink multi-application scheduling process;

FIG. 8 is a schematic diagram of the AVALON-MM WRITE timing of the SRIO control module (SRIO IP).

Detailed ways

In order to facilitate the understanding and implementation of the present invention by those of ordinary skill in the art, the present invention will be further described in detail below with reference to the embodiments. It should be understood that the embodiments described herein are only used to illustrate and explain the present invention, but not to limit the present invention.

An application-oriented multi-channel SRIO DMA transmission system includes a DSP subsystem and an FPGA subsystem.

The DSP subsystem includes: DSP, external memory DDR3 and SRIO transceiver hardware modules. The external memory DDR3 of the DSP subsystem is divided into multiple DMA downstream source buffer memories and multiple DMA upstream destination buffer memories corresponding to different applications.

The FPGA subsystem includes: SRIO control module (SRIO IP), DMA downlink virtual control module, DMA uplink virtual control module, external memory DDR3 and external interfaces. The external memory DDR3 of the FPGA subsystem is divided into multiple DMA downlinks corresponding to different applications. The destination buffer memory and multiple DMA upstream source buffer memories, the external interface corresponds to the application program one by one.

Applications include: SV sending tasks, analog sending tasks, FT3 sending tasks, GOOSE sending tasks, other sending tasks, SV receiving tasks, analog receiving tasks, FT3 receiving tasks, GOOSE receiving tasks, other receiving tasks, etc.;

External interfaces include SV sending module, analog sending module, FT3 sending module, GOOSE sending module, other sending modules, SV receiving module, analog receiving module, FT3 receiving module, GOOSE receiving module, other receiving modules, etc.;

Each application corresponds to a DMA virtual channel. The DMA virtual channel includes a DMA downlink virtual channel and a DMA uplink virtual channel. The DSP subsystem to the FPGA subsystem is the downlink, and the FPGA subsystem to the DSP subsystem is the uplink.

The DMA downlink virtual channel includes the DMA downlink source buffer memory, the DMA downlink virtual control module, and the DMA downlink destination buffer memory respectively corresponding to the application programs.

The DMA downlink virtual control module includes a first downlink channel register, a second downlink channel register and a third downlink channel register.

The first downlink channel register is used to store the storage state of the DMA downlink source buffer memory;

The second downlink channel register is used to store the transmission length of the transmission data to be transmitted in the DMA downlink source buffer memory;

The third downlink channel register is used to store the first address of the transmit data to be transmitted in the DMA downlink source buffer memory.

In this embodiment, the DMA downlink source buffer memory includes a first downlink source ping-pong memory dsram1_a and a second downlink source ping-pong memory dsram1_b.

The DMA downstream destination buffer memory includes a first downstream destination ping-pong memory fdram1_a and a second downstream destination ping-pong memory fdram1_b.

The 0th bit and the 1st bit of the first downlink channel register respectively correspond to the current state of the first downlink source ping-pong memory dsram1_a and the second downlink source ping-pong memory dsram1_b of the DMA downlink source buffer memory,

If the 0th bit of the first downlink channel register is 1, the downlink transmission of the first downlink source ping-pong memory dsram1_a is not completed; if the 0th bit of the first downlink channel register is 0, then the first downlink source ping-pong memory dsram1_a downlink transmission completed;

If the first bit of the first downlink channel register is 1, the downlink transmission of the second downlink source ping-pong memory dsram1_b is not completed; if the first bit of the first downlink channel register is 0, the second downlink source ping-pong memory dsram1_b downlink transmission completed;

The DMA upstream virtual channel includes the DMA upstream source buffer memory, the DMA upstream virtual control module, and the DMA upstream destination buffer memory respectively corresponding to the application program.

The DMA upstream virtual control module includes a first upstream channel register, a second upstream channel register and a third upstream channel register.

The first upstream channel register is used to store the storage state of the DMA upstream destination buffer memory ddram1;

The second upstream channel register is used to store the transmission length of the received data to be transmitted in the DMA upstream source buffer memory;

The third upstream channel register is used to store the first address of the received data to be transmitted in the DMA upstream source buffer memory.

In this embodiment, the DMA upstream source buffer memory fsram1 includes two pieces of a first upstream source ping-pong memory fsram1_a and a second upstream source ping-pong memory fsram1_b with the same size and the same function to form a ping-pong operation.

The DMA upstream destination buffer memory ddram1 has two same-sized first upstream destination ping-pong memory ddram1_a and second upstream destination ping-pong memory ddram1_b operating in ping-pong mode.

The 0th bit and the 1st bit of the first upstream channel register respectively correspond to the idle state of the first upstream destination ping-pong memory ddram1_a and the second upstream destination ping-pong memory ddram1_b,

If the 0th bit of the first upstream channel register is 1, then the first upstream destination ping-pong memory ddram1_a is not idle, and if the 0th bit of the first upstream channel register is 0, then the first upstream destination ping-pong memory ddram1_a is idle;

If the first bit of the first upstream channel register is 1, the second upstream destination ping-pong memory ddram1_b is not idle, and if the first bit of the first upstream channel register is 0, the second upstream destination ping-pong memory ddram1_b is idle.

The DSP is connected with each DMA downstream virtual control module and each DMA upstream virtual control module through a register bus.

The high-speed SRIO bus between DSP and FPGA adopts 4 physical channels, 2.5Gbps/channel, and the maximum theoretical communication bandwidth in both directions is 10Gbps. After 10B8B/8B10B conversion, the effective available bandwidth is 8Gbps, and a certain margin is further reserved to set the effective user bandwidth to 80 %, which is 6.4Gbps.

From the perspective of the whole application, applications can be divided into SV sending tasks, analog sending tasks, Goose sending tasks, FT3 sending tasks, other sending tasks, and the corresponding receiving tasks. The present invention binds these application programs to one by one. On the pre-defined DMA virtual channel, each application independently occupies the bandwidth and memory of the DMA virtual channel, and does not affect each other independently. The corresponding relationship between each application and the DMA virtual channel is: the first DMA downlink virtual channel corresponds to the SV transmission task, the second DMA downlink virtual channel corresponds to the analog transmission task, the third DMA downlink virtual channel corresponds to the FT3 transmission task, and the fourth DMA downlink virtual channel corresponds to the FT3 transmission task. Corresponding to Goose sending tasks; the first DMA upstream virtual channel corresponds to SV receiving tasks, the second DMA upstream virtual channel corresponds to analog receiving tasks, the third DMA upstream virtual channel corresponds to FT3 receiving tasks, and the fourth DMA upstream virtual channel corresponds to Goose receiving tasks; And reserve a spare channel N, which can be used as an extension for other sending and receiving tasks.

In addition, it also includes a register bus for the interaction between the DSP and the FPGA. The register bus is used to interact with the first downstream channel register, the second downstream channel register and the third downstream channel register in the DMA downstream virtual control module during DMA transmission between the DSP side and the FPGA side. The channel register, and the first upstream channel register, the second upstream channel register and the third upstream channel register in the DMA upstream virtual control module.

An application-oriented multi-channel SRIO DMA transmission method, in order to facilitate the implementation of the method by those skilled in the art, the following describes the operation processes of the first DMA downlink virtual channel and the first DMA uplink virtual channel as implementation examples.

Taking the SV sending task to transmit the SV sending data through the DMA downlink virtual channel as an example, an application-oriented multi-channel SRIO DMA transmission method includes the following steps:

Step 100, after the DSP is started, the SV sending task of the DSP acquires and initializes the DMA downlink source buffer memory dsram1,

In this embodiment, the DMA downlink source buffer memory dsram1 is composed of two first downlink source ping-pong memories dsram1_a and second downlink source ping-pong memories dsram2_b that are the same in size and operate in a ping-pong mode. Each of the first downlink source ping-pong memories and The maximum size of the second downstream source ping-pong memory is 32150 bytes.

Step 101, when the SV sending task has SV data to send, firstly, the DSP uses the register bus EMIF to query the first downlink channel register of the DMA downlink virtual control module, the first downlink channel register marks the state of the DMA downlink source buffer memory, and determines the DMA. The downstream source buffer memory is in the transfer completion state;

In this embodiment, the 0th bit and the 1st bit of the first downlink channel register respectively correspond to the current state of the first downlink source ping-pong memory dsram1_a and the second downlink source ping-pong memory dsram1_b of the DMA downlink source buffer memory. If The 0th bit of the first downlink channel register is 1, then the downlink transmission of the first downlink source ping-pong memory dsram1_a is not completed, and the first bit of the first downlink channel register is 1, then the second downlink source ping-pong memory dsram1_b downlink transmission If it is not completed, it needs to wait, otherwise, step 102 can be continued.

Step 102, the SV sending task fills the multiple SV sending data packets into the DMA downlink source buffer memory in turn, the first SV sending data packet starts from the 5th byte, and the subsequent SV sending data packets are arranged in the back in sequence, Until the DMA downlink source buffer memory can be filled, but the integrity of the last SV sending data packet must be guaranteed, that is, if the remaining byte data is not enough to place a pending SV sending data packet, the remaining space is free, As shown in Figure 3. After the SV transmit data packet to be transmitted fills the DMA downlink source buffer memory, modify the 32 bits of the first 4 bytes of the DMA downlink source buffer memory to the following definition:

Bits 7 to 0: The serial number tx_ch1_dma_stream of the SV sending data packet to be transmitted, incremented by 1 after each packet is completed, that is, 1 is added after the DMA downstream source buffer memory is filled with the SV sending data packet, as a follow-up verification on the receiving side. The basis for packet loss;

The 15th to 8th bits: the number of SV transmission packets currently to be transmitted tx_ch1_dma_pack_num;

Bits 31 to 16: tx_ch1_dma_byte_len of the total number of bytes of the SV transmit data packet currently to be transmitted.

In the above filling process, the first downlink source ping-pong memory dsram1_a and the second downlink source ping-pong memory dsram2_b of the DMA downlink source buffer memory are alternately filled.

Step 103: The SV transmission task writes the transmission length tx_ch1_dma_byte_len of the SV transmission data to be transmitted into the second downlink channel register of the DMA downlink virtual control module through the register bus EMIF, and writes the header of the SV transmission data to be transmitted in the DMA downlink source buffer memory. The address is written into the third downlink channel register of the DMA downlink virtual control module, and the first downlink channel register of the DMA downlink virtual control module is modified to indicate that the transmission is not completed.

Step 104, the DMA downlink virtual control module polls which DMA downlink virtual channels have SV transmission data to be scheduled according to the transmission cycle of every 250u, that is, through the first downlink channel register corresponding to each DMA downlink virtual channel to query whether SV transmission is required. The data needs to be scheduled for transmission, and the SV transmission data to be transmitted of each DMA downlink virtual channel is transmitted according to the preset channel bandwidth value, priority, and effective bandwidth of the SRIO bus of the DMA downlink virtual channel. That is, according to the channel bandwidth value of the DMA downstream virtual channel, calculate the number of bytes to be sent by the DMA downstream virtual channel in the sending cycle, and calculate the DMA downstream virtual channel according to the number of bytes to be sent by the DMA downstream virtual channel and the effective bandwidth of the SRIO bus in the sending cycle. The scheduling time occupied by the virtual channel in the sending cycle, according to the priority of the DMA downlink virtual channel, and sequentially according to the calling time corresponding to the DMA downlink virtual channel to transmit the SV transmission data to be transmitted;

Priority 1 is the highest, the highest priority scheduling, followed by the next. In this embodiment, the channel bandwidth value and priority of each DMA downlink virtual channel are set as follows:

The bandwidth of the first DMA downlink virtual channel is set to 1Gbps, which is divided into 250us transmission cycles, that is, the scheduling data volume is 1G*250* ^10-6 /8=31250 bytes, and the scheduling time is 31250*8/6400Mbps=39.0625us. The channel priority is 1;

The bandwidth of the second DMA downlink virtual channel is set to 261.12Mbps, which is divided into 250us transmission cycles, that is, the scheduling data volume is 261.12M*250*10 ^-6 /8=8160 bytes, and the scheduling time is 8160*8/6400Mbps=10.2us , the channel priority is 2.

The bandwidth of the third DMA downlink virtual channel is set to 163.84Mbps, which is divided into 250us transmission cycles, that is, the scheduling data volume is 163.84M*250*10 ^-6 /8=5120 bytes, and the scheduling time is 5120*8/6400Mbps=6.4us , the channel priority is 3;

The bandwidth of the fourth DMA downlink virtual channel is set to 28.8Mbps, which is divided into 250us transmission cycles, that is, the scheduling data volume is 28.8M*250*10 ^-6 /8=900 bytes, and the scheduling time is 900*8/6400Mbps=1.125us , the channel priority is 4;

The above 6400Mbps is the effective bandwidth of the SRIO bus.

The total scheduling occupied time is: 39.0625+10.2+6.4+1.125=56.7875us; the scheduling idle time is: 250us-56.7875us=193.2125us. The scheduling sequence diagram of each DMA downlink virtual channel is shown in Figure 5.

In the 250us cycle, first use 39.0625us to send the SV data packet of the first DMA downlink virtual channel with priority 1, and then use 10.2us to send the analog data packet of the second DMA downlink virtual channel with priority 2, and then use 6.4us send the GOOSE data packet of the third DMA downlink virtual channel with priority 3, and then use 1.125us to send the FT3 data packet of the fourth DMA downlink virtual channel with priority 4.

The DMA downlink virtual control module first reads the first downlink channel register corresponding to the DMA downlink virtual channel according to the channel priority defined above, and confirms whether the DMA downlink virtual channel has SV transmission data that needs to be transmitted. Send data, and then read the second downlink channel register and the third downlink channel register, that is, the transmission length of the SV transmission data to be transmitted in the DMA downlink source buffer memory and the first address of the transmission data to be transmitted in the DMA downlink source buffer memory. .

In this embodiment, if any one of the 0th bit and the 1st bit of the first downlink channel register is 1, it indicates that the DMA downlink virtual channel has data to be transmitted (the 0th bit is 1, the first downlink source is 1). The ping-pong memory dsram1_a has the SV transmission data to be transmitted, the first bit is 1, the second downlink source ping-pong memory dsram2_b has the SV transmission data to be transmitted), and then read the second downlink channel register and the third downlink channel register, that is, the DMA downlink source The transmission length of the SV transmission data to be transmitted in the buffer memory and the first address of the SV transmission data to be transmitted in the DMA downstream source buffer memory.

Further according to the transmission length of the SV transmission data to be transmitted in the DMA downlink source buffer memory and the first address of the SV transmission data to be transmitted in the DMA downlink source buffer memory, the AVALONE bus timing sequence of the DMA read request is generated, and the AVALONE bus is an Intel SRIO The DMA request bus provided by the control module (SRIO IP) is shown in Figure 6.

Step 105, the DMA downlink virtual control module sends the AVALONE bus timing of the DMA read request to the SRIO control module (SRIO IP) according to the method of step 104, and the SRIO control module (SRIO IP) packages the AVALONE bus timing of the DMA read request into SRIO The NREAD command is sent to the SRIO transceiver hardware module on the DSP side through the SRIO bus in serial data format;

Step 106: After the SRIO transceiver hardware module on the DSP side receives the SRIO NREAD command, it parses and identifies an SRIO DMA read request, and further parses out the SV transmit data to be transmitted in the DMA downlink source buffer memory of the DMA read request. The transmission length and the first address of the SV to be transmitted in the DMA downstream source buffer memory, and the transmission length of the SV to be transmitted in the DMA downstream source buffer memory on the DSP side and the transmission length of the DMA downstream source buffer memory to be transmitted. The first address of the SV sending data is the SV sending data to be transmitted according to the corresponding address read from the DMA downstream source buffer memory on the DSP side, and the corresponding RESP data packet is generated according to the RESP packet format of the SRIO protocol to respond to the SRIO on the FPGA side. Control module (SRIO IP);

Step 107 , after the SRIO control module (SRIO IP) on the FPGA side receives the RESP data packet of the SRIO transceiver hardware module on the DSP side, it parses it into an AVALONE bus read response sequence as a follow-up operation of the AVALONE bus in step 105 .

Step 108, after the DMA downlink virtual control module obtains the AVALONE bus read response sequence from the SRIO control module (SRIO IP), the corresponding SV transmission data to be transmitted is written in the DMA downlink destination buffer memory fdram1;

In this embodiment, the DMA downlink destination buffer memory fdram1 is composed of two first downlink destination ping-pong memory fdram1_a and second downlink destination ping-pong memory fdram1_b with the same capacity and ping-pong operation, and ping-pong reading and writing in turn.

Step 109, the SV sending module corresponding to the FPGA side reads the SV sending data to be transmitted by ping-pong operation by checking the non-empty identifier of the DMA downstream destination buffer memory fdram1 of the DMA downstream virtual channel and sends the data to be transmitted through the corresponding external interface on the FPGA side. The SV send data is sent out.

Other DMA downlink virtual channels can also transmit the data of their respective applications to the corresponding external interface on the FPGA side according to the above method.

Taking the SV receiving task to transmit the SV receiving data through the DMA uplink virtual channel as an example, an application-oriented multi-channel SRIO DMA transmission method includes the following steps:

Step 200, after the DSP is started, the SV receiving task of the DSP acquires and initializes the DMA uplink destination buffer memory ddram1,

In this embodiment, the DMA upstream destination buffer memory ddram1 is composed of two first upstream destination ping-pong memory ddram1_a and second upstream destination ping-pong memory ddram1_b which are the same in size and operate in ping-pong mode. The first upstream destination ping-pong memory ddram1_a and the second upstream destination ping-pong memory ddram1_a The maximum size of the uplink destination ping-pong memory ddram1_b is 32150 bytes.

Step 201, the SV receiving task clears the first upstream channel register of the DMA upstream virtual control module through the register bus EMIF, and the first upstream channel register reflects the storage state of the DMA upstream destination buffer memory ddram1,

In this embodiment, bits 0 and 1 of the first upstream channel register correspond to the current states of the first upstream destination ping-pong memory ddram1_a and the second upstream destination ping-pong memory ddram1_b of the DMA upstream virtual channel, respectively. When the SV receives a task After initializing or emptying the corresponding first upstream destination ping-pong memory ddram1_a and the second upstream destination ping-pong memory ddram1_b for the first time, the status register of the first upstream channel register is cleared.

Initialize the third upstream channel register as the first address of the DMA upstream destination buffer memory ddram1,

In this embodiment, the third upstream channel register stores the first address of the first upstream destination ping-pong memory ddram1_a or the second upstream destination ping-pong memory ddram1_b of the DMA upstream virtual channel. When the 0th bit of the first upstream channel register is 0, Assign the first address of the first upstream destination ping-pong memory ddram1_a to the third upstream channel register. When the first bit of the first upstream channel register is 0, assign the first address of the second upstream destination ping-pong memory ddram1_b to the third upstream channel register. .

After the configuration of the DMA upstream virtual channel is completed, it will wait for the FPGA subsystem to write data into the corresponding DMA upstream destination buffer memory ddram1, that is, the SV receiving task on the DSP side will poll the first upstream channel register corresponding to each DMA upstream virtual channel. The first upstream channel register reflects whether the DMA upstream destination buffer memory ddram1 is buffered with SV received data, if buffered with SV received data, then enter step 207, otherwise enter step 202;

In this embodiment, the 0th bit of the first upstream channel register is 1, which reflects that the SV received data is buffered in the ping-pong memory ddram1_a of the first upstream destination, and the first bit of the first upstream channel register is 1, which reflects the second upstream destination. SV received data is buffered in the ping-pong memory ddram1_b.

Step 202, the SV receiving module on the FPGA side receives the SV Ethernet data packet from the optical network port in real time, and marks the SV received data packet with a timestamp, and buffers it in the DMA upstream source buffer memory fsram1,

In this embodiment, the DMA upstream source buffer memory fsram1 includes two pieces of a first upstream source ping-pong memory fsram1_a and a second upstream source ping-pong memory fsram1_b with the same size and the same function to form a ping-pong operation.

The received Ethernet SV received data packets are filled into the DMA upstream source buffer memory fsram1 in turn. The first SV received data packet starts from the 5th byte, and the subsequent SV received data packets are arranged in sequence until the DMA can be The upstream source buffer memory fsram1 is full, but the integrity of the last SV received data packet must be guaranteed, that is, if the remaining byte data is not enough to place a to-be-placed SV received data packet, the remaining space is free, as shown in 4. Show. When the SV received data packets to be transmitted are filled, modify the 32 bits of the first 4 bytes of the DMA upstream source buffer memory fsram1 to the following definition:

The 7th to 0th bits: the serial number rx_ch1_dma_stream of the SV receiving data packet to be transmitted, which is incremented by 1 after each packet is completed, as the basis for the subsequent receiving side to verify whether the packet is lost;

The 15th to 8th bits: the number of SV received packets currently to be transmitted rx_ch1_dma_pack_num;

Bits 31 to 16: the total number of bytes rx_ch1_dma_byte_len of the SV received data packet to be transmitted currently.

And, after the SV receiving module grouping the data to be transmitted is completed, the number rx_ch1_dma_byte_len of the currently to-be-transmitted SV received data packets is updated to the second upstream channel register, and the second upstream channel register functions as a data length register to be transmitted.

In this embodiment, the first upstream source ping-pong memory fsram1_a and the second upstream source ping-pong memory fsram1_b in the DMA upstream source buffer memory fsram1 form a ping-pong operation to fill the Ethernet SV receiving data packets.

Step 203: The DMA upstream virtual control module polls which DMA upstream virtual channels need to be scheduled according to the receiving cycle of every 250us, that is, polls whether the DMA upstream source buffer memory fsram1 has SV receiving data to be transmitted, and according to the preset DMA upstream virtual channel The channel bandwidth value, priority, and effective bandwidth of the SRIO bus are used to receive the SV received data to be transmitted on each DMA upstream virtual channel, that is, according to the channel bandwidth value of the DMA upstream virtual channel, calculate the DMA upstream virtual channel needs to be transmitted in the receiving cycle. Calculate the number of bytes of data received by the SV in the receiving cycle, and calculate the scheduling time occupied by the DMA upstream virtual channel in the receiving cycle according to the number of bytes that the DMA upstream virtual channel needs to receive in the receiving cycle and the effective bandwidth of the SRIO bus. Priority, in turn receive the SV received data to be transmitted according to the calling time corresponding to the DMA uplink virtual channel.

Priority 1 is the highest, the highest priority scheduling, followed by the next. The bandwidth value and priority of each DMA uplink virtual channel are set as follows:

The bandwidth of the first DMA uplink virtual channel is set to 1Gbps, which is divided into a 250us receiving period, that is, the scheduling data volume is 1G*250*10 ^-6 /8=31250 bytes, and the scheduling time is 31250*8/6400Mbps=39.0625us, The channel priority is 1;

The bandwidth of the second DMA uplink virtual channel is set to 261.12Mbps, which is divided into 250us receiving cycles, that is, the scheduling data volume is 261.12M*250*10 ^-6 /8=8160 bytes, and the scheduling time is 8160*8/6400Mbps=10.2 us, the channel priority is 2;

The bandwidth of the third DMA uplink virtual channel is set to 163.84Mbps, which is divided into 250us receiving cycles, that is, the scheduling data volume is 163.84M*250*10 ^-6 /8=5120 bytes, and the scheduling time is 5120*8/6400Mbps=6.4 us, the channel priority is 3;

The bandwidth of the fourth DMA uplink virtual channel is set to 28.8Mbps, which is divided into 250us receiving cycles, that is, the scheduling data volume is 28.8M*250*10 ^-6 /8=900 bytes, and the scheduling time is 900*8/6400Mbps=1.125 us, the channel priority is 4;

The total scheduling occupied time is: 39.0625+10.2+6.4+1.125=56.7875us; the scheduling idle time is: 250us-56.7875us=193.2125us. The DMA uplink data scheduling sequence diagram is shown in Figure 7.

That is, in the 250us period, firstly use 39.0625us to send the SV data packet of the first DMA upstream virtual channel with priority 1, and then use 10.2us to send the simulation of the second DMA upstream virtual channel with priority 2; Then use 6.4us to send the GOOSE data packet of the third DMA upstream virtual channel with priority 3, and then use 1.125us to send the FT3 data packet of the fourth DMA upstream virtual channel with priority 4.

When receiving the SV receiving data to be transmitted, the DMA uplink virtual control module checks whether the corresponding DMA uplink source buffer memory fsram1 has the SV receiving data to be transmitted according to the priority of the DMA uplink virtual channel. If there is SV receiving data to be transmitted, and The value of the third upstream channel register is set as the first address of the SV receive data to be transmitted in the DMA upstream source buffer memory fsram1 of the SV receive data to be transmitted.

The value of setting the second upstream channel register is the SV receiving data length to be transmitted in the DMA upstream source buffer memory fsram;

Determines the first address of the DMA upstream destination buffer memory.

The DMA upstream virtual control module generates the DMA after obtaining the transmission length of the SV receiving data to be transmitted in the DMA upstream source buffer memory, the first address of the SV receiving data to be transmitted in the DMA upstream source buffer memory, and the first address of the DMA upstream destination buffer memory. The AVALONE bus timing of the write request, the AVALONE bus is the DMA request bus provided by the Intel SRIO control module (SRIO IP), as shown in Figure 8.

Step 204: The DMA uplink virtual control module sends the AVALONE bus timing of the DMA write request to the SRIO control module (SRIO IP), and the SRIO control module (SRIO IP) packages the AVALONE bus timing of the DMA write request of the SV receiving task into SRIO NWRITE The command is sent to the SRIO transceiver hardware module on the DSP side through the SRIO bus in serial data format.

Step 205: After the SRIO transceiver hardware module on the DSP side receives the SRIO NWRITE command, it parses and recognizes the DMA write request of the SRIO, and further parses out the SV receive data to be transmitted in the DMA upstream source buffer memory corresponding to the DMA write request. After the transmission length, the first address of the SV receiving data to be transmitted in the DMA upstream source buffer memory, and the first address of the DMA upstream destination buffer memory, and according to this, the SV receiving data to be transmitted is written to the DDR3 on the DSP side in sequence. DMA upstream destination buffer memory.

Step 206, after the DMA upstream virtual control module completes the transmission of the SV received data to be transmitted on the DMA upstream virtual channel, the first upstream channel register is set to 1, indicating that the corresponding DMA upstream destination buffer memory ddram1 is in a full state,

In this embodiment, if the SV received data to be transmitted is uploaded to the first uplink destination ping-pong memory ddram1-a, the 0th bit of the first uplink channel register is set to 1, and if the SV received data to be transmitted is uploaded to the second uplink destination ping-pong memory In the memory ddram1-b, the first bit of the first upstream channel register is set to 1.

Step 207, the first upstream channel register is set to 1 to indicate that the DMA upstream destination buffer memory ddram1 has the SV received data update, and the SV receive task processes the updated SV received data of the DMA upstream destination buffer memory ddram1,

In this embodiment, if the 0th bit of the first upstream channel register is 1, it indicates that there is DMA upstream data update in the first upstream destination ping-pong memory ddram1-a, and the first bit of the first upstream channel register is 1, indicating that the second upstream channel register is 1. There is data update in the upstream destination ping-pong memory ddram1-b; further, the SV receiving task reads out, processes, and applies the first upstream destination ping-pong memory ddram1-a or the second upstream destination ping-pong memory ddram1-b in the DMA upstream virtual channel data in .

Step 208, the SV reception task processing in the DMA upstream virtual channel completes the updated SV reception data of the DMA upstream destination buffer memory ddram1, and the corresponding first upstream channel register is cleared, that is, the SV reception task on the DSP side releases the DMA upstream virtual data. The control right of the DMA upstream destination buffer memory of the channel allows the DMA upstream virtual control module on the FPGA side to transmit data to the DMA upstream destination buffer memory again.

In this embodiment, that is to clear the 0th bit or the 1st bit in the corresponding first upstream channel register to zero,

For other DMA uplink virtual channels, the data of the application program of each interface on the FPGA side can also be transmitted to the corresponding application program on the DSP side according to the above method.

It should be pointed out that the specific embodiments described in the present invention are only for illustrating the spirit of the present invention. Those skilled in the art to which the present invention pertains can make various modifications or additions to the described specific embodiments or substitute in similar manners, but will not deviate from the spirit of the present invention or go beyond the definition of the appended claims range.

Claims (4)

1. An application-oriented multi-channel SRIO DMA transmission system, comprising a DSP subsystem and an FPGA subsystem, The DSP subsystem includes: DSP, SRIO transceiver hardware module, multiple DMA downstream source buffer memories and multiple DMA upstream destination buffer memories; The FPGA subsystem includes: SRIO control module, DMA downstream virtual control module, DMA upstream virtual control module, external interface, multiple DMA downstream destination buffer memories and multiple DMA upstream source buffer memories, Each application corresponds to a DMA virtual channel. The DMA virtual channel includes a DMA downlink virtual channel and a DMA uplink virtual channel. The DMA downlink virtual channel includes the DMA downlink source buffer memory, the DMA downlink virtual control module, and the DMA downlink destination buffer memory corresponding to the application program, respectively. The DMA downlink virtual control module includes a first downlink channel register for storing the state of the DMA downlink source buffer memory, a second downlink channel register for storing the transmission length of the transmit data to be transmitted in the DMA downlink source buffer memory, and a It is used to store the first address of the transmit data to be transmitted in the DMA downlink source buffer memory, The DMA upstream virtual channel includes the DMA upstream source buffer memory, the DMA upstream virtual control module, and the DMA upstream destination buffer memory corresponding to the application program, respectively. The DMA upstream virtual control module includes a first upstream channel register for storing the storage state of the DMA upstream destination buffer memory, a second upstream channel register for storing the transmission length of the received data to be transmitted in the DMA upstream source buffer memory, and a The third upstream channel register for storing the first address of the received data to be transmitted in the DMA upstream source buffer memory. 2. a kind of application-oriented multi-channel SRIO DMA transmission system according to claim 1, is characterized in that, The DMA downlink source buffer memory includes a first downlink source ping-pong memory and a second downlink source ping-pong memory, The 0th bit and the 1st bit of the first downlink channel register respectively correspond to the current state of the first downlink source ping-pong memory and the second downlink source ping-pong memory of the DMA downlink source buffer memory, The DMA upstream destination buffer memory includes a first upstream destination ping-pong memory and a second upstream destination ping-pong memory, Bit 0 and bit 1 of the first upstream channel register respectively correspond to the idle states of the first upstream destination ping-pong memory and the second upstream destination ping-pong memory. 3. an application-oriented multi-channel SRIO DMA transmission method, is characterized in that, comprises data sending step: In step 100, after the DSP is started, the sending task of the DSP acquires and initializes the DMA downlink source buffer memory, Step 101, when the sending task has to send data to send, the DSP uses the register bus to query the first downlink channel register of the DMA downlink virtual control module to determine that the DMA downlink source buffer memory is in a transmission completion state; Step 102: The sending task fills multiple sending data packets into the DMA downlink source buffer memory in turn. The first send data packet starts from the 5th byte until the DMA downlink source buffer memory is filled, and the last one is guaranteed. The integrity of the sending data packet, when the sending data packet to be transmitted fills the DMA downstream source buffer memory, modify the 32 bits of the first 4 bytes of the DMA downstream source buffer memory to the following definition: The 7th to 0th bits: the serial number of the sending data packet to be sent, plus 1 after each packet is completed; The 15th to 8th bits: the number of sending packets currently to be transmitted; Bits 31 to 16: The total number of bytes of the currently transmitted packet to be transmitted, Step 103: The transmission task writes the transmission length of the transmission data to be transmitted into the second downlink channel register of the DMA downlink virtual control module through the register bus, and writes the first address of the DMA downlink source buffer memory as the first address of the transmission data source to be transmitted. Enter the third downlink channel register of the DMA downlink virtual control module, and modify the first downlink channel register of the DMA downlink virtual control module to indicate that the transmission is not completed, Step 104: The DMA downlink virtual control module polls according to the sending cycle, determines that the DMA downlink virtual channel that has data needs to be scheduled has data, and matches the preset channel bandwidth value, priority, and effective bandwidth of the SRIO bus of the DMA downlink virtual channel. The send data to be transmitted of each DMA downlink virtual channel is sent, that is, according to the channel bandwidth value of the DMA downlink virtual channel, the number of bytes to be sent by the DMA downlink virtual channel in the transmission cycle is calculated, and the number of bytes to be sent by the DMA downlink virtual channel in the transmission cycle is calculated. According to the number of bytes and the effective bandwidth of the SRIO bus, calculate the scheduling time occupied by the DMA downlink virtual channel in the transmission cycle, and send the data to be sent according to the calling time corresponding to the DMA downlink virtual channel according to the priority of the DMA downlink virtual channel; When sending the data to be sent, the DMA downlink virtual control module first reads the first downlink channel register corresponding to the DMA downlink virtual channel to confirm whether the DMA downlink virtual channel has send data to be transmitted, and if there is send data to be transmitted , then read the transmission length of the transmission data to be transmitted recorded in the second downlink channel register, read the first address of the transmission data to be transmitted recorded in the third downlink channel register, according to the transmission length of the transmission data to be transmitted and The first address of the transmitted data to be transmitted, the AVALONE bus timing for generating the DMA read request, Step 105: The DMA downlink virtual control module sends the AVALONE bus timing of the DMA read request to the SRIO control module, and the SRIO control module packages the AVALONE bus timing of the DMA read request into an SRIO NREAD command and sends it to the DSP side through the SRIO bus in a serial data format SRIO transceiver hardware module; Step 106: After the SRIO transceiver hardware module on the DSP side receives the SRIO NREAD command, it parses out the corresponding transmission length of the transmission data to be transmitted and the first address of the transmission data to be transmitted, and uses the transmission data to be transmitted on the DSP side. The transmission length and the first address of the transmission data to be transmitted are based on reading the corresponding transmission data to be transmitted from the DMA downstream source buffer memory, and according to the RESP packet format of the SRIO protocol, the corresponding RESP data packet is generated and responded to the FPGA side. SRIO control module; Step 107: After the SRIO control module on the FPGA side receives the RESP data packet of the SRIO transceiver hardware module on the DSP side, it parses it into an AVALONE bus read response sequence; Step 108, after the DMA downlink virtual control module obtains the AVALONE bus read response sequence from the SRIO control module, the corresponding transmission data to be transmitted is written into the DMA downlink destination buffer memory; Step 109 , the sending module corresponding to the FPGA side reads the sending data to be transmitted by checking the non-empty identifier of the DMA downstream destination buffer memory of the DMA downstream virtual channel, and sends the sending data to be transmitted through the external interface corresponding to the FPGA side. 4. a kind of application-oriented multi-channel SRIO DMA transmission method according to claim 3, is characterized in that, also comprises data receiving step: Step 200, after the DSP is started, the receiving task of the DSP acquires and initializes the DMA uplink destination buffer memory, Step 201, the receiving task clears the first upstream channel register of the DMA upstream virtual control module through the register bus, Initialize the third upstream channel register as the first address of the DMA upstream destination buffer memory, The receiving task on the DSP side will poll each DMA upstream virtual channel corresponding to the first upstream channel register, if the first upstream channel register reflects that the DMA upstream destination buffer memory has received data buffered, then enter step 207, otherwise enter step 202; In step 202, the receiving module on the FPGA side receives the received data packets from the external interface in real time, and marks the received data packets with a timestamp, and buffers them in the DMA upstream source buffer memory, The received data packets are filled in the DMA upstream source buffer memory in turn. The first received data packet starts from the 5th byte, and the subsequent received data packets are arranged in sequence until the DMA upstream source buffer memory is full, and finally When a received data packet is complete, when the received data packet to be transmitted is filled, modify the 32 bits of the first 4 bytes of the DMA upstream source buffer memory to the following definition: The 7th to 0th bits: the serial number of the received data packet to be transmitted, plus 1 after each packet is completed; Bits 15 to 8: the number of received packets currently to be transmitted; Bits 31 to 16: the total number of bytes of the received data packet currently to be transmitted; The total number of bytes of the received data packets currently to be transmitted is updated to the second upstream channel register, Step 203, the DMA uplink virtual control module polls according to the receiving period, determines the DMA uplink virtual channel that needs to be scheduled, and performs virtual uplink virtual channels for each DMA according to the preset channel bandwidth value, priority, and effective bandwidth of the SRIO bus of the DMA uplink virtual channel. The received data of the channel to be transmitted is received, that is, according to the channel bandwidth value of the DMA upstream virtual channel, the number of bytes of received data that needs to be transmitted by the DMA upstream virtual channel in the receiving cycle is calculated, and the number of bytes of the received data that needs to be received by the DMA upstream virtual channel in the receiving cycle is calculated. The number of bytes and the effective bandwidth of the SRIO bus, calculate the scheduling time occupied by the DMA uplink virtual channel in the receiving cycle, and receive the received data to be transmitted according to the priority of the DMA uplink virtual channel and the corresponding calling time of the DMA uplink virtual channel. , When receiving the received data to be transmitted, the DMA uplink virtual control module checks whether the corresponding DMA uplink source buffer memory has received data to be transmitted according to the priority of the DMA uplink virtual channel. If there is received data to be transmitted, set the third The value of the upstream channel register is the first address of the received data to be transmitted in the DMA upstream source buffer memory, Set the value of the second upstream channel register as the received data length to be transmitted in the DMA upstream source buffer memory; Determine the first address of the DMA upstream destination buffer memory, The DMA upstream virtual control module generates a DMA write request after obtaining the transmission length of the received data to be transmitted in the DMA upstream source buffer memory, the first address of the received data to be transmitted in the DMA upstream source buffer memory, and the first address of the DMA upstream destination buffer memory. AVALONE bus timing, Step 204, the DMA uplink virtual control module sends the AVALONE bus timing of the DMA write request to the SRIO control module, and the SRIO control module packages the AVALONE bus timing of the DMA write request of the application into an SRIO NWRITE command in a serial data format through the SRIO bus Sent to the SRIO transceiver hardware module on the DSP side, Step 205: After the SRIO transceiver hardware module on the DSP side receives the SRIO NWRITE command, it parses and recognizes the DMA write request of the SRIO, and parses out the transmission length and DMA of the received data to be transmitted in the DMA upstream source buffer memory of the DMA write request. After the first address of the received data to be transmitted in the upstream source buffer memory and the first address of the DMA upstream destination buffer memory, the received data to be transmitted is sequentially written to the DMA upstream destination buffer memory, Step 206, after the DMA upstream virtual control module completes the transmission of the received data to be transmitted of the DMA upstream virtual channel, the value of the first upstream channel register is modified to represent that the DMA upstream destination buffer memory is a full state, Step 207, the receiving task processes the received data of the DMA uplink destination buffer memory, Step 208: The receive task in the DMA uplink virtual channel is processed to complete the received data of the DMA uplink destination buffer memory, and the value of the first uplink channel register is modified to indicate that the DMA uplink destination buffer memory is empty.

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