CN112777563B - Manufacturing method of airtight radio frequency MEMS device and airtight radio frequency MEMS device - Google Patents

Abstract

The invention discloses a manufacturing method of an airtight radio frequency MEMS device and the airtight radio frequency MEMS device, wherein the method comprises the following steps: processing a TGV filled through hole structure on the substrate wafer; deposit and grow a first SiO ₂ The dielectric layer is used for processing a transmission line and a first bonding pad; deposit and grow a second SiO ₂ The dielectric layer is processed into an interlayer interconnection through hole structure; deposit and grow third SiO ₂ The dielectric layer is used for processing the pull-down electrode and the second bonding pad; deposit and grow fourth SiO ₂ A dielectric layer, wherein contact bumps are processed; depositing a sacrificial layer, and processing a bonding ring, an anchor point and an upper polar plate; releasing the sacrificial layer; manufacturing a packaging cover plate; performing wafer level metal bonding; and carrying out wafer-level tin ball implantation and scribing, thereby obtaining the final airtight radio frequency MEMS device. The airtight radio frequency MEMS device manufactured by the method has reliable structure, good air tightness, good radio frequency performance, low parasitic effect, high production efficiency and low production cost, and is suitable for mass production.

Description

Manufacturing method of airtight radio frequency MEMS device and airtight radio frequency MEMS device

Technical field

The present invention relates to the technical field of airtight radio frequency MEMS devices, and in particular to a manufacturing method of an airtight radio frequency MEMS device and an airtight radio frequency MEMS device.

Background technique

Radio frequency microelectromechanical systems (RF MEMS) is one of the important application fields of MEMS technology and has also been a research hotspot in the field of MEMS since the 1990s. RF MEMS devices have excellent microwave performance such as high isolation, low loss, high linearity, low power consumption, and wide bandwidth. They are also small in size and easy to integrate. RF MEMS is used for signal processing in RF and microwave frequency circuits and is a technology that will have a significant impact on existing RF structures in radar and communications. However, because RF MEMS itself has a special structure that is incomparable to traditional ICs, it has stricter packaging and reliability requirements. RF MEMS devices with high-reliability packaging structures have become one of the key areas of current MEMS research.

In radio frequency MEMS devices, at least one kind of metal (gold or aluminum, etc.) is used as a thin structural material. Therefore, the packaging of radio frequency devices must be low-temperature packaging to avoid the impact of high temperature on the structure; radio frequency MEMS devices contain movable The cantilever beam or double-end fixed beam structure is easily affected by water vapor and some impurities in the external environment and causes adhesion failure. Therefore, the packaging of RF MEMS chips must use airtight sealing packaging. In the existing technology, packaging forms with bonding temperatures >300°C such as gold-silicon, silicon-silicon melting, and anode bonding are not suitable for RF MEMS devices. The organic adhesive bonding packaging process can realize low-temperature packaging and lateral interconnection of leads, but the airtightness of organic material packaging is much lower than that of metal packaging. Although the strength and airtightness of the packaging can be guaranteed when using metal packaging, In the existing technology, it is impossible to realize the lateral interconnection signal extraction of the leads, and the through-hole signal extraction process must be used. The through-holes located in the cavity also increase the probability of air leakage. At the same time, the introduction of the package cover and metal package sealing ring will bring additional parasitic effects to the RF signal transmission line, affecting the RF performance of the device.

In view of the above-mentioned defects, the designer actively conducts research and innovation in order to create a method for manufacturing radio frequency MEMS devices with an airtight packaging structure, so as to make it more industrially valuable.

Contents of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the present invention is to propose a method for manufacturing an air-tight radio frequency MEMS device. The air-tight radio frequency MEMS device produced has a reliable structure, good air tightness, good radio frequency performance, low parasitic effects, and high production efficiency. , low production cost and suitable for mass production.

The method for manufacturing an airtight radio frequency MEMS device according to the first embodiment of the present invention includes the following steps:

S1: Process the TGV filled through-hole structure on the substrate wafer to form the first intermediate product;

S2: Deposit and grow a first SiO ₂ dielectric layer on the upper surface of the first intermediate product, process a transmission line and a first pad in the first SiO ₂ dielectric layer, and process the transmission line and the first pad. The first pads are electrically connected to the corresponding TGV filled through-hole structures, thereby forming a second intermediate product;

S3: Deposit and grow a second SiO ₂ dielectric layer on the upper surface of the second intermediate product, and process an interlayer interconnection via structure in the second SiO ₂ dielectric layer. The interlayer interconnection via hole a structure electrically connected to the first pad to form a third intermediate product piece;

S4: Deposit and grow a third SiO ₂ dielectric layer on the upper surface of the third intermediate product, and process a pull-down electrode and a second bonding pad in the third SiO ₂ dielectric layer. The second bonding pad Electrically connected to the interlayer interconnection via structure to form a fourth intermediate product piece;

S5: Deposit and grow a fourth SiO ₂ dielectric layer on the upper surface of the fourth intermediate product. Between the fourth SiO ₂ dielectric layer, the third SiO ₂ dielectric layer and the second SiO ₂ dielectric layer Contact bumps are processed in the layer, the bottoms of the contact bumps are electrically connected to one of the transmission lines, thereby forming a fifth intermediate product piece;

S6: Deposit a sacrificial layer on the upper surface of the fifth intermediate product, process a bonding ring in the sacrificial layer, and fix the bottom of the bonding ring to the fourth SiO ₂ dielectric layer. An anchor point is processed in the sacrificial layer, the fourth SiO ₂ dielectric layer, the third SiO ₂ dielectric layer and the second SiO ₂ dielectric layer, and the bottom of the anchor point is electrically connected to the other transmission line. connection, an upper electrode plate is processed on the upper surface of the sacrificial layer, and the upper electrode plate is electrically connected to the top of the anchor point. The anchor point, the upper electrode plate and the contact bump are all located within said bonding ring, thereby forming a sixth intermediate product piece;

S7: Release the sacrificial layer in the sixth intermediate product piece, thereby forming a seventh intermediate product piece;

S8: Make a packaging cover plate. The bottom surface of the packaging cover plate has a packaging inner cavity. The upper side of the packaging cover plate and the lower side of the packaging cover plate except for the packaging inner cavity have a masking layer. A bonding sealing ring is provided on the shielding layer on the lower side of the packaging cover plate, and the packaging inner cavity is located in the bonding sealing ring;

S9: Align the bonding ring of the seventh intermediate product part with the bonding sealing ring of the packaging cover plate, and perform wafer-level metal bonding to form an eighth intermediate product part;

S10: Perform wafer-level solder ball implantation on the lower surface of the substrate wafer of the eighth intermediate product, and scribe the eighth intermediate product to obtain the final air tightness RF MEMS devices.

The method for manufacturing an airtight radio frequency MEMS device according to the first embodiment of the present invention has the following advantages: First, the transmission line (such as a coplanar waveguide transmission line) is led out of the package cavity in combination with the rewiring process to achieve TGV filling. The external real through-hole structure greatly improves the airtightness of the airtight RF MEMS device packaging, which is conducive to improving the reliability of the airtight RF MEMS device; secondly, the introduction of the bonding sealing ring on the packaging cover plate, It can ensure the airtightness of the package, but at the same time it will bring additional parasitic effects to the RF signal transmission line, affecting the radio frequency performance of the device; by setting the second SiO ₂ dielectric layer, the third SiO ₂ dielectric layer, and the fourth SiO ₂ dielectric layer It can not only thicken the thickness of the dielectric layer between the transmission line and the bonding ring, but also reduce the distance between the pull-down electrode and the upper plate (i.e., the cantilever beam), and reduce the pull-down voltage without affecting the pull-down voltage. Alleviating the problem of parasitic effects caused by the metal packaging sealing ring; thirdly, aligning the bonding ring of the fifth intermediate product with the bonding sealing ring of the packaging cover for wafer-level metal bonding can provide good air tightness While completing the air-tight packaging, it avoids the impact of high-temperature packaging on the structure of air-tight RF MEMS devices; fourth, the packaging method is wafer-level packaging, which is suitable for mass production of air-tight RF MEMS devices. Improve production efficiency and reduce production costs.

According to an embodiment of the first aspect of the present invention, the upper surface of the first intermediate product piece, the upper surface of the second intermediate product piece, the upper surface of the third intermediate product piece and the fourth intermediate product The upper surface of the parts is polished and flat.

According to an embodiment of the first aspect of the present invention, in step S1, the specific processing steps of the TGV filled through hole structure are: after making a through hole on the substrate wafer, Plate a metal conductive layer on the inner peripheral wall, and then fill the through hole with an insulating medium that has been plated with the metal conductive layer, thereby processing the TGV filled through hole structure, or completely filling the through hole. solid conductive metal, thereby processing the TGV filled through hole structure.

According to an embodiment of the first aspect of the present invention, in step S2, processing a transmission line and a first pad in the first SiO ₂ dielectric layer specifically includes the following steps: The SiO ₂ dielectric layer is first processed to expose the transmission line pattern cavity and the first pad pattern cavity of the substrate wafer (photolithography and etching); then, the transmission line pattern cavity and the first pad pattern cavity are processed A first metal adhesion layer and a first metal circuit layer are sequentially deposited and grown in the pattern cavity, and the first metal adhesion layer is used to adhere the first metal circuit layer.

According to an embodiment of the first aspect of the present invention, in step S3, processing an interlayer interconnection via structure in the second SiO ₂ dielectric layer specifically includes the following steps: _2. An interlayer interconnection via pattern cavity is first processed in the dielectric layer, and then a second metal adhesion layer and a second metal circuit layer are sequentially deposited and grown in the interlayer interconnection via pattern cavity. The second metal The adhesive layer is used to adhere the second metal circuit layer.

According to an embodiment of the first aspect of the present invention, in step S4, processing a pull-down electrode and a second pad in the third SiO ₂ dielectric layer specifically includes the following steps: A pull-down electrode pattern cavity and a second pad pattern cavity are first processed in the SiO ₂ dielectric layer, and then a third metal adhesion layer and a third metal adhesion layer are deposited and grown in the pull-down electrode pattern cavity and the second pad pattern cavity respectively. The third metal circuit layer.

According to an embodiment of the first aspect of the present invention, in step S5, the fourth SiO ₂ dielectric layer, the third SiO ₂ dielectric layer and the second SiO ₂ dielectric layer are processed first Producing contact bumps specifically includes the following steps: processing contact bump pattern cavities in the fourth SiO ₂ dielectric layer, the third SiO ₂ dielectric layer and the second SiO ₂ dielectric layer, and then forming A fourth metal adhesion layer and a metal bump layer are sequentially deposited and grown at the contact bump pattern cavity, and the metal bump layer is processed to form the contact bump.

According to an embodiment of the first aspect of the present invention, in step S6, processing a bonding ring in the sacrificial layer specifically includes the following steps: first processing a bonding ring pattern in the sacrificial layer cavity, and then fabricate the bonding ring in the bonding ring pattern cavity.

According to an embodiment of the first aspect of the present invention, in step S6, the sacrificial layer, the fourth SiO ₂ dielectric layer, the third SiO ₂ dielectric layer and the second SiO ₂ Processing anchor points in the dielectric layer specifically includes the following steps: first processing anchor points in the sacrificial layer, the fourth SiO ₂ dielectric layer, the third SiO ₂ dielectric layer and the second SiO ₂ dielectric layer point pattern cavity, and then create anchor points in the anchor point pattern cavity.

According to an embodiment of the first aspect of the present invention, in step S6, the sacrificial layer is an organic sacrificial layer or an inorganic sacrificial layer.

According to an embodiment of the first aspect of the present invention, in step S7, the sacrificial layer is released using dry release or wet release.

According to an embodiment of the first aspect of the present invention, in the step S8, the manufacturing method of the packaging cover is: simultaneously depositing the masking layer on the upper and lower sides of the high-resistance silicon wafer, patterning The masking layer on the lower side is etched into the packaging inner cavity in the masking layer on the lower side and the high-resistance silicon wafer.

According to an embodiment of the first aspect of the present invention, the bonding sealing ring is made by separately depositing a fifth metal adhesion layer and a metal bonding layer, and the fifth metal adhesion layer is used to bind the The metal bonding layer is fixed.

The second aspect of the present invention also provides an airtight radio frequency MEMS device.

An airtight radio frequency MEMS device according to an embodiment of the second aspect of the present invention. The airtight radio frequency MEMS device is manufactured by using the manufacturing method of an airtight radio frequency MEMS device according to any embodiment of the first aspect of the present invention. .

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of the drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

Figure 1 is a first process schematic diagram of the manufacturing method of the airtight radio frequency MEMS device of the present invention.

Figure 2 is a second process schematic diagram of the manufacturing method of the airtight radio frequency MEMS device of the present invention.

Figure 3 is a third process schematic diagram of the manufacturing method of the airtight radio frequency MEMS device of the present invention.

Figure 4 is a schematic diagram of the fourth process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.

Figure 5 is a schematic diagram of the fifth process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.

Figure 6 is a schematic diagram of the sixth process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.

Figure 7 is a schematic diagram of the seventh process of the manufacturing method of the airtight radio frequency MEMS device of the present invention.

Figure 8 is a schematic cross-sectional structural diagram of the airtight radio frequency MEMS device of the present invention.

Reference signs:

Hermetic RF MEMS Device 1000

Substrate wafer 1TGV filled through hole structure 2

First SiO ₂ dielectric layer 3 Transmission line 4 First pad 5

Second SiO ₂ dielectric layer 6 interlayer interconnection via structure 7

Third SiO ₂ dielectric layer 8 pull-down electrode 9 second pad 10

The fourth SiO ₂ dielectric layer 11 contacts the bump 12

Sacrificial layer 13 bonding ring 14 anchor point 15 upper plate 16

Package cover 17

High resistance silicon wafer 1701 package cavity 1702 masking layer 1703 bonding sealing ring 1704

Tin ball 18

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and cannot be understood as limiting the present invention.

The manufacturing method of the airtight radio frequency MEMS device and the airtight radio frequency MEMS device 1000 of the present invention will be described below with reference to FIGS. 1 to 8 .

As shown in Figures 1 to 8, the method for manufacturing an airtight radio frequency MEMS device 1000 according to the first embodiment of the present invention includes the following steps:

S1: As shown in Figure 1, process the TGV filled through hole structure 2 on the substrate wafer 1 to form the first intermediate product;

S2: As shown in Figure 2, deposit and grow the first SiO ₂ dielectric layer 3 on the upper surface of the first intermediate product, and process the transmission line 4 and the first pad 5 in the first SiO ₂ dielectric layer 3. The transmission line 4 and the first pad 5 are electrically connected to the corresponding TGV filled through hole structure 2 respectively, thereby forming a second intermediate product;

S3: As shown in Figure 3, a second SiO ₂ dielectric layer 6 is deposited and grown on the upper surface of the second intermediate product, and an interlayer interconnection via structure 7 is processed in the second SiO ₂ dielectric layer 6. The interconnection via structure 7 is electrically connected to the first pad 5, thereby forming a third intermediate product;

S4: As shown in Figure 3, a third SiO ₂ dielectric layer 8 is deposited and grown on the upper surface of the third intermediate product, and a pull-down electrode 9 and a second pad 10 are processed in the third SiO ₂ dielectric layer 8. The second pad 10 is electrically connected to the interlayer interconnection via structure 7, thereby forming a fourth intermediate product;

S5: As shown in Figures 3 and 4, a fourth SiO ₂ dielectric layer 11 is deposited and grown on the upper surface of the fourth intermediate product. Between the fourth SiO ₂ dielectric layer 11, the third SiO ₂ dielectric layer 8 and the Contact bumps 12 are processed in the SiO ₂ dielectric layer 6, and the bottom of the contact bumps 12 is electrically connected to a transmission line 4, thereby forming a fifth intermediate product;

S6: As shown in Figure 5, a sacrificial layer 13 is deposited on the upper surface of the fifth intermediate product, a bonding ring 14 is processed in the sacrificial layer 13, and the bottom of the bonding ring 14 is fixed to the fourth SiO ₂ dielectric layer 11 , an anchor point 15 is processed in the sacrificial layer 13, the fourth SiO ₂ dielectric layer 11, the third SiO ₂ dielectric layer 8 and the second SiO ₂ dielectric layer 6, and the bottom of the anchor point 15 is electrically connected to another transmission line 4, An upper plate 16 is processed on the upper surface of the sacrificial layer 13. The upper plate 16 is electrically connected to the top of the anchor point 15. The anchor point 15, the upper plate 16 and the contact bump 12 are all located in the bonding ring 14. Thus forming the sixth intermediate product piece;

S7: As shown in Figure 6, release the sacrificial layer 13 in the sixth intermediate product piece, thereby forming the seventh intermediate product piece;

S8: As shown in Figure 7, make the packaging cover 17. The bottom surface of the packaging cover 17 has a packaging cavity 1702. Both the upper side of the packaging cover 17 and the lower side of the packaging cover 17 except for the packaging cavity 1702 have Masking layer 1703, a bonding sealing ring 1704 is provided on the masking layer 1703 on the lower side of the packaging cover 17, and the packaging inner cavity 1702 is located in the bonding sealing ring 1704;

S9: As shown in Figure 8, align the bonding ring 14 of the seventh intermediate product part with the bonding sealing ring 1704 of the packaging cover 17, and perform wafer-level metal bonding to form the eighth intermediate product part;

S10: As shown in Figure 8, wafer-level solder balls 18 are implanted on the lower surface of the substrate wafer 1 of the eighth intermediate product, and the eighth intermediate product is diced to obtain the final airtightness. RF MEMS devices.

The manufacturing method of an airtight radio frequency MEMS device according to the first embodiment of the present invention has the following advantages: first, the transmission line 4 (such as the coplanar waveguide transmission line 4) is led out of the package inner cavity 1702 in combination with the rewiring process; Realizing the external placement of the TGV filled through-hole structure 2 greatly improves the airtightness of the airtight radio frequency MEMS device 1000, which is beneficial to improving the reliability of the airtight radio frequency MEMS device; secondly, the key on the packaging cover 17 The introduction of the sealing ring 1704 can ensure the airtightness of the package, but at the same time it will bring additional parasitic effects to the RF signal transmission line 4, affecting the radio frequency performance of the device; by setting the second SiO ₂ dielectric layer and the third SiO ₂ dielectric layer layer, the fourth SiO ₂ dielectric layer can not only thicken the thickness of the dielectric layer between the transmission line 4 and the bonding ring 14, but also reduce the distance between the pull-down electrode 9 and the upper plate 16 (i.e., the cantilever beam), reducing the The pull-down voltage alleviates the parasitic effect problem brought by the metal package sealing ring without affecting the pull-down voltage; thirdly, the bonding ring 14 of the fifth intermediate product part and the bonding sealing ring 1704 of the packaging cover 17 Aligned wafer-level metal bonding can provide good airtightness. While completing the airtight packaging, it avoids the impact of high-temperature packaging on the structure of the airtight RF MEMS device 1000; fourth, the packaging method is Wafer-level packaging is suitable for mass production of 1000 air-tight RF MEMS devices, improving production efficiency and reducing production costs.

According to an embodiment of the first aspect of the present invention, the upper surface of the first intermediate product piece, the upper surface of the second intermediate product piece, the upper surface of the third intermediate product piece and the upper surface of the fourth intermediate product piece are all polished and smooth. noodle. In this way, the stress of the airtight radio frequency MEMS device 1000 can be reduced, the flatness of the cantilever beam (ie, the upper plate 16 ) of the airtight radio frequency MEMS device 1000 can be increased, and the interlayer interconnection of the airtight radio frequency MEMS device 1000 can be improved. Electrical contact properties.

Preferably, the upper surface of the first intermediate product piece, the upper surface of the second intermediate product piece, the upper surface of the third intermediate product piece, and the upper surface of the fourth intermediate product piece are all polished flat surfaces, which can be processed by CMP (Chemical Processing Method) respectively. Mechanical polishing) polishing process.

According to an embodiment of the first aspect of the present invention, in step S1, the specific processing steps of the TGV filled through-hole structure 2 are: after making a through-hole on the substrate wafer 1, plating on the inner peripheral wall of the through-hole A metal conductive layer, such as a copper layer, is then filled with an insulating medium in the through hole that has been plated with the metal conductive layer, thereby processing a TGV filled through hole structure 2, or the through hole is completely filled with a conductive metal, such as copper, thereby Process the TGV filled through hole structure 2. Thus, the electrical conductivity of the TGV filled via structure 2 is achieved.

Preferably, the substrate wafer 1 can be a glass wafer.

According to an embodiment of the first aspect of the present invention, in step S2, processing the transmission line _{4 and the first pad 5 in the first SiO 2 dielectric} layer 3 specifically includes the following steps: First, a transmission line pattern cavity and a first pad pattern cavity exposing the substrate wafer 1 are processed; and then the first metal adhesion layer and the first metal adhesion layer and the first pad pattern cavity are sequentially deposited and grown in the transmission line pattern cavity and the first pad pattern cavity. A metal circuit layer, the first metal adhesion layer is used to adhere the first metal circuit layer. Therefore, the processing is convenient, and the processed transmission line 4 and first pad 5 are of high quality and have no risk of falling off.

It should be noted that the transmission line pattern cavity and the first pad pattern cavity can be obtained by photolithography and etching the first SiO ₂ dielectric layer 3 and exposing the substrate wafer 1. This processing method has good selectivity and repeatability. Good, high production efficiency and low cost.

According to an embodiment of the first aspect of the present invention, in step S3, the interlayer interconnection via structure 7 is processed _in the second SiO ₂ dielectric layer 6, which specifically includes the following steps: first, The interlayer interconnection via hole pattern cavity is processed, and then a second metal adhesion layer and a second metal circuit layer are sequentially deposited and grown in the interlayer interconnection via hole pattern cavity. The second metal adhesion layer is used to adhere the second metal circuit layer. Metal circuit layer. Therefore, the processing is convenient, and the processed interlayer interconnection via structure 7 is of good quality.

It should be noted that the interlayer interconnection via hole pattern cavity can be obtained by photolithography and etching the second SiO ₂ dielectric layer 6. This processing method has good selectivity, good repeatability, high production efficiency and low cost.

According to an embodiment of the first aspect of the present invention, in step S4, the pull-down electrode 9 and the second pad 10 _{are processed in the third SiO 2 dielectric} layer 8, which specifically includes the following steps: The pull-down electrode pattern cavity and the second pad pattern cavity are first processed, and then the third metal adhesion layer and the third metal circuit layer are deposited and grown in the pull-down electrode pattern cavity and the second pad pattern cavity respectively. Therefore, the processing is easy, and the processed pull-down electrode 9 and the second bonding pad 10 are of high quality.

It should be noted that the pull-down electrode pattern cavity and the second pad pattern cavity can be obtained by photolithography and etching the third SiO ₂ dielectric layer 8. This processing method has good selectivity, good repeatability, high production efficiency and low cost. .

According to an embodiment of the first aspect of the present invention, in step S5, contact bumps 12 are first processed in the fourth SiO ₂ dielectric layer 11, the third SiO ₂ dielectric layer 8 and the second SiO ₂ dielectric layer 6. Specifically, The method includes the following steps: processing contact bump pattern cavities in the fourth SiO ₂ dielectric layer 11, the third SiO ₂ dielectric layer 8 and the second SiO ₂ dielectric layer 6, and then sequentially depositing and growing the contact bump pattern cavities. The fourth metal adhesion layer and metal bump layer are processed to form contact bumps 12 . Thus, the contact bumps 12 can be processed, and the contact bumps 12 are of good quality.

It should be noted that the contact bump pattern cavity can be obtained by photolithography and etching the fourth SiO ₂ dielectric layer 11, the third SiO ₂ dielectric layer 8 and the second SiO ₂ dielectric layer 6. This processing method has good selectivity. , good repeatability, high production efficiency and low cost.

According to an embodiment of the first aspect of the present invention, in step S6, the bonding ring 14 is processed in the sacrificial layer 13, which specifically includes the following steps: first processing the bonding ring pattern cavity in the sacrificial layer, and then processing the bonding ring 14 in the sacrificial layer 13. The bonding ring 14 is produced in the ring pattern cavity. Thus, the bonding ring 14 can be easily processed, and the bonding ring 14 is of good quality.

It should be noted that the bonding ring pattern cavity can be obtained by photolithography and etching the sacrificial layer 13. This processing method has good selectivity, good repeatability, high production efficiency and low cost.

According to an embodiment of the first aspect of the present invention, in step S6, anchor points 15 are processed in the sacrificial layer 13, the fourth SiO ₂ dielectric layer 11, the third SiO ₂ dielectric layer 8 and the second SiO ₂ dielectric layer 6 , specifically including the following steps: first process an anchor point pattern cavity in the sacrificial layer 13, the fourth SiO ₂ dielectric layer 11, the third SiO ₂ dielectric layer 8 and the second SiO ₂ dielectric layer 6, and then process the anchor point pattern cavity in the anchor point pattern cavity. Create anchor point 15. Therefore, the anchor point 15 can be easily processed, and the anchor point 15 is of high quality.

It should be noted that the anchor pattern cavity can be obtained by photolithography and etching the sacrificial layer 13, the fourth SiO ₂ dielectric layer 11, the third SiO ₂ dielectric layer 8 and the second SiO ₂ dielectric layer 6. This processing method Good selectivity, good repeatability, high production efficiency and low cost.

According to an embodiment of the first aspect of the present invention, in step S6, the sacrificial layer 13 is an organic sacrificial layer 13 or an inorganic sacrificial layer 13. For example, the organic layer can be a polyimide sacrificial layer 13, and the inorganic sacrificial layer 13 can be a silicon sacrificial layer 13.

According to an embodiment of the first aspect of the present invention, in step S7, the sacrificial layer 13 is released using dry release or wet release. In particular, when the sacrificial layer 13 is a polyimide sacrificial layer 13, a dry method can be used to release the sacrificial layer 13. When the sacrificial layer 13 is a silicon sacrificial layer 13, a wet method can be used to release the sacrificial layer 13, which can be easily and thoroughly removed. Sacrificial layer 13.

According to an embodiment of the first aspect of the present invention, in step S8, the manufacturing method of the package cover 17 is: simultaneously depositing the masking layer 1703 on the upper and lower sides of the high-resistance silicon wafer 1701, and patterning the lower side. Masking layer 1703, and etching a package cavity 1702 in the lower masking layer 1703 and the high-resistance silicon wafer 1701. Therefore, processing is easy, and processing the packaging cover 17 can reduce the leakage of radio frequency signals.

According to a further embodiment of the first aspect of the invention, the masking layer 1703 is a Si ₃ N ₄ masking layer 1703 . As a result, the etching selectivity is high and the package inner cavity 1702 can be easily processed.

According to a further embodiment of the first aspect of the present invention, the bonding sealing ring 1704 is made by depositing a fifth metal adhesion layer and a metal bonding layer respectively, and the fifth metal adhesion layer is used to fix the metal bonding layer. . Therefore, processing is easy and the quality of the bonding ring 14 can be ensured.

According to a further embodiment of the first aspect of the invention, the sealing bonding ring 14 is made of one, two or more combinations of Cu/Sn, Au/Sn, Au/Sn/Cu, Ge/Al and Au/Au. can be selected according to actual needs.

The second aspect of the present invention also provides an airtight radio frequency MEMS device 1000.

According to the airtight radio frequency MEMS device 1000 according to the second embodiment of the present invention, the airtight radio frequency MEMS device 1000 is manufactured by using the manufacturing method of the airtight radio frequency MEMS device 1000 according to any embodiment of the first aspect of the present invention.

Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art will appreciate that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and purposes of the invention. The scope of the invention is defined by the claims and their equivalents.

Claims (14)

1. The manufacturing method of the airtight radio frequency MEMS device is characterized by comprising the following steps of:

s1: processing a TGV filled through hole structure on a substrate wafer so as to form a first intermediate product piece;

s2: depositing and growing a first SiO on the upper surface of the first intermediate product piece ₂ A dielectric layer on the first SiO ₂ Processing a transmission line and a first bonding pad in the dielectric layer, wherein the transmission line and the first bonding pad are respectively and electrically connected with the corresponding TGV filling through hole structure, so as to form a second intermediate product piece;

s3: depositing and growing a second SiO on the upper surface of the second intermediate product piece ₂ A dielectric layer on the second SiO ₂ Processing an interlayer interconnection through hole structure in the dielectric layer, wherein the interlayer interconnection through hole structure is electrically connected with the first bonding pad, so that a third intermediate product piece is formed;

s4: depositing and growing a third SiO on the upper surface of the third intermediate product piece ₂ A dielectric layer on the third SiO ₂ A pull-down electrode and a second bonding pad are processed in the dielectric layer, and the second bonding pad is electrically connected with the interlayer interconnection through hole structure, so that a fourth intermediate product piece is formed;

s5: depositing and growing a fourth SiO on the upper surface of the fourth intermediate product piece ₂ A dielectric layer on the fourth SiO ₂ A dielectric layer, the third SiO ₂ Dielectric layer and the second SiO ₂ Processing contact protruding points in the dielectric layer, wherein the bottoms of the contact protruding points are electrically connected with one transmission line, so that a fifth intermediate product piece is formed;

s6: depositing a sacrificial layer on the upper surface of the fifth intermediate product piece, and processing a bonding ring on the sacrificial layer, wherein the bottom of the bonding ring is connected with the fourth SiO ₂ A dielectric layer fixed on the sacrificial layer and the fourth SiO ₂ A dielectric layer, the third SiO ₂ Dielectric layer and the second SiO ₂ An anchor point is processed in the dielectric layer, the bottom of the anchor point is electrically connected with another transmission line, an upper polar plate is processed on the upper surface of the sacrificial layer, the upper polar plate is electrically connected with the top of the anchor point, and the anchor point, the upper polar plate and the contact salient point are all positioned in the bonding ring, so that a sixth intermediate product piece is formed;

s7: releasing the sacrificial layer in the sixth intermediate product piece, thereby forming a seventh intermediate product piece;

s8: manufacturing a packaging cover plate, wherein the bottom surface of the packaging cover plate is provided with a packaging inner cavity, masking layers are arranged on the upper side of the packaging cover plate and the part, except for the packaging inner cavity, of the lower side of the packaging cover plate, a bonding sealing ring is arranged on the masking layer on the lower side of the packaging cover plate, and the packaging inner cavity is positioned in the bonding sealing ring;

s9: aligning the bonding ring of the seventh intermediate product piece with the bonding sealing ring of the packaging cover plate, and performing wafer-level metal bonding so as to form an eighth intermediate product piece;

s10: and carrying out wafer-level tin ball implantation on the lower surface of the substrate wafer of the eighth intermediate product piece, and scribing the eighth intermediate product piece, so as to obtain the final airtight radio frequency MEMS device.

2. The method of claim 1, wherein the upper surface of the first intermediate product, the upper surface of the second intermediate product, the upper surface of the third intermediate product, and the upper surface of the fourth intermediate product are polished flat surfaces.

3. The method for fabricating a hermetic radio frequency MEMS device according to claim 1, wherein in the step S1, the specific processing steps of the TGV filling via structure are as follows: and after a through hole is manufactured on the substrate wafer, plating a metal conducting layer on the inner peripheral wall of the through hole, and filling an insulating medium in the through hole plated with the metal conducting layer, so that the TGV filled through hole structure is processed, or all conductive metals are filled in the through hole, so that the TGV filled through hole structure is processed.

4. The method of fabricating a hermetic radio frequency MEMS device according to claim 1, wherein in step S2, the first SiO is a silicon oxide film ₂ The method for processing the transmission line and the first bonding pad in the dielectric layer specifically comprises the following steps: at the first SiO ₂ Firstly processing a transmission line pattern cavity and a first bonding pad pattern cavity which are exposed out of the substrate wafer in the dielectric layer; and respectively depositing and growing a first metal adhesion layer and a first metal circuit layer in the transmission line pattern cavity and the first bonding pad pattern cavity in sequence, wherein the first metal adhesion layer is used for cementing the first metal circuit layer.

5. The method of fabricating a hermetic radio frequency MEMS device according to claim 1, wherein in step S3, the second SiO is a silicon oxide film ₂ Processing an interlayer interconnection through hole structure in a dielectric layer, which specifically comprises the following steps: at the second SiO ₂ And processing an interlayer interconnection through hole pattern cavity in the dielectric layer, and sequentially depositing and growing a second metal adhesion layer and a second metal circuit layer in the interlayer interconnection through hole pattern cavity respectively, wherein the second metal adhesion layer is used for cementing the second metal circuit layer.

6. The method of fabricating a hermetic radio frequency MEMS device according to claim 1, wherein in step S4, the third SiO is a silicon oxide film ₂ The method for processing the pull-down electrode and the second bonding pad in the dielectric layer specifically comprises the following steps: at the third SiO ₂ Processing a pull-down electrode pattern cavity and a second bonding pad pattern cavity in the dielectric layer, and sequentially depositing and growing a third metal adhesion layer and a third gold in the pull-down electrode pattern cavity and the second bonding pad pattern cavity respectivelyBelongs to a circuit layer.

7. The method of fabricating a hermetically sealed rf MEMS device as claimed in claim 1, wherein in step S5, the fourth SiO is a silicon oxide film ₂ A dielectric layer, the third SiO ₂ Dielectric layer and the second SiO ₂ The method comprises the following steps of: at the fourth SiO ₂ A dielectric layer, the third SiO ₂ Dielectric layer and the second SiO ₂ And processing a contact bump pattern cavity in the dielectric layer, respectively depositing and growing a fourth metal adhesion layer and a metal bump layer at the contact bump pattern cavity in sequence, and processing the metal bump layer to form the contact bump.

8. The method for fabricating a hermetic radio frequency MEMS device according to claim 1, wherein in the step S6, the step of processing a bonding ring in the sacrificial layer comprises the steps of: and processing a bonding ring graph cavity in the sacrificial layer, and then manufacturing the bonding ring in the bonding ring graph cavity.

9. The method of fabricating a hermetic radio frequency MEMS device according to claim 1, wherein in the step S6, the sacrificial layer and the fourth SiO ₂ A dielectric layer, the third SiO ₂ Dielectric layer and the second SiO ₂ An anchor point is processed in the dielectric layer, and the method specifically comprises the following steps: at the sacrificial layer, the fourth SiO ₂ A dielectric layer, the third SiO ₂ Dielectric layer and the second SiO ₂ And processing an anchor point graphic cavity in the dielectric layer, and then manufacturing an anchor point in the anchor point graphic cavity.

10. The method according to claim 1, wherein in the step S6, the sacrificial layer is an organic sacrificial layer or an inorganic sacrificial layer.

11. The method of fabricating a hermetically sealed rf MEMS device according to claim 1, wherein in step S7, the sacrificial layer is released by dry or wet release.

12. The method of manufacturing a hermetically sealed rf MEMS device according to claim 1, wherein in step S8, the method of manufacturing the package cover plate comprises: and simultaneously depositing the masking layer on the upper side and the lower side of the high-resistance silicon wafer, patterning the masking layer on the lower side, and etching the packaging inner cavity in the masking layer on the lower side and the high-resistance silicon wafer.

13. The method of claim 1, wherein the bonded seal ring is formed by depositing a fifth metal adhesion layer and a metal bonding layer, respectively, the fifth metal adhesion layer being used for fixing the metal bonding layer.

14. A hermetically sealed rf MEMS device, characterized in that the hermetically sealed rf MEMS device is fabricated by a fabrication method of the hermetically sealed rf MEMS device according to any one of claims 1-13.