CN112770492A - Design method and system of high-speed signal via hole and storage medium - Google Patents
Design method and system of high-speed signal via hole and storage medium Download PDFInfo
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- CN112770492A CN112770492A CN201910992766.5A CN201910992766A CN112770492A CN 112770492 A CN112770492 A CN 112770492A CN 201910992766 A CN201910992766 A CN 201910992766A CN 112770492 A CN112770492 A CN 112770492A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
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Abstract
The application discloses a design method, a system and a storage medium of high-speed signal through holes, wherein the design method of the high-speed signal through holes firstly classifies the high-speed signal through holes according to the impedance of the through holes so as to obtain multiple types of high-speed signal through holes; then setting parameters of various high-speed signal via holes according to simulation results of various high-speed signal via holes; and finally, corresponding constraint driving is set for various high-speed signals so as to ensure that the routing does not cross reference. The method realizes the purpose of combining the classified use and the constraint drive of the high-speed signal through holes, and the purpose of ensuring that the design of the high-speed signal through holes meets the requirement at one time, so that the design of the high-speed signal through holes does not need to be checked and modified repeatedly in the later period, and the problem of performance reduction of devices caused by improper use of the high-speed signal through holes is also avoided.
Description
Technical Field
The present invention relates to the field of circuit design technologies, and in particular, to a method and a system for designing a high-speed signal via, and a storage medium.
Background
As signal rates continue to ramp up, signal integrity issues for high speed signals are becoming increasingly non-negligible. In the design process of a Printed Circuit Board (PCB), it is important to ensure the impedance continuity of a signal, reduce the influence of reflection on the signal quality, and meet the signal integrity requirement of the signal. The high-speed signal line adopts the difference to walk the line form more, and to the difference line, when designing reasonable line width interval, the design of high-speed signal via hole is also ignorable.
In the design process of the high-speed signal via hole, the design is completely dependent on the experience of designers, the workload of post-inspection modification can be increased due to the problem of improper use of the via hole in the design process of the high-speed signal via hole, and the performance of the finally designed product can be reduced due to the fact that the problem of improper use of the via hole is not checked in the case of the post-inspection modification.
Disclosure of Invention
In order to solve the above technical problems, the present application provides a method, a system and a storage medium for designing a high-speed signal via hole, so as to achieve the purpose of avoiding the situation that the high-speed signal via hole is improperly used in the design process of the high-speed signal via hole.
In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:
a design method of a high-speed signal via hole comprises the following steps:
classifying the high-speed signal through holes according to the through hole impedance so as to obtain multiple types of high-speed signal through holes;
according to the simulation result of each type of high-speed signal via hole, performing parameter setting on each type of high-speed signal via hole;
and setting corresponding constraint drive for various high-speed signals to ensure that the routing does not cross reference.
Optionally, the classifying the high-speed signal via according to the via impedance includes:
high-speed signal vias with a via impedance value of 85 ohms are classified into a class, namely via10g — 85ohm vias;
high-speed signal vias with a via impedance value of 92 ohms are classified into a class, namely via10g — 92ohm vias;
the high-speed signal vias disposed in the BGA area are grouped into a class, referred to as via10g — BGA vias.
Optionally, the performing parameter setting on the various high-speed signal via holes according to the simulation result of the various high-speed signal via holes includes:
the via parameters for via10g — 85ohm via are set to: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.70mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
the via parameters for via10g _92ohm via are set to: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.75mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
via parameters for via10g _ BGA vias are determined according to the manufacturing process and impedance requirements.
Optionally, the determining via parameters of the via10g _ BGA via according to the manufacturing process and the impedance requirement includes:
for a BGA chip designed at high speed as 1mmpitch, and when the hole-to-trace spacing is 0.1mm, the via parameters of via10g _ BGA via are set as: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the via hole reverse bonding pad is 0.65mm, for via10g _ BGA via holes with the via hole impedance value of 92 ohms, the via hole reverse bonding pads are connected into an ellipse, and the value range of the ellipse size is 26mil-30 mil.
Optionally, the setting of the corresponding constraint driver for each type of the high-speed signal includes:
setting the size of a via hole anti-bonding pad in the BGA area to be the sum of a preset size and 4 mils, wherein the preset size is the size of a conventional bonding pad;
setting the distance from the wiring to the hole in the BGA area to be greater than or equal to 4 mil;
setting the distance from the wiring outside the BGA area to the hole to be greater than or equal to 5mil, and setting the size of the via hole reverse bonding pad to be the sum of the preset size and 5 mil;
for via with via impedance value of 92 ohms via10g — 92ohm, the trace-to-via distance is set to be greater than or equal to 6 mils, and the via antipad size is set to the sum of the preset size and 6 mils.
A system for designing a high-speed signal via, comprising:
the via hole classification module classifies the high-speed signal via holes according to the via hole impedance so as to obtain multiple types of high-speed signal via holes;
the parameter setting module is used for setting parameters of various high-speed signal through holes according to simulation results of the various high-speed signal through holes;
and the constraint driving module is used for setting corresponding constraint driving for various high-speed signals so as to ensure that the routing does not cross reference.
Optionally, the via classification module is specifically configured to classify high-speed signal vias with a via impedance value of 85 ohms into a class, which is called via10g — 85ohm vias;
high-speed signal vias with a via impedance value of 92 ohms are classified into a class, namely via10g — 92ohm vias;
the high-speed signal vias disposed in the BGA area are grouped into a class, referred to as via10g — BGA vias.
Optionally, the parameter setting module is specifically configured to set via hole parameters of via10g — 85ohm via holes as follows: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.70mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
the via parameters for via10g _92ohm via are set to: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.75mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
via parameters for via10g _ BGA vias are determined according to the manufacturing process and impedance requirements.
Optionally, the constraint driving module is specifically configured to set a size of a via anti-pad located in the BGA area to a sum of a preset size and 4 mils, where the preset size is a size of a conventional pad;
setting the distance from the wiring to the hole in the BGA area to be greater than or equal to 4 mil;
setting the distance from the wiring outside the BGA area to the hole to be greater than or equal to 5mil, and setting the size of the via hole reverse bonding pad to be the sum of the preset size and 5 mil;
for via with via impedance value of 92 ohms via10g — 92ohm, the trace-to-via distance is set to be greater than or equal to 6 mils, and the via antipad size is set to the sum of the preset size and 6 mils.
A storage medium having stored therein a program for executing the method of designing a high-speed signal via according to any one of the above claims when triggered.
It can be seen from the foregoing technical solutions that the embodiments of the present application provide a method, a system, and a storage medium for designing high-speed signal via holes, wherein the method for designing high-speed signal via holes first classifies the high-speed signal via holes according to the via hole impedance to obtain multiple types of high-speed signal via holes; then setting parameters of various high-speed signal via holes according to simulation results of various high-speed signal via holes; and finally, corresponding constraint driving is set for various high-speed signals so as to ensure that the routing does not cross reference. The method realizes the purpose of combining the classified use and the constraint drive of the high-speed signal through holes, and the purpose of ensuring that the design of the high-speed signal through holes meets the requirement at one time, so that the design of the high-speed signal through holes does not need to be checked and modified repeatedly in the later period, and the problem of performance reduction of devices caused by improper use of the high-speed signal through holes is also avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for designing a high-speed signal via according to an embodiment of the present application;
FIG. 2 is a schematic flow chart illustrating a method for designing a high-speed signal via according to another embodiment of the present application;
FIG. 3 is a schematic flow chart illustrating a method for designing a high-speed signal via according to yet another embodiment of the present application;
FIG. 4 is a schematic diagram of a signal hole and a ground hole provided by an embodiment of the present application;
FIG. 5 is a schematic diagram of a signal hole pitch and ground hole to signal hole pitch as provided by one embodiment of the present application;
FIG. 6 is a schematic flow chart illustrating a method for designing a high-speed signal via according to yet another embodiment of the present application;
fig. 7 is a schematic flow chart illustrating a method for designing a high-speed signal via according to an alternative embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the present application provides a method for designing a high-speed signal via, as shown in fig. 1, including:
s101: classifying the high-speed signal through holes according to the through hole impedance so as to obtain multiple types of high-speed signal through holes;
s102: according to the simulation result of each type of high-speed signal via hole, performing parameter setting on each type of high-speed signal via hole;
s103: and setting corresponding constraint drive for various high-speed signals to ensure that the routing does not cross reference.
In step S103, referring to the special structure on the PCB, the reference path is in the form of a plane, and therefore is also called a reference plane. Cross-referencing means that the reference plane corresponding to the trace is incomplete.
In this embodiment, the method for designing the high-speed signal via hole achieves the purpose of combining the classified use and the constraint driving of the high-speed signal via hole, and achieves the purpose of ensuring that the design of the high-speed signal via hole meets the requirement at one time, so that the design of the high-speed signal via hole does not need to be checked and modified repeatedly in the later period, and the problem of performance reduction of the device caused by improper use of the high-speed signal via hole is also avoided.
On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 2, the method for designing a high-speed signal via includes:
s201: high-speed signal vias with a via impedance value of 85 ohms are classified into a class, namely via10g — 85ohm vias;
s202: high-speed signal vias with a via impedance value of 92 ohms are classified into a class, namely via10g — 92ohm vias;
s203: high-speed signal vias arranged in the BGA area are classified into one type, namely via10g _ BGA vias;
s204: according to the simulation result of each type of high-speed signal via hole, performing parameter setting on each type of high-speed signal via hole;
s205: and setting corresponding constraint drive for various high-speed signals to ensure that the routing does not cross reference.
In the present embodiment, steps S201-S203 provide a practical method of specifically "sorting high speed signal vias according to via impedance". In step S201, the setting region of the high-speed signal via hole with the via hole impedance value of 85 ohms is not a BGA region; the setting region of the high-speed signal via hole having the via hole impedance value of 92 ohms in step S202 is not the BGA region.
Here, BGA refers to ball grid Array (ball grid Array).
In the present embodiment, the description is made only with respect to the classification of the high-speed signal holes, and in general, the ordinary signal holes are named or classified in a conventional manner.
On the basis of the above embodiments, in another embodiment of the present application, as shown in fig. 3, the method for designing a high-speed signal via includes:
s301: high-speed signal vias with a via impedance value of 85 ohms are classified into a class, namely via10g — 85ohm vias;
s302: high-speed signal vias with a via impedance value of 92 ohms are classified into a class, namely via10g — 92ohm vias;
s303: high-speed signal vias arranged in the BGA area are classified into one type, namely via10g _ BGA vias;
s304: the via parameters for via10g — 85ohm via are set to: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.70mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
s305: the via parameters for via10g _92ohm via are set to: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.75mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
s306: determining via parameters of via10g _ BGA vias according to manufacturing process and impedance requirements;
s307: and setting corresponding constraint drive for various high-speed signals to ensure that the routing does not cross reference.
In this embodiment, steps S304-S306 provide a specific way to "perform parameter setting on various types of high-speed signal vias according to simulation results of the various types of high-speed signal vias". In this embodiment, the ground hole refers to a via hole for grounding, the signal hole refers to a via hole for signal transmission, and referring to fig. 4, in fig. 4, reference numeral GND denotes the ground hole, and reference numeral TH denotes the signal hole; referring to fig. 5, P1 denotes a signal hole pitch and P2 denotes a ground hole-to-signal hole pitch in fig. 5.
Optionally, referring to fig. 6, step S306 specifically includes:
s3061: for a BGA chip designed at high speed as 1mmpitch, and when the hole-to-trace spacing is 0.1mm, the via parameters of via10g _ BGA via are set as: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the via hole reverse bonding pad is 0.65mm, for via10g _ BGA via holes with the via hole impedance value of 92 ohms, the via hole reverse bonding pads are connected into an ellipse through rout keepout, and the value range of the ellipse size is 26mil-30 mil.
Wherein 1mmpitch means that the center-to-center distance (pitch) between two pads in the BGAl region is 1mm, and mil is a length unit, and represents one thousandth of an inch, that is, 0.025 mm.
On the basis of the above embodiments, in another embodiment of the present application, as shown in fig. 7, the method for designing a high-speed signal via includes:
s401: classifying the high-speed signal through holes according to the through hole impedance so as to obtain multiple types of high-speed signal through holes;
s402: according to the simulation result of each type of high-speed signal via hole, performing parameter setting on each type of high-speed signal via hole;
s403: setting the size of a via hole anti-bonding pad in the BGA area to be the sum of a preset size and 4 mils, wherein the preset size is the size of a conventional bonding pad;
s404: setting the distance from the wiring to the hole in the BGA area to be greater than or equal to 4 mil;
s405: setting the distance from the wiring outside the BGA area to the hole to be greater than or equal to 5mil, and setting the size of the via hole reverse bonding pad to be the sum of the preset size and 5 mil;
s406: for via with via impedance value of 92 ohms via10g — 92ohm, the trace-to-via distance is set to be greater than or equal to 6 mils, and the via antipad size is set to the sum of the preset size and 6 mils.
In the present embodiment, steps S403 to S406 provide a specific way of "setting corresponding constraint driving for each type of the high-speed signal". The distance from the trace to the hole refers to the distance from the trace to the signal hole and the distance from the trace to the ground hole.
The following describes a system for designing a high-speed signal via provided in an embodiment of the present application, and the system for designing a high-speed signal via described below and the method for designing a high-speed signal via described above may be referred to in correspondence.
Correspondingly, the embodiment of the present application provides a system for designing a high-speed signal via, including:
the via hole classification module classifies the high-speed signal via holes according to the via hole impedance so as to obtain multiple types of high-speed signal via holes;
the parameter setting module is used for setting parameters of various high-speed signal through holes according to simulation results of the various high-speed signal through holes;
and the constraint driving module is used for setting corresponding constraint driving for various high-speed signals so as to ensure that the routing does not cross reference.
Optionally, the via classification module is specifically configured to classify high-speed signal vias with a via impedance value of 85 ohms into a class, which is called via10g — 85ohm vias;
high-speed signal vias with a via impedance value of 92 ohms are classified into a class, namely via10g — 92ohm vias;
the high-speed signal vias disposed in the BGA area are grouped into a class, referred to as via10g — BGA vias.
Optionally, the parameter setting module is specifically configured to set via hole parameters of via10g — 85ohm via holes as follows: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.70mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
the via parameters for via10g _92ohm via are set to: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.75mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
via parameters for via10g _ BGA vias are determined according to the manufacturing process and impedance requirements.
Optionally, the constraint driving module is specifically configured to set a size of a via anti-pad located in the BGA area to a sum of a preset size and 4 mils, where the preset size is a size of a conventional pad;
setting the distance from the wiring to the hole in the BGA area to be greater than or equal to 4 mil;
setting the distance from the wiring outside the BGA area to the hole to be greater than or equal to 5mil, and setting the size of the via hole reverse bonding pad to be the sum of the preset size and 5 mil;
for via with via impedance value of 92 ohms via10g — 92ohm, the trace-to-via distance is set to be greater than or equal to 6 mils, and the via antipad size is set to the sum of the preset size and 6 mils.
Correspondingly, the embodiment of the present application further provides a storage medium, where the storage medium stores a program, and the program is used to execute the design method of the high-speed signal via according to any of the above embodiments when triggered.
In summary, the embodiments of the present application provide a method, a system, and a storage medium for designing high-speed signal via holes, wherein the method for designing high-speed signal via holes first classifies the high-speed signal via holes according to the via hole impedance to obtain multiple types of high-speed signal via holes; then setting parameters of various high-speed signal via holes according to simulation results of various high-speed signal via holes; and finally, corresponding constraint driving is set for various high-speed signals so as to ensure that the routing does not cross reference. The method realizes the purpose of combining the classified use and the constraint drive of the high-speed signal through holes, and the purpose of ensuring that the design of the high-speed signal through holes meets the requirement at one time, so that the design of the high-speed signal through holes does not need to be checked and modified repeatedly in the later period, and the problem of performance reduction of devices caused by improper use of the high-speed signal through holes is also avoided.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for designing a high-speed signal via, comprising:
classifying the high-speed signal through holes according to the through hole impedance so as to obtain multiple types of high-speed signal through holes;
according to the simulation result of each type of high-speed signal via hole, performing parameter setting on each type of high-speed signal via hole;
and setting corresponding constraint drive for various high-speed signals to ensure that the routing does not cross reference.
2. The method of claim 1, wherein the classifying the high-speed signal vias according to via impedances comprises:
high-speed signal vias with a via impedance value of 85 ohms are classified into a class, namely via10g — 85ohm vias;
high-speed signal vias with a via impedance value of 92 ohms are classified into a class, namely via10g — 92ohm vias;
the high-speed signal vias disposed in the BGA area are grouped into a class, referred to as via10g — BGA vias.
3. The method for designing high-speed signal via holes according to claim 2, wherein the performing parameter setting on each type of high-speed signal via holes according to the simulation result of each type of high-speed signal via holes comprises:
the via parameters for via10g — 85ohm via are set to: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.70mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
the via parameters for via10g _92ohm via are set to: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.75mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
via parameters for via10g _ BGA vias are determined according to the manufacturing process and impedance requirements.
4. The method of claim 3, wherein determining via parameters for via10g _ BGA vias comprises, in accordance with manufacturing process and impedance requirements:
for a BGA chip designed at high speed as 1mm pitch, and when the hole-to-trace spacing is 0.1mm, the via parameters of via10g _ BGA via are set as: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the via hole reverse bonding pad is 0.65mm, for via10g _ BGA via holes with the via hole impedance value of 92 ohms, the via hole reverse bonding pads are connected into an ellipse, and the value range of the ellipse size is 26mil-30 mil.
5. The method for designing a high-speed signal via according to claim 1, wherein the setting of the corresponding constraint driver for each type of the high-speed signal comprises:
setting the size of a via hole anti-bonding pad in the BGA area to be the sum of a preset size and 4 mils, wherein the preset size is the size of a conventional bonding pad;
setting the distance from the wiring to the hole in the BGA area to be greater than or equal to 4 mil;
setting the distance from the wiring outside the BGA area to the hole to be greater than or equal to 5mil, and setting the size of the via hole reverse bonding pad to be the sum of the preset size and 5 mil;
for via with via impedance value of 92 ohms via10g — 92ohm, the trace-to-via distance is set to be greater than or equal to 6 mils, and the via antipad size is set to the sum of the preset size and 6 mils.
6. A system for designing a high speed signal via, comprising:
the via hole classification module classifies the high-speed signal via holes according to the via hole impedance so as to obtain multiple types of high-speed signal via holes;
the parameter setting module is used for setting parameters of various high-speed signal through holes according to simulation results of the various high-speed signal through holes;
and the constraint driving module is used for setting corresponding constraint driving for various high-speed signals so as to ensure that the routing does not cross reference.
7. The system for designing high-speed signal vias of claim 6, wherein the via classification module is specifically configured to classify high-speed signal vias having a via impedance value of 85 ohms into a class, referred to as via10g — 85ohm vias;
high-speed signal vias with a via impedance value of 92 ohms are classified into a class, namely via10g — 92ohm vias;
the high-speed signal vias disposed in the BGA area are grouped into a class, referred to as via10g — BGA vias.
8. The system for designing a high-speed signal via according to claim 7, wherein the parameter setting module is specifically configured to set via parameters of via10g — 85ohm via as follows: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.70mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
the via parameters for via10g _92ohm via are set to: the finished aperture is 0.2mm, the diameter of the surface layer bonding pad is 0.45mm, the diameter of the anti-bonding pad is 0.75mm, the distance between signal holes is 30mil, the distance between a ground hole and a signal hole is 30mil, and the centers of the signal hole and the ground hole are on the same straight line;
via parameters for via10g _ BGA vias are determined according to the manufacturing process and impedance requirements.
9. The system for designing high-speed signal vias of claim 6, wherein the constraint driving module is specifically configured to set the size of the via antipad located in the BGA area to a sum of a preset size and 4 mils, wherein the preset size is the size of a regular pad;
setting the distance from the wiring to the hole in the BGA area to be greater than or equal to 4 mil;
setting the distance from the wiring outside the BGA area to the hole to be greater than or equal to 5mil, and setting the size of the via hole reverse bonding pad to be the sum of the preset size and 5 mil;
for via with via impedance value of 92 ohms via10g — 92ohm, the trace-to-via distance is set to be greater than or equal to 6 mils, and the via antipad size is set to the sum of the preset size and 6 mils.
10. A storage medium having a program stored therein, the program when triggered being used to perform the method of designing a high speed signal via according to any one of claims 1 to 5.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114137332A (en) * | 2021-10-26 | 2022-03-04 | 中科可控信息产业有限公司 | Signal testing device, method, computer equipment and storage medium |
| CN114184933A (en) * | 2021-11-26 | 2022-03-15 | 浪潮(北京)电子信息产业有限公司 | Backflow ground hole detection method, system, device and computer readable storage medium |
| CN114449762A (en) * | 2021-12-24 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Method, device, equipment and medium for optimizing BGA chip pin map |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6859915B1 (en) * | 2003-02-13 | 2005-02-22 | Hewlett-Packard Development Company, L.P. | Signal line impedance verification tool |
| US6971077B1 (en) * | 2003-02-13 | 2005-11-29 | Hewlett-Packard Development Company, L.P. | Signal line impedance adjustment tool |
| CN1756460A (en) * | 2004-09-30 | 2006-04-05 | 华为技术有限公司 | High-density BGA printed circuit board wiring method |
| US20060255876A1 (en) * | 2003-06-02 | 2006-11-16 | Nec Corporation | Compact via transmission line for printed circuit board and its designing method |
| JP2010021198A (en) * | 2008-07-08 | 2010-01-28 | Renesas Technology Corp | Wiring substrate, and semiconductor device using the same |
| CN102364478A (en) * | 2011-10-17 | 2012-02-29 | 中兴通讯股份有限公司 | Simulation method, device and system for high speed signal channel via holes |
| CN103793575A (en) * | 2014-02-19 | 2014-05-14 | 浪潮(北京)电子信息产业有限公司 | Method and device for arranging passing holes in single plate |
| CN104102757A (en) * | 2013-04-15 | 2014-10-15 | 鸿富锦精密工业（深圳）有限公司 | Through-hole design system |
| CN105550460A (en) * | 2015-12-30 | 2016-05-04 | 迈普通信技术股份有限公司 | Electronic circuit board wiring assessment method and apparatus |
| CN105578714A (en) * | 2015-12-11 | 2016-05-11 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A new laminate structure of multi-layer high-speed PCB and signal via hole optimization method |
| CN107194065A (en) * | 2017-05-19 | 2017-09-22 | 郑州云海信息技术有限公司 | A kind of method for being checked in PCB design and setting binding occurrence |
| US20180137228A1 (en) * | 2016-11-14 | 2018-05-17 | Fujitsu Limited | Simulation assist apparatus and simulation assist method |
| CN108882513A (en) * | 2018-08-30 | 2018-11-23 | 郑州云海信息技术有限公司 | A kind of dig a hole method, apparatus and system for keeping away line automatically |
| CN109379835A (en) * | 2018-10-16 | 2019-02-22 | 郑州云海信息技术有限公司 | A PCB board high-speed signal via design method, via structure and a PCB board |
| CN109558683A (en) * | 2018-12-03 | 2019-04-02 | 上海泽丰半导体科技有限公司 | A kind of data information input method and system based on Via Wizard software |
-
2019
- 2019-10-18 CN CN201910992766.5A patent/CN112770492B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6971077B1 (en) * | 2003-02-13 | 2005-11-29 | Hewlett-Packard Development Company, L.P. | Signal line impedance adjustment tool |
| US6859915B1 (en) * | 2003-02-13 | 2005-02-22 | Hewlett-Packard Development Company, L.P. | Signal line impedance verification tool |
| US20060255876A1 (en) * | 2003-06-02 | 2006-11-16 | Nec Corporation | Compact via transmission line for printed circuit board and its designing method |
| CN1756460A (en) * | 2004-09-30 | 2006-04-05 | 华为技术有限公司 | High-density BGA printed circuit board wiring method |
| JP2010021198A (en) * | 2008-07-08 | 2010-01-28 | Renesas Technology Corp | Wiring substrate, and semiconductor device using the same |
| CN102364478A (en) * | 2011-10-17 | 2012-02-29 | 中兴通讯股份有限公司 | Simulation method, device and system for high speed signal channel via holes |
| CN104102757A (en) * | 2013-04-15 | 2014-10-15 | 鸿富锦精密工业（深圳）有限公司 | Through-hole design system |
| CN103793575A (en) * | 2014-02-19 | 2014-05-14 | 浪潮(北京)电子信息产业有限公司 | Method and device for arranging passing holes in single plate |
| CN105578714A (en) * | 2015-12-11 | 2016-05-11 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A new laminate structure of multi-layer high-speed PCB and signal via hole optimization method |
| CN105550460A (en) * | 2015-12-30 | 2016-05-04 | 迈普通信技术股份有限公司 | Electronic circuit board wiring assessment method and apparatus |
| US20180137228A1 (en) * | 2016-11-14 | 2018-05-17 | Fujitsu Limited | Simulation assist apparatus and simulation assist method |
| CN107194065A (en) * | 2017-05-19 | 2017-09-22 | 郑州云海信息技术有限公司 | A kind of method for being checked in PCB design and setting binding occurrence |
| CN108882513A (en) * | 2018-08-30 | 2018-11-23 | 郑州云海信息技术有限公司 | A kind of dig a hole method, apparatus and system for keeping away line automatically |
| CN109379835A (en) * | 2018-10-16 | 2019-02-22 | 郑州云海信息技术有限公司 | A PCB board high-speed signal via design method, via structure and a PCB board |
| CN109558683A (en) * | 2018-12-03 | 2019-04-02 | 上海泽丰半导体科技有限公司 | A kind of data information input method and system based on Via Wizard software |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114137332A (en) * | 2021-10-26 | 2022-03-04 | 中科可控信息产业有限公司 | Signal testing device, method, computer equipment and storage medium |
| CN114184933A (en) * | 2021-11-26 | 2022-03-15 | 浪潮(北京)电子信息产业有限公司 | Backflow ground hole detection method, system, device and computer readable storage medium |
| CN114184933B (en) * | 2021-11-26 | 2024-04-05 | 浪潮(北京)电子信息产业有限公司 | Method, system, device and computer readable storage medium for detecting backflow ground hole |
| CN114449762A (en) * | 2021-12-24 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Method, device, equipment and medium for optimizing BGA chip pin map |
| CN114449762B (en) * | 2021-12-24 | 2023-08-25 | 苏州浪潮智能科技有限公司 | Method, device, equipment and medium for optimizing BGA chip pin distribution diagram |
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