CN112768937B - High isolation phased array antenna module and phased array antenna array - Google Patents
High isolation phased array antenna module and phased array antenna array Download PDFInfo
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- CN112768937B CN112768937B CN202110075471.9A CN202110075471A CN112768937B CN 112768937 B CN112768937 B CN 112768937B CN 202110075471 A CN202110075471 A CN 202110075471A CN 112768937 B CN112768937 B CN 112768937B
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- 238000002955 isolation Methods 0.000 title claims abstract description 71
- 230000003071 parasitic effect Effects 0.000 claims abstract description 60
- 230000005855 radiation Effects 0.000 claims description 19
- 238000009434 installation Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 12
- 238000004080 punching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/52—Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
- H01Q1/521—Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure reducing the coupling between adjacent antennas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
- H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
- H01Q21/061—Two dimensional planar arrays
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- Variable-Direction Aerials And Aerial Arrays (AREA)
Abstract
本发明的实施例提供了一种高隔离度相控阵天线模块和相控阵天线阵面，涉及天线技术领域，该高隔离度相控阵天线模块包括电路板和多个阵列设置在电路板上的辐射单元，相邻两个辐射单元之间设置有第一寄生单元，第一寄生单元用于优化相邻两个辐射单元间的隔离度。通过在相邻的辐射单元之间设置第一寄生单元，从而优化了相邻两个辐射单元间的隔离度，避免了辐射单元之间相互影响，优化了组阵后的相控阵天线的性能。相较于现有技术，本发明优化了辐射单元之间的隔离度，提升了天线性能，同时避免了复杂的开孔工艺，工艺简单且成本低。
The embodiments of the present invention provide a high-isolation phased array antenna module and a phased array antenna array, which relate to the field of antenna technology. The high-isolation phased array antenna module includes a circuit board and a plurality of radiating units arranged in an array on the circuit board, and a first parasitic unit is arranged between two adjacent radiating units, and the first parasitic unit is used to optimize the isolation between the two adjacent radiating units. By arranging the first parasitic unit between adjacent radiating units, the isolation between the two adjacent radiating units is optimized, the mutual influence between the radiating units is avoided, and the performance of the phased array antenna after the array is optimized. Compared with the prior art, the present invention optimizes the isolation between the radiating units, improves the antenna performance, and avoids the complicated hole opening process at the same time, and the process is simple and the cost is low.
Description
Technical Field
The invention relates to the technical field of antennas, in particular to a high-isolation phased array antenna module and a phased array antenna array surface.
Background
The AiP (Antennas in Package) antenna is applied to a mobile phone antenna or a wearable intelligent device, and is generally an omni-directional antenna or is used for scanning a beam in a small range, and the number of units is smaller, such as 1x4, 2x2 or 4x4. There is no clear requirement for the isolation between adjacent cells, and the array is generally performed at a pitch of half a wavelength. The adjacent units are assembled according to the interval, the isolation between the adjacent units is usually-12 dB to-15 dB, if isolation holes are added between the adjacent units, the isolation between the adjacent units can be optimized to be-17 dB to-20 dB, but since AiP is a packaged antenna, if not special, the isolation holes are not added, the process complexity is increased, and the cost is increased.
Disclosure of Invention
The invention aims at providing a high-isolation phased array antenna module and a phased array antenna array surface, which can optimize isolation between adjacent units, and have simple process and low process cost.
Embodiments of the invention may be implemented as follows:
In a first aspect, the present invention provides a phased array antenna module with high isolation, which includes a circuit board and a plurality of radiating elements arranged on the circuit board in an array, wherein a first parasitic element is arranged between two adjacent radiating elements, and the first parasitic element is used for optimizing isolation between the two adjacent radiating elements.
In an alternative embodiment, each first parasitic element is provided with a first gap groove extending to the surface of the circuit board, the first gap groove divides the first parasitic element into two first patches, and the two first patches are oppositely arranged at two sides of the first gap groove.
In an alternative embodiment, two opposite sides of the first patches are provided with second clearance grooves, the two second clearance grooves extend towards directions deviating from each other, and each second clearance groove is communicated with the first clearance groove.
In an alternative embodiment, the extending direction of the first clearance groove is parallel to the central connecting line of two adjacent radiating units, and the extending direction of the second clearance groove is perpendicular to the extending direction of the first clearance.
In an alternative embodiment, the width of the first clearance groove is greater than the width of the second clearance groove.
In an alternative embodiment, the edge of the circuit board is further provided with a plurality of second parasitic elements, which are arranged outside the plurality of radiating elements.
In an alternative embodiment, a third gap groove extending to the surface of the circuit board is arranged on the second parasitic element, the third gap groove divides the second parasitic element into two second patches, and the two second patches are oppositely arranged at two sides of the third gap groove.
In an alternative embodiment, a fourth clearance groove is formed in one side, opposite to the second patches, of each second patch, the two fourth clearance grooves extend in directions away from each other, and each fourth clearance groove is communicated with the third clearance groove and extends outwards to the edge of the circuit board.
In an alternative embodiment, the width of the first parasitic element in the direction perpendicular to the central connecting line of two adjacent radiating elements is the same as the width of the corresponding adjacent two radiating elements, and the width of the second parasitic element in the direction parallel to the edge of the circuit board is the same as the width of the corresponding radiating element.
In a second aspect, the present invention provides a phased array antenna array plane, which includes a plurality of high isolation phased array antenna modules according to any of the foregoing embodiments, a plurality of circuit boards are spliced together, and a mounting gap is provided between two adjacent circuit boards.
The beneficial effects of the embodiment of the invention include, for example:
According to the high-isolation phased array antenna module and the phased array antenna array surface, the first parasitic units are arranged between the adjacent radiation units, so that the isolation between the two adjacent radiation units is optimized, the mutual influence between the radiation units is avoided, and the performance of the phased array antenna after the phased array is assembled is optimized. Compared with the prior art, the invention optimizes the isolation between the radiating units, improves the antenna performance, and simultaneously avoids complex perforating technology, and has simple technology and low cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a high isolation phased array antenna module according to a first embodiment of the present invention;
FIG. 2 is an enlarged partial schematic view of II in FIG. 1;
Fig. 3 is a schematic structural diagram of a phased array antenna array according to a second embodiment of the present invention.
The icons are 100-high isolation phased array antenna module, 110-circuit board, 130-radiating element, 150-first parasitic element, 151-first patch, 153-first slot, 155-second slot, 170-second parasitic element, 171-second patch, 173-third slot, 175-fourth slot, 200-phased array antenna array face, 210-mounting slot.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
As disclosed in the background art, the number of units of the conventional Aip (Antennas in Package) antenna module is generally small, generally 1x4, or 2x2, or 4x4, and in the case of such small number of units, there is generally no requirement for isolation between units. However, when forming an array surface by stitching, for example, forming a 64-channel array, it is necessary to consider the isolation between cells. In the prior art, isolation is usually achieved by using an open-pore process, i.e., dense metallized through holes are formed between adjacent cells to optimize the isolation between adjacent cells.
However, since AiP is a packaged antenna, if not the case, the addition of isolation holes is not generally performed, and the addition of isolation holes generally requires punching operations on the substrate, and metal layer plating is required to implement metallization of the isolation holes, the addition of isolation holes increases the complexity of the process, and the cost is optimized.
In order to solve the problems, the invention provides a novel high-isolation phased array antenna module, which can achieve the purpose of increasing isolation without punching and saves cost. It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1 to 3, the present embodiment provides a high isolation phased array antenna module 100, which can optimize isolation between adjacent units without punching, and has simple process and low process cost.
The high isolation phased array antenna module 100 provided in this embodiment includes a circuit board 110 and a plurality of radiating units 130 arranged on the circuit board 110 in an array, wherein a first parasitic unit 150 is disposed between two adjacent radiating units 130, and the first parasitic unit 150 is used for optimizing the isolation between two adjacent radiating units 130.
In this embodiment, the first parasitic element 150 is not electrically connected to the feeding element below the circuit board 110, and by adding the first parasitic element 150 between two adjacent radiating elements 130, the isolation between the two radiating elements 130 can be effectively optimized, so as to avoid the mutual influence between the two adjacent radiating elements 130.
It should be noted that, in the present embodiment, the circuit board 110 is a PCB board, and the plurality of radiating units 130 are arranged on the surface of the circuit board 110 in an array manner. Specifically, in this embodiment, the high-isolation phased array antenna module 100 is a 4x4 channel, that is, a single circuit board 110 is provided with 16 radiating elements 130,16 arranged in a 4x4 manner, and arrays of radiating elements 130 are distributed on the surface of the circuit board 110, and a first parasitic element 150 is disposed between two adjacent radiating elements 130. The first parasitic elements 150 are located at the middle position of two adjacent radiating elements 130 and have the same distance with the two adjacent radiating elements 130, and 24 first parasitic elements 150 are totally arranged on the circuit board 110 and are distributed among 16 radiating elements 130 on the circuit board 110 in a 3-horizontal-3-vertical mode, so that one first parasitic element 150 is arranged between every two radiating elements 130. Of course, the number of radiating elements 130 and first parasitic elements 150 are merely illustrative and will not be described in detail herein for other high isolation phased array antenna modules 100, such as 1x4 or 2x2 channels.
In the present embodiment, each first parasitic element 150 is provided with a first gap groove 153 extending to the surface of the circuit board 110, the first gap groove 153 divides the first parasitic element 150 into two first patches 151, and the two first patches 151 are disposed on two opposite sides of the first gap groove 153. Specifically, the first clearance groove 153 penetrates through the first parasitic element 150, extends downwards to the surface of the circuit board 110, and separates the first parasitic element 150 into two first patches 151 symmetrically arranged, and the two first patches 151 can realize isolation effect on the adjacent radiation units 130.
In the present embodiment, the opposite sides of the two first patches 151 are provided with the second clearance grooves 155, and the two second clearance grooves 155 extend in directions away from each other, and each of the second clearance grooves 155 communicates with the first clearance groove 153. Specifically, the second clearance grooves 155 extend downward to the surface of the circuit board 110, and the second clearance grooves 155 do not penetrate the first patches 151 in the horizontal direction, so that the first patches 151 exhibit a C-shape, and the two first patches 151 are symmetrically disposed at both sides of the first clearance groove 153.
Note that, in this embodiment, the first patches 151 are formed by an etching process, specifically, the first clearance grooves 153 and the second clearance grooves 155 are formed after patterning, so that two first patches 151 disposed symmetrically are formed.
In the present embodiment, the extending direction of the first clearance groove 153 is parallel to the central line of the adjacent two radiating units 130, and the extending direction of the second clearance groove 155 is perpendicular to the extending direction of the first clearance. Specifically, two second clearance grooves 155 are symmetrically distributed on both sides of the first clearance groove 153, and the first clearance groove 153 and the two second clearance grooves 155 form a cross-shaped grooved structure.
In the present embodiment, the width of the first parasitic element 150 in the direction perpendicular to the central line of the adjacent two radiating elements 130 is the same as the width of the corresponding adjacent two radiating elements 130. Specifically, the distance between the ends of the two first patches 151 that are far from each other is the same as the width of the radiating element 130, so that the two first patches 151 are distributed flush with both sides of the radiating element 130.
It should be noted that, the central line of two radiation units 130 in this embodiment refers to a line of geometric centers of two adjacent radiation units 130, and specifically, the line passes through the corresponding first clearance groove 153 and coincides with the center line of the first clearance groove 153.
In the present embodiment, the width of the first clearance groove 153 is larger than the width of the second clearance groove 155. Specifically, the width of the first clearance groove 153 is determined by simulation software for depth adjustment of the isolation, i.e., the first clearance groove 153 of different widths is set for different isolation requirements. The width of the second gap groove 155 is also determined by simulation software and can be used for frequency adjustment, acting in conjunction with the first gap groove 153, to optimize the isolation between adjacent radiating elements 130.
In the present embodiment, the edge of the circuit board 110 is further provided with a plurality of second parasitic elements 170, and the second parasitic elements 170 are disposed outside the plurality of radiating elements 130. Specifically, the second parasitic elements 170 are disposed on the outer sides of the radiation units 130 disposed near the edge of the circuit board 110, and in this embodiment, 16 second parasitic elements 170 are also disposed uniformly at the peripheral edge of the circuit board 110 and correspond to the peripheral radiation units 130.
It should be noted that, in the present embodiment, the outer sides of the plurality of radiating elements 130 refer to the side of the radiating element 130 away from the center point of the circuit board 110. Specifically, since the radiation units 130 in the present embodiment use 4x4 channels, 4 of the radiation units 130 are located in the inner layer, 12 of the radiation units 130 are located in the outer layer, the outer layer is surrounded by the inner layer, and the plurality of second parasitic units 170 are distributed on the outer side of the outer layer, that is, 16 second parasitic units 170 are surrounded by the outer layer and are disposed near the edge of the circuit board 110.
In the present embodiment, the second parasitic element 170 is provided with a third gap groove 173 extending to the surface of the circuit board 110, the third gap groove 173 divides the second parasitic element 170 into two second patches 171, and the two second patches 171 are disposed on two opposite sides of the third gap groove 173. Specifically, the third gap groove 173 penetrates the second parasitic element 170 and extends downward to the surface of the circuit board 110, and the third gap groove 173 separates the second parasitic element 170 into two second patches 171 that are symmetrically disposed, when the phased array antenna array surface is formed by stitching, the two second patches 171 on the circuit board 110 can co-act with the two second patches 171 on the adjacent circuit board 110, so as to realize the isolation of the radiating element 130 on the adjacent circuit board 110.
It should be noted that, in the present embodiment, the width of the third clearance groove 173 is the same as the width of the first clearance groove 153, which is also determined by simulation software, for the depth adjustment of the isolation, that is, the third clearance groove 173 with different widths is set for the requirements of different isolation.
In the present embodiment, the opposite sides of the two second patches 171 are provided with fourth clearance grooves 175, and the two fourth clearance grooves 175 extend in directions away from each other, and each fourth clearance groove 175 communicates with the third clearance groove 173 and extends outward to the edge of the circuit board 110. Specifically, the fourth gap groove 175 is formed on a side of the second patch 171 away from the radiating unit 130 on the same circuit board 110, and the fourth gap groove 175 is an open gap groove for splicing with the fourth gap groove 175 on an adjacent circuit board 110 during splicing. Meanwhile, in the horizontal direction, the fourth clearance groove 175 does not penetrate through the second patch 171, so that the second patch 171 is L-shaped and is convenient to splice with the adjacent second patch 171.
It should be noted that, in the present embodiment, the distance between the second patch 171 and the corresponding radiating unit 130 is the same as the distance between the first patch 151 and the corresponding radiating unit 130, so that the second patch 171 and the first patch 151 are uniformly distributed around the radiating unit 130, and the isolation effect is better.
It should be further noted that, in this embodiment, the width of the fourth gap groove 175 is related to the width of the mounting slot 210 on the phased array antenna array surface formed after the phased array antenna array is assembled, specifically, it may be determined according to simulation software that the width of the fourth gap groove 175 is used to adjust the frequency, preferably, 2 times of the width of the fourth gap groove 175 plus the width of the mounting slot 210 is equal to the width of the second gap groove 155, and the width of the third gap groove 173 is combined with the width of the first gap groove 153 to be the same, so that the isolation between the radiating elements 130 on two adjacent circuit boards 110 is the same as the isolation between the radiating elements 130 on the same circuit board 110, that is, the parasitic structures around each radiating element 130 are the same, so that the radiation performance in each channel is kept consistent, and the isolation between the radiating elements 130 is optimized.
In the present embodiment, the width of the second parasitic element 170 in the direction parallel to the edge of the circuit board 110 is the same as the width of the corresponding radiating element 130. Specifically, the distance between the ends of the two second patches 171 that are away from each other is the same as the width of the radiating element 130, so that the two second patches 171 are distributed flush with the two sides of the radiating element 130.
In summary, this embodiment provides a phased array antenna module 100 with high isolation, by arranging the first parasitic element 150 between the adjacent radiating elements 130, thereby optimizing the isolation between the adjacent radiating elements 130, avoiding the mutual influence between the radiating elements 130, and simultaneously arranging the second parasitic element 170 at the edge of the circuit board 110, so that the isolation between the radiating elements 130 on the two adjacent circuit boards 110 after the array is optimized, thereby optimizing the performance of the phased array antenna after the array, and simultaneously, without adopting a punching process, reducing the process difficulty and saving the cost.
Second embodiment
With continued reference to fig. 3, the present embodiment provides a phased array antenna array plane 200, which includes a plurality of high-isolation phased array antenna modules 100, wherein the basic structure and principles of the high-isolation phased array antenna modules 100 and the technical effects thereof are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents in the first embodiment.
The phased array antenna array plane 200 provided in this embodiment includes a plurality of high isolation phased array antenna modules 100, where the high isolation phased array antenna modules 100 include a circuit board 110 and a plurality of radiating units 130 arranged on the circuit board 110 in array, a first parasitic unit 150 is disposed between two adjacent radiating units 130, and the first parasitic unit 150 is used to optimize isolation between two adjacent radiating units 130. The edge of the circuit board 110 is further provided with a plurality of second parasitic elements 170, and the second parasitic elements 170 are disposed outside the plurality of radiating elements 130. The plurality of circuit boards 110 are spliced together with a mounting gap 210 between two adjacent circuit boards 110.
In this embodiment, the two second parasitic elements 170 on the adjacent circuit boards 110 are spliced with each other, so that the isolation between the radiating elements 130 on the adjacent circuit boards 110 can be optimized, and the isolation between every two adjacent radiating elements 130 after the array is assembled can be optimized.
According to the phased array antenna array surface 200 provided by the embodiment, the first parasitic units 150 are arranged between the adjacent radiation units 130, so that the isolation between the adjacent two radiation units 130 is optimized, the mutual influence between the radiation units 130 is avoided, and meanwhile, the second parasitic units 170 are arranged at the edges of the circuit boards 110, so that the isolation between the radiation units 130 on the two adjacent circuit boards 110 after the phased array is optimized, and the performance of the phased array antenna array surface 200 after the phased array is optimized.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
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| CN202110075471.9A CN112768937B (en) | 2021-01-20 | 2021-01-20 | High isolation phased array antenna module and phased array antenna array |
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| CN202110075471.9A CN112768937B (en) | 2021-01-20 | 2021-01-20 | High isolation phased array antenna module and phased array antenna array |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109524783A (en) * | 2017-09-20 | 2019-03-26 | 西安四海达通信科技有限公司 | Reduce the method and relevant multiaerial system, wireless telecommunications system of antenna coupling |
| CN214477906U (en) * | 2021-01-20 | 2021-10-22 | 成都天锐星通科技有限公司 | High-isolation phased array antenna module and phased array antenna array plane |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101834349B (en) * | 2010-05-05 | 2012-08-29 | 电子科技大学 | Microstrip patch antenna with reconfigurable directional diagram |
| WO2014099079A1 (en) * | 2012-09-27 | 2014-06-26 | Raytheon Company | Methods and apparatus for fragmented phased array radar |
| WO2017150054A1 (en) * | 2016-03-04 | 2017-09-08 | 株式会社村田製作所 | Array antenna |
| CN110311224A (en) * | 2019-07-23 | 2019-10-08 | 深圳锐越微技术有限公司 | Small spacing micro-strip antenna array |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109524783A (en) * | 2017-09-20 | 2019-03-26 | 西安四海达通信科技有限公司 | Reduce the method and relevant multiaerial system, wireless telecommunications system of antenna coupling |
| CN214477906U (en) * | 2021-01-20 | 2021-10-22 | 成都天锐星通科技有限公司 | High-isolation phased array antenna module and phased array antenna array plane |
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