CN112768522B - Superjunction device and method of manufacturing the same - Google Patents

Abstract

The present invention discloses a superjunction device, wherein the superjunction structure is formed above the surface of the first N-type epitaxial layer, the width of the P-type column at the top position of the superjunction unit is smaller than the width of the N-type column and the step is constant; the N-type column is composed of the second N-type epitaxial layer filled in the groove, the P-type column is composed of the first P-type epitaxial layer between the grooves, and the first P-type epitaxial layer is formed on the first N-type epitaxial layer; the groove passes through the first P-type epitaxial layer and the bottom is in contact with the first N-type epitaxial layer; the total amount of P-type impurities of the P-type column in the superjunction unit matches the total amount of N-type impurities of the N-type column, and the doping concentration of the P-type column is higher than the doping concentration of the N-type column. The present invention also discloses a method for manufacturing a superjunction device. The present invention can reduce the difficulty of process control and improve the consistency of the device; when the groove is inclined, the high-temperature on-resistance of the device can be reduced, the difference in PN impurities between the top and bottom of the superjunction unit can be reduced, and the breakdown voltage of the device can be improved.

Description

Super junction device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction device; the present invention also relates to a method for manufacturing the super junction device.

Background Art

The super junction structure is a structure of alternating N-type columns and P-type columns, i.e., PN columns. If the super junction structure is used to replace the N-type drift region in the vertical double diffused MOS transistor (VDMOS) device, it provides a conduction path in the on state (only the N-type column provides the path, the P-type column does not provide it), and withstands the reverse bias voltage in the off state (both the PN columns withstand it), thus forming a super junction metal-oxide semiconductor field-effect transistor (MOSFET). Super junction MOSFET can significantly reduce the on-resistance of the device by using a low-resistivity epitaxial layer while maintaining the reverse breakdown voltage consistent with that of the traditional VDMOS device.

By forming a trench in the N-type epitaxial layer and filling the trench with a P-type epitaxial layer, alternatingly arranged PN columns are formed. This is a super junction manufacturing method that can be mass-produced.

In the prior art, in order to obtain a lower specific on-resistance, the width of the N-type column of the PN column is generally designed to be greater than or equal to the width of the P-type column, so as to ensure that the area of the N-type region is increased and the specific on-resistance of the device is reduced. For example, in actual use, the width of the P-type column and the width of the N-type column are 5 microns/12 microns, 5 microns/8 microns, 5 microns/6 microns, 4 microns/5 microns, and 2 microns/3 microns, where the number before the "/" represents the width of the P-type column and the number after the "/" represents the width of the N-type column. However, in the manufacturing process, especially in the trench process, the small width of the P column increases the difficulty of process control, and at the same time causes the concentration of filling impurities to increase. Moreover, due to the increase in the absolute value of the concentration, the same percentage of process change will increase the change in the total amount of impurities, the degree of charge imbalance will be serious, and the deviation of device performance, including the deviation of breakdown voltage, will be large, affecting the consistency of the device.

Summary of the invention

The technical problem to be solved by the present invention is to provide a super junction device, which can reduce the difficulty of process control and improve the consistency of the device. To this end, the present invention also provides a method for manufacturing a super junction device.

In order to solve the above technical problems, the super junction device provided by the present invention includes a super junction structure formed by alternating P-type columns and N-type columns; the super junction device is an N-type device and is formed on the super junction structure; one P-type column and an adjacent N-type column constitute a super junction unit.

The super junction structure is formed above the surface of a first N-type epitaxial layer, the first N-type epitaxial layer is formed on an N-type highly doped semiconductor substrate, and the first N-type epitaxial layer serves as a buffer layer at the bottom of the super junction structure.

The width of the P-type column at the top of the super junction unit is smaller than that of the N-type column, and the sum of the widths of the P-type column and the N-type column, i.e., the pitch of the super junction unit, remains unchanged, so as to increase the volume of the N-type column and thereby reduce the specific on-resistance of the super junction device.

The N-type column with a larger top width of the super junction unit is composed of a second N-type epitaxial layer filled in the groove, and the P-type column with a smaller top width of the super junction unit is composed of a first P-type epitaxial layer between the grooves, and the first P-type epitaxial layer is formed on the first N-type epitaxial layer; the groove passes through the first P-type epitaxial layer and the bottom is in contact with the first N-type epitaxial layer.

The total amount of P-type impurities of the P-type column and the total amount of N-type impurities of the N-type column in the super junction unit match each other, and the doping concentration of the P-type column is higher than the doping concentration of the N-type column.

The top opening of the trench is set according to the top width of the N-type column with a larger top width of the super junction unit and is defined by photolithography to reduce the aspect ratio of the trench; the doping concentration of the second N-type epitaxial layer filling the trench is set according to the doping concentration of the N-type column with a smaller doping concentration of the super junction unit to reduce the variation of the impurity amount in the epitaxial filling process of the trench.

A further improvement is that the super junction device includes a plurality of super junction device units, each of which is formed on a corresponding super junction unit.

The super junction device unit includes a P-type body region formed on the top of the P-type column and extending into the N-type column.

A further improvement is that the thickness of the first N-type epitaxial layer is 5 microns to 20 microns, and the body diode characteristics of the device are adjusted by the thickness of the first N-type epitaxial layer. The thicker the first N-type epitaxial layer, the better the body diode characteristics of the device.

A further improvement is that the side surface of the trench is in a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.

A further improvement is that the side surface of the groove is in an inclined structure, the top width of the N-type column is greater than the bottom width, and the top width of the P-type column is less than the bottom width.

The structure in which the width of the N-type column gradually decreases from top to bottom reduces the volume of the N-type column and increases the doping concentration of the N-type column under the conditions that the step size of the super junction unit remains unchanged and the total amount of N-type doping remains unchanged, thereby reducing the high-temperature on-resistance of the super junction device.

A further improvement is that the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped;

The doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer are such that the P-type impurity amount of the P-type column and the N-type impurity amount of the N-type column at the middle position in depth of the super junction unit located at the bottom of the P-type well form an optimal match;

The amount of P-type impurities of the P-type column at each position above the middle position in depth of the super junction unit is less than the amount of N-type impurities of the N-type column;

The amount of P-type impurities of the P-type pillars at positions below a middle position in depth of the super junction unit is greater than the amount of N-type impurities of the N-type pillars.

A further improvement is that the first N-type epitaxial layer simultaneously forms a compensation structure for depleting the P-type impurities of the P-type column from the bottom, so as to compensate for the effect of the P-type impurity amount of the P-type column at the bottom of the super junction unit being greater than the N-type impurity amount of the N-type column on the reduction of the breakdown voltage.

The P-type body region simultaneously forms a compensation structure for depleting the N-type impurities of the N-type column from the top, so as to compensate for the effect of the P-type impurity amount of the P-type column at the top of the super junction unit being less than the N-type impurity amount of the N-type column on the reduction of breakdown voltage.

In order to solve the above technical problems, the present invention provides a method for manufacturing a super junction device, wherein the super junction device is an N-type device and is formed on a super junction structure; the super junction structure is formed by alternating P-type columns and N-type columns, and one P-type column and an adjacent N-type column form a super junction unit; the width of the P-type column at the top position of the super junction unit is smaller than the width of the N-type column and the sum of the widths of the P-type column and the N-type column remains unchanged, so as to increase the volume of the N-type column and thereby reduce the specific on-resistance of the super junction device; the super junction structure is manufactured by the following steps:

Step 1: Provide an N-type highly doped semiconductor substrate, and form a first N-type epitaxial layer on the semiconductor substrate; the first N-type epitaxial layer serves as a buffer layer at the bottom of the super junction structure.

Step 2: forming a first P-type epitaxial layer on the surface of the first N-type epitaxial layer.

Step three: forming a trench in the first P-type epitaxial layer by using a photolithography definition and etching process, wherein the trench passes through the first P-type epitaxial layer and the bottom of the trench contacts the first N-type epitaxial layer.

The top opening of the trench is set according to the top width of the N-type column having a larger top width of the super junction unit, so that the aspect ratio of the trench can be reduced.

Step 4: Fill the second N-type epitaxial layer in the trench, wherein the N-type column is composed of the second N-type epitaxial layer filled in the trench, and the P-type column is composed of the first P-type epitaxial layer between the trenches.

The total amount of P-type impurities of the P-type column in the super junction unit matches the total amount of N-type impurities of the N-type column, and the doping concentration of the P-type column is lower than the doping concentration of the N-type column; the doping concentration of the second N-type epitaxial layer filling the trench is set according to the doping concentration of the N-type column with a smaller doping concentration of the super junction unit to reduce the change in the impurity amount of the epitaxial filling process of the trench.

A further improvement is that in step three, before performing photolithography definition, it also includes the step of forming a hard mask layer on the surface of the first P-type epitaxial layer, in the etching process, the hard mask layer is first etched, and then the first P-type epitaxial layer is etched, and after the etching of step three is completed, a part of the thickness of the hard mask layer is removed; in step four, the epitaxial growth process of the second N-type epitaxial layer is first performed, and the second N-type epitaxial layer after growth is completed also extends to the outer surface of the groove; then a chemical mechanical polishing process is used to remove the second N-type epitaxial layer on the outer surface of the groove, and then the remaining hard mask layer is removed.

A further improvement is that the super junction device includes a plurality of super junction device units, each of which is formed on a corresponding super junction unit; after the super junction structure is formed, the following steps are further included:

forming a P-type body region, wherein the P-type body region is formed on the top of the P-type column and extends into the N-type column;

Forming a gate structure, a source region, an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a gate and a source;

The semiconductor substrate is thinned on the back side, a drain region is formed on the back side of the semiconductor substrate, and a back side metal layer is formed on the back side of the drain region.

A further improvement is that the thickness of the first N-type epitaxial layer is 5 microns to 20 microns, and the body diode characteristics of the device are adjusted by the thickness of the first N-type epitaxial layer. The thicker the first N-type epitaxial layer, the better the body diode characteristics of the device.

A further improvement is that the side surface of the trench is in a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.

A further improvement is that the side surface of the groove is in an inclined structure, the top width of the N-type column is greater than the bottom width, and the top width of the P-type column is less than the bottom width.

The structure in which the width of the N-type column gradually decreases from top to bottom reduces the volume of the N-type column and increases the doping concentration of the N-type column under the conditions that the super junction unit step remains unchanged and the total amount of N-type doping remains unchanged, thereby reducing the high-temperature on-resistance of the super junction device.

A further improvement is that the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.

The doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer are such that the P-type impurity amount of the P-type column and the N-type impurity amount of the N-type column at the middle position in depth of the super junction unit located at the bottom of the P-type well form an optimal match.

The amount of P-type impurities of the P-type pillar at each position above the middle position in depth of the super junction unit is less than the amount of N-type impurities of the N-type pillar.

The amount of P-type impurities of the P-type pillars at positions below a middle position in depth of the super junction unit is greater than the amount of N-type impurities of the N-type pillars.

A further improvement is that the first N-type epitaxial layer simultaneously forms a compensation structure for depleting the P-type impurities of the P-type column from the bottom, so as to compensate for the effect of the P-type impurity amount of the P-type column at the bottom of the super junction unit being greater than the N-type impurity amount of the N-type column on the reduction of the breakdown voltage.

The P-type body region simultaneously forms a compensation structure for depleting the N-type impurities of the N-type column from the top, so as to compensate for the effect of the P-type impurity amount of the P-type column at the top of the super junction unit being less than the N-type impurity amount of the N-type column on the reduction of breakdown voltage.

The present invention makes a special arrangement for the super junction structure based on the overall structure of the super junction device. According to the needs of the N-type device, the present invention increases the volume of the N-type column while keeping the widths of the P-type column and the N-type column unchanged in the step of the super junction unit, thereby reducing the specific on-resistance of the super junction device; on this basis, the present invention selects the top width of the N-type column with a larger width as the top opening width of the groove, and arranges the N-type column to be composed of an N-type epitaxial layer filled in the groove, namely, a second N-type epitaxial layer, and the epitaxial layer formed by the groove is a P-type epitaxial layer, namely, a first P-type epitaxial layer. Since the top opening width of the groove is increased, the aspect ratio of the groove is reduced, thereby reducing the difficulty of process control, including reducing the difficulty of controlling the etching, cleaning and filling processes of the groove.

Since in the present invention, the width of the P-type column at the top position of the super junction unit is smaller than the width of the N-type column, and the volume of the N-type column is larger than the volume of the P-type column, the present invention also simultaneously utilizes the characteristics that the doping concentration of the N-type column is lower than the doping concentration of the P-type column when the super junction unit charge matches and the volume of the N-type column is larger than the volume of the P-type column, and adopts the process of filling the groove with a second N-type epitaxial layer to realize the N-type column. Compared with the technical solution of forming the P-type column by filling the groove with a P-type epitaxial layer in the prior art, the present invention can reduce the doping concentration of the epitaxial layer filling the groove. Since the offset of the doping concentration of the epitaxial layer in the process of filling the groove changes according to the percentage offset, the present invention can reduce the doping concentration of the epitaxial layer filling the groove and thereby reduce the drift of the doping concentration of the epitaxial layer caused by the epitaxial layer filling the groove, thereby reducing the charge imbalance of the super junction unit, reducing the performance of the device such as the deviation of the breakdown voltage, and finally improving the consistency of the device.

In addition, the groove usually has a certain inclination angle, that is, the side of the groove is inclined, which is more conducive to the etching, cleaning and filling of the groove; at the same time, when the present invention applies the groove with the side inclined structure to the N-type column, since the top width of the N-type column, that is, the top opening width of the groove is directly defined by photolithography, and the width of the N-type column will gradually decrease from the top to the bottom, the N-type column of the present invention is compared with the N-type column composed of the N-type epitaxial layer between the grooves in the prior art. Under the condition that the top width of the two is the same, the volume of the N-type column of the present invention becomes smaller, and under the condition that the total amount of doping of the two is the same, the doping concentration of the N-type column of the present invention is higher, so compared with the N-type column of the prior art, the N-type column with a higher doping concentration of the present invention can reduce the high-temperature on-resistance of the super junction device; and usually in actual use, due to the existence of switching loss and conduction loss, the actual operating temperature of the device is not room temperature, but generally reaches 50°C to 120°C. After reducing the on-resistance of the device at high temperature, the present invention can reduce device loss, reduce the junction temperature of the device, and extend the life of the device.

In addition, when the groove is inclined, under the condition that the top widths of the N-type column and the P-type column remain unchanged, compared with the existing super junction structure in which the P-type column is formed by trench filling, the volume of the N-type column of the present invention will become smaller and the width will gradually decrease from top to bottom, while the volume of the P-type column will increase and the width will gradually increase from top to bottom. Under the condition that the total doping amount of the N-type column of the super junction unit, that is, the total doping amount of the P-type column remains unchanged, the present invention can increase the doping concentration of the N-type column and reduce the doping concentration of the P-type column at the same time compared with the existing structure. Combined with the change in the width of the N-type column and the P-type column, the present invention can simultaneously reduce the difference in the amount of impurities between the P-type column and the N-type column at the top and bottom positions of the super junction unit compared with the existing structure, so the present invention can improve the charge matching between the P-type column and the N-type column at the top and bottom positions of the super junction unit.

At the same time, the present invention can achieve that the amount of P-type impurities of the P-type column at the bottom position of the super junction unit is greater than the amount of N-type impurities of the N-type column. Since the first N-type epitaxial layer is arranged at the bottom of the super junction structure, the excess P-type impurities of the P-type column can be depleted from the bottom through the first N-type epitaxial layer, thereby compensating for the effect of the amount of P-type impurities of the P-type column at the bottom of the super junction unit being greater than the amount of N-type impurities of the N-type column on the reduction of the breakdown voltage, and finally improving the breakdown voltage of the device; on the contrary, in the existing structure, since the amount of P-type impurities of the P-type column at the bottom position of the super junction unit is less than the amount of N-type impurities of the N-type column, it is impossible to perform similar compensation of the present invention through the N-type epitaxial layer arranged at the bottom, and of course it is impossible to improve the breakdown voltage of the device.

At the same time, the present invention can achieve that the amount of P-type impurities in the P-type column at the bottom position of the super junction unit is less than the amount of N-type impurities in the N-type column. Since a P-type body region is usually formed at the top of the super junction structure, the excess N-type impurities at the top of the N-type column can be depleted through the P-type body region, thereby compensating for the effect of the amount of P-type impurities in the P-type column at the top of the super junction unit being less than the amount of N-type impurities in the N-type column on the reduction of the breakdown voltage, and finally improving the breakdown voltage of the device; on the contrary, in the existing structure, since the amount of P-type impurities in the P-type column at the top position of the super junction unit is greater than the amount of N-type impurities in the N-type column, similar compensation of the present invention cannot be performed through the P-type body region, and of course the breakdown voltage of the device cannot be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

FIG1 is a schematic diagram of the structure of an existing super junction device;

FIG2 is a schematic diagram of the structure of a super junction device according to a first embodiment of the present invention;

3A-3B are schematic diagrams of device structures in various steps of forming a super junction structure in a method for manufacturing a super junction device according to a first embodiment of the present invention;

4 is a curve showing on-resistance variation with temperature of the super junction device according to the first embodiment of the present invention and the conventional super junction device;

FIG. 5 is a curve showing the electric field intensity distribution in the longitudinal direction in the super junction unit of the super junction device according to the first embodiment of the present invention and the conventional super junction device.

DETAILED DESCRIPTION

Existing super junction devices:

In order to compare with the super junction device of the first embodiment of the present invention, the existing super junction device is first introduced. As shown in Figure 1, it is a structural schematic diagram of the existing super junction device; the existing super junction device includes a super junction structure formed by alternating arrangement of P-type columns 103 and N-type columns 101; the super junction device is an N-type device and is formed on the super junction structure; one P-type column 103 and an adjacent N-type column 101 constitute a super junction unit.

In the prior art, the P-type column 103 is composed of a P-type epitaxial layer filled in the trench 102. The N-type column 101 is composed of an N-type epitaxial layer 101 between the trenches 102. The trench 102 is located in the N-type epitaxial layer 101, and the N-type epitaxial layer 101 at the bottom of the trench 102 serves as a buffer layer.

The N-type epitaxial layer 101 is formed on an N-type highly doped semiconductor substrate 10 .

The width of the P-type column 103 at the top of the super junction unit is smaller than that of the N-type column 101 and the sum of the widths of the P-type column 103 and the N-type column 101 remains unchanged, so as to increase the volume of the N-type column 101 and thereby reduce the specific on-resistance of the super junction device.

The super junction device includes a plurality of super junction device units, and each of the super junction device units is formed on a corresponding super junction unit.

The super junction device unit includes a P-type body region 1 , which is formed on the top of the P-type column 103 and extends into the N-type column 101 .

It also includes: a gate structure, a source region 4, an interlayer film 7, a contact hole 8 and a front metal layer 9, and the front metal layer 9 is patterned to form a gate and a source.

In Fig. 1, the gate structure is a planar gate, which is formed by stacking a gate dielectric layer such as a gate oxide layer 2 and a polysilicon gate 3. Alternatively, the gate structure is a trench gate.

The drain region is formed by the semiconductor substrate 10 after the back side is thinned. Alternatively, the drain region is formed by an N+ ion implantation region formed in the semiconductor substrate 10 after the back side is thinned.

A back metal layer 11 is formed on the back side of the drain region. The back metal layer 11 forms a drain electrode.

Typically, a contact region 5 consisting of a P+ region is formed at the top of the contact hole 8 at the top of the source region 4 .

The surface of the body region 1 covered by the polysilicon gate 3 is used to form a channel. In order to reduce the on-resistance of the top region of the N-type column 101 between two adjacent body regions 1, a JFET implantation region 6 is usually formed.

The first embodiment of the super junction device of the present invention:

As shown in Figure 2, it is a schematic diagram of the structure of the super junction device of the first embodiment of the present invention; the super junction device of the first embodiment of the present invention includes a super junction structure formed by alternating P-type columns 202 and N-type columns 204; the super junction device is an N-type device and is formed on the super junction structure; one P-type column 202 and an adjacent N-type column 204 constitute a super junction unit.

The super junction structure is formed on the surface of the first N-type epitaxial layer 201, which is formed on an N-type highly doped semiconductor substrate 10, and the first N-type epitaxial layer 201 serves as a buffer layer at the bottom of the super junction structure. The semiconductor substrate 10 includes a silicon substrate.

The width of the P-type column 202 at the top of the super junction unit is smaller than that of the N-type column 204 and the sum of the widths of the P-type column 202 and the N-type column 204 remains unchanged, so as to increase the volume of the N-type column 204 and thus reduce the specific on-resistance of the super junction device.

The N-type column 204 with a larger top width of the super junction unit is composed of a second N-type epitaxial layer filled in the groove 203, and the P-type column 202 with a smaller top width of the super junction unit is composed of a first P-type epitaxial layer between the grooves 203, and the first P-type epitaxial layer is formed on the first N-type epitaxial layer 201; the groove 203 passes through the first P-type epitaxial layer and the bottom is in contact with the first N-type epitaxial layer 201.

The total amount of P-type impurities in the P-type column 202 and the total amount of N-type impurities in the N-type column 204 in the super junction unit match each other, and the doping concentration of the P-type column 202 is higher than the doping concentration of the N-type column 204 .

The top opening of the trench 203 is set according to the top width of the N-type column 204 having a larger top width of the super junction unit and is defined by photolithography to reduce the aspect ratio of the trench 203; the doping concentration of the second N-type epitaxial layer filling the trench 203 is set according to the doping concentration of the N-type column 204 having a smaller doping concentration of the super junction unit to reduce the variation in the impurity amount of the epitaxial filling process of the trench 203.

The super junction device includes a plurality of super junction device units, and each of the super junction device units is formed on a corresponding super junction unit.

The super junction device unit includes a P-type body region 1 , which is formed on the top of the P-type column 202 and extends into the N-type column 204 .

It also includes: a gate structure, a source region 4, an interlayer film 7, a contact hole 8 and a front metal layer 9, and the front metal layer 9 is patterned to form a gate and a source.

In Fig. 2, the gate structure is a planar gate, which is formed by stacking a gate dielectric layer such as a gate oxide layer 2 and a polysilicon gate 3. In other embodiments, the gate structure may also be a trench gate.

The drain region is formed by the semiconductor substrate 10 after the back side is thinned. In other embodiments, the drain region can also be formed by an N+ ion implantation region formed in the semiconductor substrate 10 after the back side is thinned.

A back metal layer 11 is formed on the back side of the drain region. The back metal layer 11 forms a drain electrode.

Typically, a contact region 5 consisting of a P+ region is formed at the top of the contact hole 8 at the top of the source region 4 .

The surface of the body region 1 covered by the polysilicon gate 3 is used to form a channel. In order to reduce the on-resistance of the top region of the N-type column 204 between two adjacent body regions 1, a JFET implantation region 6 is usually formed.

In the first embodiment of the present invention, the thickness of the first N-type epitaxial layer 201 is 5 microns to 20 microns. The body diode characteristics of the device are adjusted by the thickness of the first N-type epitaxial layer 201. The thicker the first N-type epitaxial layer 201 is, the better the body diode characteristics of the device are. The body diode is a parasitic diode formed between the body region 1 and the drift region. The drift region is composed of the N-type column 204 and the first N-type epitaxial layer 201.

The side surface of the groove 203 is in an inclined structure, the top width of the N-type column 204 is greater than the bottom width, and the top width of the P-type column 202 is less than the bottom width.

The structure in which the width of the N-type column 204 gradually decreases from top to bottom reduces the volume of the N-type column 204 and increases the doping concentration of the N-type column 204 under the conditions that the step size of the super junction unit remains unchanged and the total amount of N-type doping remains unchanged, thereby reducing the high-temperature on-resistance of the super junction device.

The first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.

The doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer are such that the P-type impurity amount of the P-type column 202 and the N-type impurity amount of the N-type column 204 at the middle position in depth of the super junction unit at the bottom of the P-type well form an optimal match.

The amount of P-type impurities in the P-type pillar 202 at each position above the middle position in depth of the super junction unit is less than the amount of N-type impurities in the N-type pillar 204 .

The amount of P-type impurities in the P-type pillar 202 at each position below the middle position in depth of the super junction unit is greater than the amount of N-type impurities in the N-type pillar 204 .

The first N-type epitaxial layer 201 simultaneously forms a compensation structure for depleting the P-type impurities of the P-type column 202 from the bottom, so as to compensate for the effect of the P-type impurity amount of the P-type column 202 at the bottom of the super junction unit being greater than the N-type impurity amount of the N-type column 204 on the reduction of the breakdown voltage.

The P-type body region 1 simultaneously forms a compensation structure for depleting the N-type impurities of the N-type column 204 from the top, so as to compensate for the effect of the P-type impurity amount of the P-type column 202 at the top of the super junction unit being less than the N-type impurity amount of the N-type column 204 on the breakdown voltage reduction.

The embodiment of the present invention makes special arrangements for the super junction structure based on the overall structure of the super junction device. According to the needs of the N-type device, the embodiment of the present invention increases the volume of the N-type column 204 while keeping the widths of the P-type column 202 and the N-type column 204 unchanged in the stepping of the super junction unit, thereby reducing the specific on-resistance of the super junction device. On this basis, the embodiment of the present invention selects the top width of the N-type column 204 with a larger width as the top opening width of the groove 203, and sets the N-type column 204 to be composed of an N-type epitaxial layer filled in the groove 203, namely, a second N-type epitaxial layer, while the epitaxial layer formed by the groove 203 is a P-type epitaxial layer, namely, a first P-type epitaxial layer. Since the top opening width of the groove 203 is increased, the aspect ratio of the groove 203 is reduced, thereby reducing the difficulty of process control, including reducing the difficulty of controlling the etching, cleaning and filling processes of the groove 203.

Since in the embodiment of the present invention, the width of the P-type column 202 at the top position of the super junction unit is smaller than the width of the N-type column 204, that is, the volume of the N-type column 204 is larger than the volume of the P-type column 202, the embodiment of the present invention also utilizes the characteristics that when the super junction unit charges are matched and the volume of the N-type column 204 is larger than the volume of the P-type column 202, the doping concentration of the N-type column 204 is lower than the doping concentration of the P-type column 202, and adopts the process of filling the groove 203 with the second N-type epitaxial layer to realize the N-type column 204, compared with the prior art that uses the P-type epitaxial layer to fill the groove The technical solution of forming the P-type column 202 through the groove 203 is adopted. The embodiment of the present invention can reduce the doping concentration of the epitaxial layer filling the groove 203. Since the deviation of the doping concentration of the epitaxial layer in the process of filling the groove 203 varies according to the deviation in percentage, the embodiment of the present invention can reduce the doping concentration of the epitaxial layer filling the groove 203 and thus reduce the drift of the doping concentration of the epitaxial layer caused by filling the groove 203 with the epitaxial layer, thereby reducing the charge imbalance of the super junction unit, reducing the deviation of the performance of the device such as the breakdown voltage, and finally improving the consistency of the device.

In addition, the groove 203 usually has a certain inclination angle, that is, the side of the groove 203 is inclined, which is more conducive to the etching, cleaning and filling of the groove 203; at the same time, when the embodiment of the present invention applies the groove 203 with the side inclined structure to the N-type column 204, since the top width of the N-type column 204, that is, the top opening width of the groove 203 is directly defined by photolithography, and the width of the N-type column 204 gradually decreases from the top to the bottom, the N-type column 204 of the embodiment of the present invention is compared with the N-type column 204 composed of the N-type epitaxial layer between the grooves 203 in the prior art. Under the condition of the same top width, the two The volume of the N-type column 204 of the embodiment of the present invention becomes smaller. At the same time, under the condition that the total amount of doping of the two is consistent, the doping concentration of the N-type column 204 of the embodiment of the present invention is higher. Therefore, compared with the N-type column 204 in the prior art, the N-type column 204 with a higher doping concentration in the embodiment of the present invention can reduce the high-temperature on-resistance of the super junction device; and usually in actual use, due to the existence of switching loss and conduction loss, the actual operating temperature of the device is not room temperature, but generally reaches 50°C to 120°C. After the embodiment of the present invention reduces the on-resistance of the device at high temperature, it can reduce device loss, reduce the junction temperature of the device, and extend the life of the device.

In addition, when the trench 203 is inclined, in the embodiment of the present invention, under the condition that the top widths of the N-type column 204 and the P-type column 202 remain unchanged, compared with the existing super junction structure in which the P-type column 202 is formed by filling the trench 203, the volume of the N-type column 204 in the embodiment of the present invention will become smaller and the width will gradually decrease from top to bottom, while the volume of the P-type column 202 will increase and the width will gradually increase from top to bottom. Under the condition that the total doping amount of the N-type column 204 of the super junction unit, that is, the total doping amount of the P-type column 202 remains unchanged, compared with the existing structure, the present invention can increase the doping concentration of the N-type column 204 and reduce the doping concentration of the P-type column 202 at the same time. Combined with the width changes of the N-type column 204 and the P-type column 202, compared with the existing structure, the embodiment of the present invention can simultaneously reduce the difference in the amount of impurities between the P-type column 202 and the N-type column 204 at the top and bottom positions of the super junction unit. Therefore, the embodiment of the present invention can improve the charge matching between the P-type column 202 and the N-type column 204 at the top and bottom positions of the super junction unit.

At the same time, the embodiment of the present invention can achieve that the P-type impurity amount of the P-type column 202 at the bottom position of the super junction unit is greater than the N-type impurity amount of the N-type column 204. Since the first N-type epitaxial layer 201 is arranged at the bottom of the super junction structure, the excess P-type impurities of the P-type column 202 can be depleted from the bottom through the first N-type epitaxial layer 201, thereby compensating for the effect of the P-type impurity amount of the P-type column 202 at the bottom of the super junction unit being greater than the N-type impurity amount of the N-type column 204 on the reduction of the breakdown voltage, and finally improving the breakdown voltage of the device; on the contrary, in the existing structure, since the P-type impurity amount of the P-type column 202 at the bottom position of the super junction unit is less than the N-type impurity amount of the N-type column 204, it is impossible to perform similar compensation as in the embodiment of the present invention through the N-type epitaxial layer arranged at the bottom, and of course it is impossible to improve the breakdown voltage of the device.

At the same time, the embodiment of the present invention can achieve that the P-type impurity amount of the P-type column 202 at the top position of the super junction unit is less than the N-type impurity amount of the N-type column 204. Since a P-type body region 1 is usually formed at the top of the super junction structure, the excess N-type impurities at the top of the N-type column 204 can be depleted through the P-type body region 1, thereby compensating for the effect of the P-type impurity amount of the P-type column 202 at the top of the super junction unit being less than the N-type impurity amount of the N-type column 204 on the reduction of the breakdown voltage, and finally improving the breakdown voltage of the device; on the contrary, in the existing structure, since the P-type impurity amount of the P-type column 202 at the top position of the super junction unit is greater than the N-type impurity amount of the N-type column 204, it is impossible to perform similar compensation as in the embodiment of the present invention through the P-type body region 1, and of course it is impossible to improve the breakdown voltage of the device.

The difference between the super junction device in the first embodiment of the present invention and the existing super junction device is described below with a specific parameter:

The conventional super junction device shown in FIG. 1 and the super junction device of the first embodiment of the present invention shown in FIG. 2 differ only in the super junction structure. The other structures are the same and are indicated by the same reference numerals.

In the first embodiment of the present invention, a 600V high-voltage NMOSFET is used as an example and has the following parameters:

The doping concentration of the semiconductor substrate 10 is higher than 1E19 cm ⁻³ , and the corresponding resistivity is, for example, 0.001 ohm·cm to 0.003 ohm·cm, and the thickness is about 725 micrometers.

The thickness of the first N-type epitaxial layer 201 is about 5 microns to 20 microns. A thick buffer layer can improve the body diode performance of the device and enhance the device's ability to resist current surge (EAS), while a thin buffer layer can reduce the device's specific on-resistance (Rsp).

In device design, the P-type body region 1 is usually composed of a P-type well, the depth of the P-type body region 1 is 2 microns, the thickness of the first P-type epitaxial layer, i.e., the P-type column 202, is 40 microns, the depth of the groove 203 is equal to 40 microns, or deeper than 40 microns, and the total amount of impurities in the N-type region, i.e., the N-type column 204, is kept consistent in the design to maintain the same Rsp. The side inclination angle of the groove 203 is 88.6 degrees to 89 degrees, and it is assumed here that the inclination angle of the groove 203 is 88.6 degrees, the top width of the groove 203 is set to 5 microns, the top width of the P-type column 202 is 4 microns, and the step of the super junction unit is 9 microns.

The thickness from line A1A2 to line C1C2 in FIG. 2 is 40 microns; the depth of the P-type body region 1 corresponds to the distance from line B1B2 to line C1C2, which is 2 microns; the thickness of the P-type column 202 that withstands voltage is the thickness from line A1A2 to line B1B2, which is 38 microns.

The concentrations of the N-type column 204 and the P-type column 202 are both single, and the P-type impurities obtained by multiplying the concentration of the P-type column 202 by the width and the N-type impurities obtained by multiplying the concentration of the N-type column 204 by the width at the center line from line A1A2 to line B1B2 are kept equal. Because the groove 203 is wide at the top and narrow at the bottom, the P-N balance on all parallel lines cannot be guaranteed. The charge balance on the center line is maintained, and the balance of the P-type impurities and the N-type impurities in total is maintained. P-N balance means that the doping amounts of the P-type column and the N-type column are equal.

The above setup is also applicable to existing superjunction devices.

In the device of the first embodiment of the present invention: the groove 203 corresponding to the N-type column 204 is an inclined groove, the top width of the groove 203 is set to 5 microns, the width of the N-type column 204 is 3.97 microns on the midline from line A1A2 to line B1B2, and the width of the bottom groove is 3.05 microns.

The top width of the P-type column 202 is 4 micrometers, the width of the P-type column 202 on the middle line from line A1A2 to line B1B2 is 5.03 micrometers, and the bottom width of the P-type column 202 is 5.95 micrometers.

Assuming that the N-type pillar 204 is uniformly doped and the doping concentration is 4E15 cm ⁻³ , the total amount of N-type impurities in the N-type pillar 204 from line A1A2 to line B1B2 is 6.04E9 cm ⁻¹ .

The total amount of P-type impurities in the P-type column 202 is also 6.04E9cm ^-1 at the optimal balance. The P-type impurities in the P-type column 202 are also uniform, so the optimal concentration of the P-type impurities in the P-type column 202 is 3.16E15cm ^-3 . That is, on the horizontal line from line A1A2 to the midline of line B1B2, the PN charge reaches equilibrium.

In the portion upward from the median line, the P-type impurities are less than the N-type impurities on the same horizontal line, and in the portion below the median line, the P-type impurities are more than the N-type impurities. At the bottom of the trench 203, i.e., the horizontal line of line A1A2, the P-type impurities, i.e., the product of the concentration and the width of the bottom of the trench, are 6.62E11cm ^-2 more than the N-type impurities. At the top of the trench 203 where it connects with the P-type body region 1, i.e., the horizontal line of line B1B2, the effects of the ion implantation of the P-type body region 1 and the ion implantation of the JFET implantation region 6 are not considered here, the P-type impurities are less than the N-type impurities, and on the B1B2 line, the P-type impurities are 6.65E11cm ^-2 less than the N-type impurities.

In the existing super junction device shown in Figure 1: the top width of the P-type column 103 is 4 microns, the corresponding groove 102 is set as an inclined groove, the top width of the groove 102 is set to 4 microns, and on the midline from line A1A2 to line B1B2, the width of the P-type column 103 is 2.97 microns, and the width of the bottom groove 102 is 2.05 microns.

The top width of the N-type column 101 is 5 micrometers, the width of the N-type column 101 on the middle line from line A1A2 to line B1B2 is 6.03 micrometers, and the bottom width of the N-type column 101 is 6.95 micrometers.

Assuming the impurity concentration of the N-type column 101 is 2.64E15 cm ⁻³ , the total amount of N-type impurities of the N-type column 101 from line A1A2 to line B1B2 is 6.04E9 cm ⁻¹ , and the total amount of P-type impurities of the P-type column 103 is also 6.04E9 cm ⁻¹ at optimal balance.

The P-type impurities of the P-type column 103 are also uniform, so the optimal concentration of the P-type impurities of the P-type column 103 is 5.35E15cm ^-3 . That is, on the horizontal line from line A1A2 to the midline of line B1B2, the PN charge reaches a balance, and on the part upward from the midline, the P-type impurities are more than the N-type impurities on the same horizontal line, and on the part below the midline, the P-type impurities are less than the N-type impurities. At the bottom of the trench 102, i.e., the horizontal line corresponding to line A1A2, the P-type impurities, i.e., the product of the concentration and the width of the bottom of the trench, are 7.37E11cm ^-2 less than the N-type impurities; at the top of the trench 102, i.e., the area connected to the P-type body region 1, i.e., the horizontal line of line B1B2, the influence of the ion implantation of the P-type body region 1 and the ion implantation of the JFET implantation region 6 are not considered here, the P-type impurities are more than the N-type impurities, and on the B1B2 line, the P-type impurities are 7.43E11/cm2 more than the N-type impurities. Summarizing the above data, the following Table 1 is obtained.

Table 1

It can be seen that since the super junction device of the first embodiment of the present invention and the existing super junction device maintain the same pitch, ie, 9 micrometers and the same total amount of N-type impurities in one pitch of 6.04E9 cm ^-1 , their Rsp are kept consistent at room temperature.

Since the N-type impurity concentration of the super junction device of the first embodiment of the present invention is 4E15cm ^-3 which is significantly higher than 2.64E15cm ^-3 of the prior art, the increase of Rsp of the super junction device of the first embodiment of the present invention as the temperature rises is lower than that of the prior art super junction device, so that the high temperature on-resistance of the super junction device of the first embodiment of the present invention is lower than that of the prior art super junction device, thereby improving the high temperature applicability of the device. As shown in FIG4 , it is a curve of on-resistance variation with temperature of the super junction device of the first embodiment of the present invention and the prior art super junction device, curve 301 is a curve of on-resistance variation with temperature of the prior art super junction device, and curve 302 is a curve of on-resistance variation with temperature of the super junction device of the first embodiment of the present invention, and it can be seen that the on-resistance of the super junction device of the first embodiment of the present invention is lower at high temperature.

Considering only the case of epitaxial deposition and epitaxial filling of the trenches, that is, one of the N-type column and the P-type column is composed of a deposited epitaxial layer, and the other is composed of an epitaxial layer filled in a trench formed in the deposited epitaxial layer. Under the condition that the P and N impurities are set to remain completely balanced in the PN column, i.e., the midline of the super junction unit, the amount of P-type impurities exceeding N-type impurities at the bottom of the super junction device of the first embodiment of the present invention is less than the amount of P-type impurities exceeding N-type impurities at the bottom of the existing super junction device. In particular, under the conditions of the super junction device of the first embodiment of the present invention, the portion with more P-type impurities at the bottom can be balanced by the impurities of the N-type buffer layer, i.e., the first N-type epitaxy 201, under the P-type column 202, thereby improving the breakdown voltage of the device.

On the top horizontal line, i.e., line B1B2, when only epitaxial deposition and epitaxial filling of the trench are considered, the amount of P-type impurities less than N-type impurities in the top superjunction device of the first embodiment of the present invention is less than the amount of P-type impurities more than N-type impurities in the existing superjunction device. In particular, under the conditions of the superjunction device of the first embodiment of the present invention, the portion with less P-type impurities in the top can be supplemented by impurities in the P-type well, i.e., the P-type body region 1, thereby increasing the breakdown voltage of the device. This relationship is shown in FIG5 , which is a vertical electric field intensity distribution curve in the superjunction unit of the superjunction device of the first embodiment of the present invention and the existing superjunction device. Curve 303 corresponds to the vertical electric field intensity distribution curve in the superjunction unit of the existing superjunction device, and curve 304 corresponds to the vertical electric field intensity distribution curve in the superjunction unit of the superjunction device of the first embodiment of the present invention. It can be seen that at line A1A2 and line B1B2, the electric field intensity of curve 304 is improved, so the breakdown voltage can be increased.

The super junction device of the first embodiment of the present invention obtains the same Rsp and higher BVds, and the filled N-type impurity concentration of 4E15cm ^-3 is significantly lower than the P-type impurity filling concentration of 5.35E15cm ^-3 of the existing super junction device. In this way, when the concentration of the filled impurities changes by the same percentage, the impurity amount of the super junction device of the first embodiment of the present invention changes little, which is beneficial to the consistency of the device. This is because in the process of filling the doped epitaxial in the trench, the control of its concentration is more difficult than the epitaxial deposition process on the plane, and the process margin of the trench filling process is more important.

The second embodiment of the super junction device of the present invention:

The difference between the super junction device of the first embodiment of the present invention and the super junction device of the second embodiment of the present invention is that the side surface of the trench 203 in the super junction device of the second embodiment of the present invention is a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.

The following is a specific parameter to illustrate the difference between the super junction device in the second embodiment of the present invention and the existing super junction device with vertical trench sides:

In existing superjunction devices, the top width of the P-type column is 4 microns, the top width of the N-type column is 5 microns, the step of the superjunction unit is 9 microns, the concentration of the planar deposited N epitaxial layer, i.e. the epitaxial layer corresponding to the N-type column, is 3.18e15 cm ^-3 , and the concentration of the P-type impurities filled in the trench, i.e. the P-type column, is 3.97E15 cm ^-3 .

In the second embodiment of the super junction device of the present invention, the top width of the P-type column is 4 microns, the top width of the N-type column is 5 microns, the step of the super junction unit is 9 microns, the concentration of the planar deposited P epitaxial layer, i.e., the P-type column, is 3.97e15 cm ^-3 , and the concentration of the P-type impurities filled in the trench, i.e., the P-type column, is 3.18E15 cm ^-3 .

It can be seen that the concentration of impurities in the trench filling of the super junction device of the second embodiment of the present invention is lower than that of the existing super junction device. This is because the control of impurity concentration in the trench filling is significantly higher than the concentration control of impurities deposited on a plane. Therefore, the existing super junction device reduces the difficulty of manufacturing technology or improves the consistency of the device.

The manufacturing method of the super junction device according to the first embodiment of the present invention:

As shown in FIGS. 3A to 3B , it is a schematic diagram of the device structure in each step of forming a super junction structure in the manufacturing method of the super junction device of the first embodiment of the present invention; in the manufacturing method of the super junction device of the first embodiment of the present invention, the super junction device is an N-type device and is formed on the super junction structure; the super junction structure is formed by alternating P-type columns 202 and N-type columns 204, and one P-type column 202 and an adjacent N-type column 204 form a super junction unit; the width of the P-type column 202 at the top position of the super junction unit is smaller than the width of the N-type column 204 and the sum of the widths of the P-type column 202 and the N-type column 204 remains unchanged, so as to increase the volume of the N-type column 204 and thereby reduce the specific on-resistance of the super junction device; the super junction structure is manufactured by the following steps:

Step 1: As shown in FIG. 3A , provide an N-type highly doped semiconductor substrate 10 , and form a first N-type epitaxial layer 201 on the semiconductor substrate 10 ; the first N-type epitaxial layer 201 serves as a buffer layer at the bottom of the super junction structure.

Step 2: As shown in FIG. 3A , a first P-type epitaxial layer is formed on the surface of the first N-type epitaxial layer 201 .

Step 3: As shown in FIG. 3A , a trench 203 is formed in the first P-type epitaxial layer by using a photolithography definition and etching process. The trench 203 passes through the first P-type epitaxial layer and the bottom thereof contacts the first N-type epitaxial layer 201 .

The top opening of the trench 203 is set according to the top width of the N-type column 204 which has a larger top width of the super junction unit, so that the aspect ratio of the trench 203 can be reduced.

In step three, before performing photolithography definition, it also includes the step of forming a hard mask layer 205 on the surface of the first P-type epitaxial layer. In the etching process, the hard mask layer 205 is first etched, and then the first P-type epitaxial layer is etched. After the etching in step three is completed, a partial thickness of the hard mask layer 205 is removed.

Preferably, the hard mask layer 205 is formed by stacking a first oxide film, a second nitride film and a third oxide film.

After the trench 203 etching process is completed, the third oxide film and the second nitride film are removed by a dry or wet etching process.

Step 4, as shown in FIG. 3B , the second N-type epitaxial layer is filled in the trench 203 , the N-type column 204 is composed of the second N-type epitaxial layer filled in the trench 203 , and the P-type column 202 is composed of the first P-type epitaxial layer between the trenches 203 .

In step four, the epitaxial growth process of the second N-type epitaxial layer is first performed, and the second N-type epitaxial layer after growth is extended to the outer surface of the groove 203; then, the second N-type epitaxial layer on the outer surface of the groove 203 is removed by a chemical mechanical polishing process, and then the remaining hard mask layer 205, i.e., the first oxide film, is removed.

The total amount of P-type impurities of the P-type column 202 in the super junction unit matches the total amount of N-type impurities of the N-type column 204, and the doping concentration of the P-type column 202 is lower than the doping concentration of the N-type column 204; the doping concentration of the second N-type epitaxial layer filling the trench 203 is set according to the doping concentration of the N-type column 204 with a smaller doping concentration of the super junction unit to reduce the change in the impurity amount of the epitaxial filling process of the trench 203.

As shown in FIG. 2 , the super junction device includes a plurality of super junction device units, each of which is formed on a corresponding super junction unit; after the super junction structure is formed, the following steps are further included:

forming a P-type body region 1, wherein the P-type body region 1 is formed on the top of the P-type column 202 and extends into the N-type column 204;

A gate structure, a source region 4, an interlayer film 7, a contact hole 8 and a front metal layer 9 are formed, and the front metal layer 9 is patterned to form a gate and a source.

The semiconductor substrate 10 is thinned on the back side, a drain region is formed on the back side of the semiconductor substrate 10 , and a back side metal layer 11 is formed on the back side of the drain region.

The gate structure is a planar gate, which is formed by stacking a gate dielectric layer such as a gate oxide layer 2 and a polysilicon gate 3. In other embodiments and methods, the gate structure can also be a trench gate.

The drain region is formed by the semiconductor substrate 10 after the back side is thinned. In other embodiments, the drain region can also be formed by an N+ ion implantation region formed in the semiconductor substrate 10 after the back side is thinned.

Typically, a contact region 5 consisting of a P+ region is formed at the top of the contact hole 8 at the top of the source region 4 , and the contact region 5 is formed by ion implantation after the opening of the contact hole 8 is opened and before metal filling.

The surface of the body region 1 covered by the polysilicon gate 3 is used to form a channel. In order to reduce the on-resistance of the top region of the N-type column 204 between two adjacent body regions 1, a JFET implantation region 6 is usually formed.

The thickness of the first N-type epitaxial layer 201 is 5 microns to 20 microns. The body diode characteristics of the device are adjusted by the thickness of the first N-type epitaxial layer 201. The thicker the first N-type epitaxial layer 201 is, the better the body diode characteristics of the device are.

In the method of the embodiment of the present invention, the side surface of the groove 203 is an inclined structure, the top width of the N-type column 204 is greater than the bottom width, and the top width of the P-type column 202 is less than the bottom width.

The structure in which the width of the N-type column 204 gradually decreases from top to bottom reduces the volume of the N-type column 204 and increases the doping concentration of the N-type column 204 under the condition that the super junction unit step remains unchanged and the total amount of N-type doping remains unchanged, thereby reducing the high-temperature on-resistance of the super junction device.

The first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.

The doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer are such that the P-type impurity amount of the P-type column 202 and the N-type impurity amount of the N-type column 204 at the middle position in depth of the super junction unit at the bottom of the P-type well form an optimal match.

The amount of P-type impurities in the P-type pillar 202 at each position above the middle position in depth of the super junction unit is less than the amount of N-type impurities in the N-type pillar 204 .

The amount of P-type impurities in the P-type pillar 202 at each position below the middle position in depth of the super junction unit is greater than the amount of N-type impurities in the N-type pillar 204 .

The first N-type epitaxial layer 201 simultaneously forms a compensation structure for depleting the P-type impurities of the P-type column 202 from the bottom, so as to compensate for the effect of the P-type impurity amount of the P-type column 202 at the bottom of the super junction unit being greater than the N-type impurity amount of the N-type column 204 on the reduction of the breakdown voltage.

The P-type body region 1 simultaneously forms a compensation structure for depleting the N-type impurities of the N-type column 204 from the top, so as to compensate for the effect of the P-type impurity amount of the P-type column 202 at the top of the super junction unit being less than the N-type impurity amount of the N-type column 204 on the breakdown voltage reduction.

The second embodiment of the present invention is a method for manufacturing a super junction device:

The difference between the manufacturing method of the super junction device in the first embodiment of the present invention and the manufacturing method of the super junction device in the second embodiment of the present invention is that the side surface of the groove 203 in the manufacturing method of the super junction device in the second embodiment of the present invention is a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.

The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims (7)

1. A super junction device, characterized in that it comprises a super junction structure formed by alternating arrangement of P-type columns and N-type columns; the super junction device is an N-type device and is formed on the super junction structure; one of the P-type columns and one of the adjacent N-type columns constitute a super junction unit; The super junction structure is formed above the surface of a first N-type epitaxial layer, the first N-type epitaxial layer is formed on an N-type highly doped semiconductor substrate, and the first N-type epitaxial layer serves as a buffer layer at the bottom of the super junction structure; The width of the P-type column at the top position of the super junction unit is smaller than the width of the N-type column, and the sum of the widths of the P-type column and the N-type column remains unchanged, so as to increase the volume of the N-type column and thus reduce the specific on-resistance of the super junction device; The N-type column with a larger top width of the super junction unit is composed of a second N-type epitaxial layer filled in the trench, and the P-type column with a smaller top width of the super junction unit is composed of a first P-type epitaxial layer between the trenches, wherein the first P-type epitaxial layer is formed on the first N-type epitaxial layer; the trench passes through the first P-type epitaxial layer and the bottom is in contact with the first N-type epitaxial layer; The total amount of P-type impurities of the P-type column in the super junction unit matches the total amount of N-type impurities of the N-type column, and the doping concentration of the P-type column is higher than the doping concentration of the N-type column; The top opening of the trench is set according to the top width of the N-type column with a larger top width of the super junction unit and is defined by photolithography to reduce the aspect ratio of the trench; the doping concentration of the second N-type epitaxial layer filling the trench is set according to the doping concentration of the N-type column with a smaller doping concentration of the super junction unit to reduce the change of impurity amount in the epitaxial filling process of the trench; The side surface of the groove is in an inclined structure, the top width of the N-type column is greater than the bottom width, and the top width of the P-type column is less than the bottom width; The structure in which the width of the N-type column gradually decreases from the top to the bottom reduces the volume of the N-type column and increases the doping concentration of the N-type column under the condition that the step size of the super junction unit remains unchanged and the total amount of N-type doping remains unchanged, so as to reduce the high temperature on-resistance of the super junction device; The first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped; The doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer are such that the P-type impurity amount of the P-type column and the N-type impurity amount of the N-type column at the middle position in depth of the super junction unit located at the bottom of the P-type body region form an optimal match; the P-type body region is formed at the top of the P-type column and extends into the N-type column; The amount of P-type impurities of the P-type column at each position above the middle position in depth of the super junction unit is less than the amount of N-type impurities of the N-type column; The P-type impurity amount of the P-type column at each position below the middle position in depth of the super junction unit is greater than the N-type impurity amount of the N-type column; The first N-type epitaxial layer simultaneously forms a compensation structure for depleting the P-type impurities of the P-type column from the bottom, so as to compensate for the effect of the P-type impurity amount of the P-type column at the bottom of the super junction unit being greater than the N-type impurity amount of the N-type column on the reduction of the breakdown voltage; The P-type body region simultaneously forms a compensation structure for depleting the N-type impurities of the N-type column from the top, so as to compensate for the effect of the P-type impurity amount of the P-type column at the top of the super junction unit being less than the N-type impurity amount of the N-type column on the reduction of breakdown voltage. 2. The super junction device according to claim 1, characterized in that: the super junction device comprises a plurality of super junction device units, each of the super junction device units is formed on a corresponding super junction unit; The super junction device unit includes the P-type body region. 3. The super junction device as described in claim 2 is characterized in that: the thickness of the first N-type epitaxial layer is 5 microns to 20 microns, and the body diode characteristics of the device are adjusted by the thickness of the first N-type epitaxial layer. The thicker the thickness of the first N-type epitaxial layer, the better the body diode characteristics of the device. 4. A method for manufacturing a super junction device, characterized in that the super junction device is an N-type device and is formed on a super junction structure; the super junction structure is formed by alternating P-type columns and N-type columns, and one P-type column and an adjacent N-type column form a super junction unit; the width of the P-type column at the top position of the super junction unit is smaller than the width of the N-type column and the sum of the widths of the P-type column and the N-type column remains unchanged, so as to increase the volume of the N-type column and thereby reduce the specific on-resistance of the super junction device; the super junction structure is manufactured by the following steps: Step 1: providing an N-type highly doped semiconductor substrate, and forming a first N-type epitaxial layer on the semiconductor substrate; the first N-type epitaxial layer serves as a buffer layer at the bottom of the super junction structure; Step 2: forming a first P-type epitaxial layer on the surface of the first N-type epitaxial layer; Step 3: forming a trench in the first P-type epitaxial layer by using a photolithography definition and etching process, wherein the trench passes through the first P-type epitaxial layer and the bottom thereof contacts the first N-type epitaxial layer; The top opening of the trench is set according to the top width of the N-type column having a larger top width of the super junction unit, so as to reduce the aspect ratio of the trench; Step 4: Filling the second N-type epitaxial layer in the trench, wherein the N-type column is composed of the second N-type epitaxial layer filled in the trench, and the P-type column is composed of the first P-type epitaxial layer between the trenches; The total amount of P-type impurities of the P-type column in the super junction unit matches the total amount of N-type impurities of the N-type column, and the doping concentration of the P-type column is higher than the doping concentration of the N-type column; the doping concentration of the second N-type epitaxial layer filling the trench is set according to the doping concentration of the N-type column with a smaller doping concentration of the super junction unit to reduce the change of impurity amount in the epitaxial filling process of the trench; The side surface of the groove is in an inclined structure, the top width of the N-type column is greater than the bottom width, and the top width of the P-type column is less than the bottom width; The structure in which the width of the N-type column gradually decreases from the top to the bottom reduces the volume of the N-type column and increases the doping concentration of the N-type column under the condition that the super junction unit step remains unchanged and the total amount of N-type doping remains unchanged, so as to reduce the high temperature on-resistance of the super junction device; The first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped; The doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer are such that the P-type impurity amount of the P-type column and the N-type impurity amount of the N-type column at the middle position in depth of the super junction unit located at the bottom of the P-type body region form an optimal match; the P-type body region is formed at the top of the P-type column and extends into the N-type column; The amount of P-type impurities of the P-type column at each position above the middle position in depth of the super junction unit is less than the amount of N-type impurities of the N-type column; The P-type impurity amount of the P-type column at each position below the middle position in depth of the super junction unit is greater than the N-type impurity amount of the N-type column; The first N-type epitaxial layer simultaneously forms a compensation structure for depleting the P-type impurities of the P-type column from the bottom, so as to compensate for the effect of the P-type impurity amount of the P-type column at the bottom of the super junction unit being greater than the N-type impurity amount of the N-type column on the reduction of the breakdown voltage; The P-type body region simultaneously forms a compensation structure for depleting the N-type impurities of the N-type column from the top, so as to compensate for the effect of the P-type impurity amount of the P-type column at the top of the super junction unit being less than the N-type impurity amount of the N-type column on the reduction of breakdown voltage. 5. The manufacturing method of the super junction device as described in claim 4 is characterized in that: in step three, before performing photolithography definition, it also includes the step of forming a hard mask layer on the surface of the first P-type epitaxial layer, in the etching process, the hard mask layer is first etched, and then the first P-type epitaxial layer is etched, and after the etching of step three is completed, a part of the thickness of the hard mask layer is removed; in step four, the epitaxial growth process of the second N-type epitaxial layer is first performed, and the second N-type epitaxial layer after growth is completed also extends to the outer surface of the groove; then the chemical mechanical polishing process is used to remove the second N-type epitaxial layer on the outer surface of the groove, and then the remaining hard mask layer is removed. 6. The manufacturing method of the super junction device according to claim 4, characterized in that: the super junction device comprises a plurality of super junction device units, each of the super junction device units is formed on the corresponding super junction unit; after the super junction structure is formed, the method further comprises the following steps: The P-type body region is formed. 7. The method for manufacturing a super junction device as described in claim 6 is characterized in that: the thickness of the first N-type epitaxial layer is 5 microns to 20 microns, and the body diode characteristics of the device are adjusted by the thickness of the first N-type epitaxial layer. The thicker the thickness of the first N-type epitaxial layer, the better the body diode characteristics of the device.