CN112768446B - Integrated chip and preparation method thereof - Google Patents
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- CN112768446B CN112768446B CN201910998781.0A CN201910998781A CN112768446B CN 112768446 B CN112768446 B CN 112768446B CN 201910998781 A CN201910998781 A CN 201910998781A CN 112768446 B CN112768446 B CN 112768446B
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- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 142
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims abstract description 71
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 354
- 230000000149 penetrating effect Effects 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 13
- 229910002601 GaN Inorganic materials 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D88/00—Three-dimensional [3D] integrated devices
- H10D88/101—Three-dimensional [3D] integrated devices comprising components on opposite major surfaces of semiconductor substrates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明涉及芯片技术领域，公开了一种集成芯片及其制备方法，该集成芯片，包括：晶圆层，晶圆层包括第一单晶硅层、第二单晶硅层以及中间的二氧化硅介质层，第一单晶硅层形成有第一芯片；还包括依次形成于第一单晶硅层上的第一介质层、第一金属部，第一金属部与对应的第一芯片的电连接部之间通过过孔电性连接；还包括依次形成于第二单晶硅层上的第二芯片器件层、第二介质层、第二金属部，第二芯片器件层形成第二芯片，第二金属部与对应的第二芯片的电连接部之间通过过孔电性连接；第二金属部通过过孔与对应的第一金属部电性连接。该集成芯片将相同或不同的多个芯片集成于晶圆的两侧，简化了芯片之间的连接且体积小。
The present invention relates to the field of chip technology, and discloses an integrated chip and a preparation method thereof, the integrated chip comprising: a wafer layer, the wafer layer comprising a first single crystal silicon layer, a second single crystal silicon layer and a silicon dioxide dielectric layer in between, the first single crystal silicon layer forming a first chip; further comprising a first dielectric layer and a first metal part sequentially formed on the first single crystal silicon layer, the first metal part being electrically connected to the corresponding electrical connection part of the first chip through a via hole; further comprising a second chip device layer, a second dielectric layer, and a second metal part sequentially formed on the second single crystal silicon layer, the second chip device layer forming a second chip, the second metal part being electrically connected to the corresponding electrical connection part of the second chip through a via hole; the second metal part being electrically connected to the corresponding first metal part through a via hole. The integrated chip integrates multiple identical or different chips on both sides of the wafer, simplifies the connection between chips and is small in size.
Description
Technical Field
The invention relates to the technical field of chips, in particular to an integrated chip and a preparation method thereof.
Background
With the rapid development of wide bandgap semiconductor material (i.e., third generation semiconductor material) devices, manufacturing processes and device physics represented by SiC and GaN, siC and GaN-based power electronic devices gradually become important development directions of power semiconductor devices, and have gradually entered market applications, in which devices such as gallium nitride schottky barrier diode (Schottky Barrier Diode, SBD), gallium nitride high electron mobility transistor (High Electron Mobility Transistor, HEMT), silicon carbide junction barrier diode JBS, silicon carbide field effect transistor MOSFET, and the like are mainly used, because the third generation semiconductor power devices have characteristics of high breakdown electric field, high saturated electron velocity, high thermal conductivity, high electron density, high mobility, low power loss, and the like, and are widely used in the fields of power electronics, new energy, and the like.
At present, a power chip and a device used by an Intelligent Power Module (IPM) are mainly silicon devices, a few of the power chip and the device are silicon device mixed GaN devices or SiC devices, and the packaging design of the module is still based on the structure of a traditional silicon device, and the devices are connected through a wire bonding mode, so that the Intelligent Power Module (IPM) has the advantages of large volume, more packaging leads and incapacity of effectively playing the advantages of a third-generation semiconductor power device.
Disclosure of Invention
The invention provides an integrated chip and a preparation method thereof, wherein the integrated chip integrates a plurality of chips on two sides of a wafer, so that the connection between the chips is simplified and the volume is small.
In order to achieve the above purpose, the present invention provides the following technical solutions:
An integrated chip, comprising:
the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide medium layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer, the first monocrystalline silicon layer comprises a groove area which divides the first monocrystalline silicon layer into a middle area and an edge area, and a first chip is formed at the position of the first monocrystalline silicon layer in the middle area;
the first dielectric layer is formed on one side of the first monocrystalline silicon layer, which is away from the second monocrystalline silicon layer;
the first metal part is formed on the first dielectric layer and deviates from the first monocrystalline silicon layer, and the first metal part is electrically connected with the corresponding electric connection part of the first chip through a via hole;
the second chip device layer is formed on one side of the second monocrystalline silicon layer, which is away from the first monocrystalline silicon layer, and the second chip device layer forms a second chip;
The second dielectric layer is formed on one side of the second chip device layer, which is away from the second monocrystalline silicon layer;
The second metal part is electrically connected with the corresponding electric connection part of the second chip through a via hole, and is electrically connected with the corresponding first metal part through a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer.
The integrated chip comprises a wafer layer, wherein the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide medium layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer, the first monocrystalline silicon layer comprises a groove area which divides the first monocrystalline silicon layer into a middle area and an edge area, a first chip is formed at the position of the first monocrystalline silicon layer in the middle area, the groove area is positioned in the peripheral area of the first chip, and the electrical isolation of the first chip is realized; the integrated chip further comprises a second chip device layer formed on one side of the second monocrystalline silicon layer, a second dielectric layer formed on one side of the second chip device layer, and a second metal part formed on one side of the second dielectric layer, wherein the second chip device layer forms a second chip, the second metal parts are electrically connected with the corresponding electric connection parts of the second chip through the through holes, namely, the second chips are electrically connected with other components through the through holes and the second metal parts, the second metal parts penetrate through the second dielectric layer, the second chip device layer, the second wafer layer and the corresponding electric connection parts of the first wafer layer, the integrated chip integrates different chips on the wafer layer and is electrically connected, thereby being beneficial to reducing the volume of the chips and simplifying the electrical connection between different chips.
Preferably, the semiconductor device further comprises a first protection layer formed on the side, away from the first monocrystalline silicon layer, of the first metal part and a second protection layer formed on the side, away from the second monocrystalline silicon layer, of the second metal part.
Preferably, a lead terminal is disposed on a surface of the first protection layer, which faces away from the first monocrystalline silicon layer, and the lead terminal is electrically connected with the first metal portion through a via penetrating through the first protection layer.
Preferably, a buffer layer is further included formed between the second chip device layer and the second monocrystalline silicon layer.
Preferably, the semiconductor device further comprises an isolation structure formed in the second chip device layer and used for isolating the adjacent second chips.
Preferably, the first chip is a driving chip, and the second chip is a gallium nitride high electron mobility transistor.
Preferably, the semiconductor device further comprises an insulating layer arranged on the side wall of the through hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer.
Preferably, the insulating layer is a silicon dioxide layer.
The invention also provides a preparation method of the integrated chip, which comprises the following steps:
Providing a wafer layer, wherein the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide dielectric layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer;
forming a groove region on the first monocrystalline silicon layer to divide the first monocrystalline silicon layer into a middle region and an edge region;
forming a first chip in the middle area of the first monocrystalline silicon layer;
Forming a first dielectric layer on one side of the first monocrystalline silicon layer, which is away from the second monocrystalline silicon layer;
Forming a second chip device layer on one side of the second monocrystalline silicon layer away from the first monocrystalline silicon layer, wherein the second chip device layer forms a second chip;
Forming a second dielectric layer on one side of the second chip device layer away from the second monocrystalline silicon layer;
Forming a via hole in a part of the second dielectric layer opposite to the electric connection part of the second chip, and forming a via hole in a part of the first dielectric layer opposite to the electric connection part of the first chip;
forming a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer at a part opposite to the edge area in the first monocrystalline silicon;
A first metal part is formed on one side of the first dielectric layer, which is away from the first monocrystalline silicon layer, and is electrically connected with the corresponding electric connection part of the first chip through a via hole, a second metal part is formed on one side of the second dielectric layer, which is away from the second chip device layer, and is electrically connected with the corresponding electric connection part of the second chip through a via hole, and the second metal part is electrically connected with the corresponding first metal part through a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer.
Preferably, the method further comprises forming a buffer layer on the side of the second monocrystalline silicon layer, which is away from the first monocrystalline silicon layer, by adopting a vapor deposition method.
Preferably, an isolation structure is formed between every two adjacent second chips in the second chip device layer by adopting an ion implantation process.
Preferably, the method further comprises forming an insulating layer on the side wall of the via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer by adopting a chemical vapor deposition method.
Preferably, the method further comprises forming a first protective layer on a side of the first metal portion facing away from the first monocrystalline silicon layer, and forming a second protective layer on a side of the second metal portion facing away from the second monocrystalline silicon layer.
Drawings
Fig. 1 to 8 are schematic diagrams illustrating film layer changes in the preparation process of an integrated chip according to the present invention.
Icon:
1-first monocrystalline silicon layer, 2-groove region, 3-middle region, 4-edge region, 5-second monocrystalline silicon layer, 6-silicon dioxide dielectric layer, 7-first dielectric layer, 8-first metal part, 9-first protective layer, 10-second chip device layer, 11-second dielectric layer, 12-second metal part, 13-second protective layer, 14-buffer layer, 15-isolation structure, 16-lead terminal, 17-insulating layer and 18-via hole.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides an integrated chip, including:
The wafer layer comprises a first monocrystalline silicon layer 1, a second monocrystalline silicon layer 5 and a silicon dioxide medium layer 6 arranged between the first monocrystalline silicon layer 1 and the second monocrystalline silicon layer 5, wherein the first monocrystalline silicon layer 1 comprises a groove region 2, the groove region 2 divides the first monocrystalline silicon layer 1 into a middle region 3 and an edge region 4, and a first chip is formed at the position of the first monocrystalline silicon layer 1, which is positioned in the middle region 3;
a first dielectric layer 7 formed on the side of the first monocrystalline silicon layer 1 facing away from the second monocrystalline silicon layer 5;
The first metal part 8 is formed on the first dielectric layer 7 and departs from the first monocrystalline silicon layer 1, and the first metal part 8 is electrically connected with the corresponding electric connection part of the first chip through the via hole 18;
The second chip device layer 10 is formed on one side of the second monocrystalline silicon layer 5 facing away from the first monocrystalline silicon layer 1, and the second chip device layer 10 forms a second chip;
A second dielectric layer 11 formed on a side of the second chip device layer 10 facing away from the second monocrystalline silicon layer 5;
the second metal part 12 is formed on one side of the second dielectric layer 11 away from the second chip device layer 10, the second metal part 12 is electrically connected with the corresponding electrical connection part of the second chip through the via hole 18, and the second metal part 12 is electrically connected with the corresponding first metal part 8 through the via hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7.
The integrated chip comprises a wafer layer, wherein the wafer layer comprises a first monocrystalline silicon layer 1, a second monocrystalline silicon layer 5 and a silicon dioxide dielectric layer 6 arranged between the first monocrystalline silicon layer 1 and the second monocrystalline silicon layer 5, the first monocrystalline silicon layer 1 comprises a groove area 2, the groove area 2 divides the first monocrystalline silicon layer 1 into a middle area 3 and an edge area 4, a first chip is formed at the position of the first monocrystalline silicon layer 1 in the middle area 3, the groove area 2 is positioned in the peripheral area of the first chip, and the electrical isolation of the first chip is realized; the integrated chip further comprises a first dielectric layer 7 formed on one side of the first monocrystalline silicon layer 1, which is far away from the second monocrystalline silicon layer 5, wherein the first dielectric layer 7 realizes the electrical isolation of the first chip, and further comprises a first metal part 8 formed on one side of the first dielectric layer 7, which is far away from the first monocrystalline silicon layer 1, wherein the first metal part 8 is electrically connected with the electrical connection part of the corresponding first chip through a via 18, the first chip is electrically connected with the first metal part 8 through the via 18, the integrated chip further comprises a second chip device layer 10 formed on one side of the second monocrystalline silicon layer 5, which is far away from the first monocrystalline silicon layer 1, a second dielectric layer 11 formed on one side of the second chip device layer 10, which is far away from the second monocrystalline silicon layer 5, and a second metal part 12 formed on one side of the second dielectric layer 11, which is far away from the second chip device layer 10, wherein the second chip device layer 10 forms the second chip, the second metal part 12 is electrically connected with the electrical connection part of the corresponding second chip through the via 18, namely, each second chip is electrically connected with the second metal part 8 through the via 18 and the second metal part 12 through the second wafer layer 11, and the second chip device layer 11 are electrically connected with the other layers, the via hole 18 of the first dielectric layer 7 is electrically connected with the corresponding first metal part 8, so that the electrical connection between the second chip electrically connected with the second chip and the first chip electrically connected with the first metal part 8 is realized, and the integrated chip integrates different chips on the wafer layer and is electrically connected, thereby being beneficial to reducing the volume of the chips and simplifying the electrical connection between different chips.
The trench region may be filled with an insulating material, such as silicon dioxide, to electrically isolate the periphery of the first chip.
Specifically, the first protective layer 9 formed on the side of the first metal portion 8 facing away from the first single crystal silicon layer 1 and the second protective layer 13 formed on the side of the second metal portion 12 facing away from the second single crystal silicon layer 5 are also included.
The integrated chip further comprises the first protective layer 9 and the second protective layer 13 formed on the surfaces of the two sides of the chip, namely on the side, away from the first monocrystalline silicon layer 1, of the first metal part 8 and on the side, away from the second monocrystalline silicon layer 5, of the second metal part 12, so that the internal structure of the chip is protected, the service life of the integrated chip is prolonged, and meanwhile, the integrated chip is attractive.
Specifically, a lead terminal 16 is disposed on a surface of the first protection layer 9 facing away from the first monocrystalline silicon layer 1, and the lead terminal 16 is electrically connected to the first metal portion 8 through a via 18 penetrating the first protection layer 9.
A lead terminal 16 is disposed on a surface of the first protection layer 9 facing away from the first monocrystalline silicon layer 1, one end of the lead terminal 16 is electrically connected with the first metal portion 8 through a via hole 18 penetrating through the first protection layer 9, and the other end is used for being connected with other devices in a use process.
Specifically, a buffer layer 14 is further included that is formed between the second chip device layer 10 and the second single crystal silicon layer 5.
A buffer layer 14 is provided between the second chip device layer 10 and the second monocrystalline silicon layer 5, enabling a transition between the second monocrystalline silicon layer 5 and the second chip device layer 10.
Specifically, the isolation structure 15 formed in the second chip device layer 10 is further included to isolate adjacent second chips.
When the second chip device layer 10 is formed with a plurality of second chips, the isolation structures 15 are disposed between the adjacent second chips to realize electrical isolation between the adjacent second chips, so as to prevent interference between the adjacent second chips from affecting the performance of the second chips.
In another embodiment, the first chip and the second chip can be two parts after a large-area chip is decomposed, the integrated chip realizes that the two sides of a wafer layer are realized after the large-area chip is decomposed, and the chip area is reduced and simultaneously the miniaturized packaging of the device is realized.
Specifically, the semiconductor device further comprises an insulating layer 17 arranged on the side wall of the through hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7, wherein the insulating layer 17 is arranged on the side wall of the through hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7 to facilitate the electrical isolation of the first chip and the second chip and prevent the performance of the chip from being influenced, and the insulating layer 17 is a silicon dioxide layer or other material layers with insulating performance.
The invention also provides a preparation method of the integrated chip, which comprises the following steps:
First, as shown in fig. 1, a recess is prepared in a wafer layer to form a recess region 2, the wafer layer including a first single crystal silicon layer 1, a second single crystal silicon layer 5, and a silicon dioxide dielectric layer 6 disposed between the first single crystal silicon layer 1 and the second single crystal silicon layer 5, the recess region 2 being formed in the first single crystal silicon layer 1 to partition the first single crystal silicon layer 1 into a middle region 3 and an edge region 4;
then, forming a first chip in the intermediate region 3 of the first single crystal silicon layer 1;
then, as shown in fig. 1, a first dielectric layer 7 is formed on the side of the first single crystal silicon layer 1 facing away from the second single crystal silicon layer 5;
then, as shown in fig. 2, a buffer layer 14 is formed on the side of the second single crystal silicon layer 5 facing away from the first single crystal silicon layer 1;
then, as shown in fig. 2, a second chip device layer 10 is formed on the side of the buffer layer 14 facing away from the first monocrystalline silicon layer 1, the second chip device layer 10 forming a second chip;
Then, as shown in fig. 3, a second dielectric layer 11 is formed on the side of the second chip device layer 10 facing away from the second monocrystalline silicon layer 5;
Then, as shown in fig. 4, a via hole 18 is formed in the second dielectric layer 11 at a position facing the electrical connection portion of the second chip, and a via hole 18 is formed in the first dielectric layer 7 at a position facing the electrical connection portion of the first chip;
Then, as shown in fig. 5, a via hole 18 penetrating the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7 is formed in a portion facing the edge region 4 in the first single crystal silicon;
Then, as shown in fig. 6, an insulating layer 17 is formed on the side walls of the via hole 18 penetrating the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7;
then, as shown in fig. 7, a first metal part 8 is formed on one side of the first dielectric layer 7 away from the first monocrystalline silicon layer 1, and the first metal part 8 is electrically connected with the corresponding electrical connection part of the first chip through a via 18, a second metal part 12 is formed on one side of the second dielectric layer 11 away from the second chip device layer 10, and the second metal part 12 is electrically connected with the corresponding electrical connection part of the second chip through a via 18, wherein the second metal part 12 is electrically connected with the corresponding first metal part 8 through a via 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7;
then, as shown in fig. 8, a first protective layer 9 is formed on the side of the first metal portion 8 facing away from the first single crystal silicon layer 1, and a second protective layer 13 is formed on the side of the second metal portion 12 facing away from the second single crystal silicon layer 5.
In the above method for manufacturing an integrated chip, the first chip is manufactured in the central area of the first monocrystalline silicon of the wafer layer, the second chip is manufactured in the side, away from the first monocrystalline silicon layer 1, of the second monocrystalline silicon layer 5 of the wafer layer, the integration of the first chip and the second chip is achieved, the effect of reducing the chip mention is achieved, the first metal part 8 electrically connected with the electrical connection part of the first chip is manufactured in the side, away from the wafer layer, of the first chip, the second metal part 12 electrically connected with the electrical connection part of the second chip is manufactured in the side, away from the wafer layer, of the second chip, and the first metal part 8 is electrically connected with the second metal part 12 through the via hole 18 penetrating through the wafer layer, so that the electrical connection between the first chip and the second chip is simplified.
Specifically, in the preparation method, a buffer layer 14 is formed on one side of the second monocrystalline silicon layer 5, which is far away from the first monocrystalline silicon layer 1, by adopting a vapor deposition method, as shown in fig. 3, an isolation structure 15 is formed between every two adjacent second chips in the second chip device layer 10 by adopting an ion implantation process, an insulating layer 17 is formed on the side wall of a via hole 18 penetrating through the second dielectric layer 11, the second chip device layer 10, the wafer layer and the first dielectric layer 7 by adopting a chemical vapor deposition method, and an insulating layer 17 is formed on the side wall of the via hole 18 by adopting a chemical vapor deposition method, so that the forming mode is simple and good.
It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (14)
1. An integrated chip, comprising:
the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide medium layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer, the first monocrystalline silicon layer comprises a groove area which divides the first monocrystalline silicon layer into a middle area and an edge area, and a first chip is formed at the position of the first monocrystalline silicon layer in the middle area;
the first dielectric layer is formed on one side of the first monocrystalline silicon layer, which is away from the second monocrystalline silicon layer;
the first metal part is formed on the first dielectric layer and deviates from the first monocrystalline silicon layer, and the first metal part is electrically connected with the corresponding electric connection part of the first chip through a via hole;
the second chip device layer is formed on one side of the second monocrystalline silicon layer, which is away from the first monocrystalline silicon layer, and the second chip device layer forms a second chip;
The second dielectric layer is formed on one side of the second chip device layer, which is away from the second monocrystalline silicon layer;
The second metal part is electrically connected with the corresponding electric connection part of the second chip through a via hole, and is electrically connected with the corresponding first metal part through a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer;
The first chip and the second chip are integrated into the integrated chip through a wafer process.
2. The integrated chip of claim 1, further comprising a first protective layer formed on a side of the first metal portion facing away from the first single crystal silicon layer and a second protective layer formed on a side of the second metal portion facing away from the second single crystal silicon layer.
3. The integrated chip of claim 2, wherein a surface of the first protective layer facing away from the first monocrystalline silicon layer is provided with a lead terminal, the lead terminal being electrically connected to the first metal portion through a via penetrating the first protective layer.
4. The integrated chip of claim 1, further comprising a buffer layer formed between the second chip device layer and the second single crystal silicon layer.
5. The integrated chip of claim 1, further comprising an isolation structure formed in the second chip device layer for isolating adjacent second chips.
6. The integrated chip of claim 1, wherein the first chip is a driver chip.
7. The integrated chip of claim 1, wherein the second chip is a gallium nitride high electron mobility transistor.
8. The integrated chip of claim 1, further comprising an insulating layer disposed through sidewalls of the vias of the second dielectric layer, the second chip device layer, the wafer layer, the first dielectric layer.
9. The integrated chip of claim 8, wherein the insulating layer is a silicon dioxide layer.
10. A method of manufacturing an integrated chip, comprising:
Providing a wafer layer, wherein the wafer layer comprises a first monocrystalline silicon layer, a second monocrystalline silicon layer and a silicon dioxide dielectric layer arranged between the first monocrystalline silicon layer and the second monocrystalline silicon layer;
forming a groove region on the first monocrystalline silicon layer to divide the first monocrystalline silicon layer into a middle region and an edge region;
forming a first chip in the middle area of the first monocrystalline silicon layer;
Forming a first dielectric layer on one side of the first monocrystalline silicon layer, which is away from the second monocrystalline silicon layer;
Forming a second chip device layer on one side of the second monocrystalline silicon layer away from the first monocrystalline silicon layer, wherein the second chip device layer forms a second chip;
Forming a second dielectric layer on one side of the second chip device layer away from the second monocrystalline silicon layer;
Forming a via hole in a part of the second dielectric layer opposite to the electric connection part of the second chip, and forming a via hole in a part of the first dielectric layer opposite to the electric connection part of the first chip;
forming a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer at a part opposite to the edge area in the first monocrystalline silicon;
A first metal part is formed on one side of the first dielectric layer, which is away from the first monocrystalline silicon layer, and is electrically connected with the corresponding electric connection part of the first chip through a via hole, a second metal part is formed on one side of the second dielectric layer, which is away from the second chip device layer, and is electrically connected with the corresponding electric connection part of the second chip through a via hole, and the second metal part is electrically connected with the corresponding first metal part through a via hole penetrating through the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer.
11. The method of claim 10, further comprising forming a buffer layer on a side of the second single crystal silicon layer facing away from the first single crystal silicon layer using a vapor deposition method.
12. The method of claim 10, further comprising forming isolation structures between each adjacent two of the second chips in the second chip device layer using an ion implantation process.
13. The method of claim 10, further comprising forming an insulating layer on sidewalls of the via hole penetrating the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer by chemical vapor deposition.
14. The method of manufacturing of claim 10, further comprising forming a first protective layer on a side of the first metal portion facing away from the first monocrystalline silicon layer, and forming a second protective layer on a side of the second metal portion facing away from the second monocrystalline silicon layer.
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