CN112768433A - Electronic packaging structure and manufacturing method - Google Patents
Electronic packaging structure and manufacturing method Download PDFInfo
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- CN112768433A CN112768433A CN202110102066.1A CN202110102066A CN112768433A CN 112768433 A CN112768433 A CN 112768433A CN 202110102066 A CN202110102066 A CN 202110102066A CN 112768433 A CN112768433 A CN 112768433A
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- 238000004100 electronic packaging Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 241
- 229910052802 copper Inorganic materials 0.000 claims abstract description 214
- 239000010949 copper Substances 0.000 claims abstract description 214
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000000565 sealant Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 67
- 238000000034 method Methods 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000003466 welding Methods 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 3
- 239000008393 encapsulating agent Substances 0.000 claims 1
- 230000017525 heat dissipation Effects 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000003292 glue Substances 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 238000003754 machining Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明公开了一种电子封装结构及制造方法，结构包括：基板；电子单元，所述电子单元设置在所述基板上；铜结构，所述铜结构包括依次堆叠设置的第一铜柱和铜连接块，所述第一铜柱和所述铜连接块均设置有多个，每一所述第一铜柱的一端与所述基板电连接，所述第一铜柱的另一端与对应的铜连接块电连接，所述电子单元设置在所述基板和所述铜连接块之间；塑封胶，所述塑封胶用于将所述电子单元和所述铜结构封装在所述基板上，铜连接块的端面露设于所述塑封胶的表面。应用本发明，能够在不增大电子单元的芯片管芯面积的同时，提升电子封装结构的整体散热效率。
The invention discloses an electronic packaging structure and a manufacturing method. The structure includes: a substrate; an electronic unit, the electronic unit is arranged on the substrate; A connection block, a plurality of the first copper pillars and the copper connection block are provided, one end of each of the first copper pillars is electrically connected to the substrate, and the other end of the first copper pillar is connected to the corresponding The copper connection block is electrically connected, and the electronic unit is arranged between the substrate and the copper connection block; the plastic sealant is used to encapsulate the electronic unit and the copper structure on the substrate, The end surface of the copper connection block is exposed on the surface of the plastic sealant. By applying the present invention, the overall heat dissipation efficiency of the electronic package structure can be improved without increasing the chip die area of the electronic unit.
Description
Technical Field
The present invention relates to the field of electronic module packaging technologies, and in particular, to an electronic package structure and a manufacturing method thereof.
Background
For a power chip module with high power, heat dissipation is an urgent problem to be solved. How to solve the heat dissipation problem while the integration level is improved becomes a great challenge. For a chip, when the current increases, the heating power increases in a square number without changing the resistance. This resistance may be the internal resistance of the chip or the conductor resistance of the package. And high heat generation can cause the problems of low reliability, performance reduction, short service life and the like of the chip. The heat dissipation of the module is improved, and the heat dissipation can be realized by reducing the internal resistance of the chip. Reducing the internal resistance of the chip requires increasing the area of the die of the chip, which increases the additional cost, for example, an 8-inch wafer may originally have 1000 chips, and after the area of the chip is increased, only 800 chips may be manufactured.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides an electronic packaging structure and a manufacturing method thereof, which can improve the overall heat dissipation efficiency of the electronic packaging structure without increasing the chip tube core area of an electronic unit.
According to the electronic packaging structure of the embodiment of the first aspect of the invention, the electronic packaging structure comprises:
a substrate;
an electronic unit disposed on the substrate;
the copper structure comprises a plurality of first copper columns and a plurality of copper connecting blocks which are sequentially stacked, one end of each first copper column is electrically connected with the substrate, the other end of each first copper column is electrically connected with the corresponding copper connecting block, and the electronic unit is arranged between the substrate and the copper connecting blocks;
and the plastic package glue is used for packaging the electronic unit and the copper structure on the substrate, and the end face of the copper connecting block is exposed on the surface of the plastic package glue.
The electronic packaging structure provided by the embodiment of the invention at least has the following beneficial effects: one end of the first copper column is electrically connected with the substrate, the other end of the first copper column is electrically connected with the corresponding copper connecting block, and the electronic unit is arranged between the substrate and the copper connecting block. On one hand, the substrate can be electrically connected with the outside through the first copper column and the copper connecting block; on the other hand, the heat generated by the substrate itself or the heat generated by the substrate due to the heat generated by the electronic unit may be transferred to the outside through the first copper pillar or the copper connection block. The electronic packaging structure provided by the embodiment of the invention improves the whole heat dissipation efficiency of the electronic packaging structure without increasing the chip tube core area of the electronic unit.
According to some embodiments of the invention, the copper structure further comprises a copper connection layer, the copper connection layer is stacked on a side surface of the copper connection block opposite to the first copper pillar, the copper connection blocks are connected with each other through the copper connection layer, and the copper connection layer is used for enabling an end surface of the copper connection block to be exposed on the surface of the molding compound after being ground.
According to some embodiments of the invention, the electronic unit comprises a chip and a first component, the chip and the first component being electrically connected to the substrate, respectively.
According to some embodiments of the invention, the first component is a capacitor.
According to some embodiments of the invention, the chip further comprises at least one second copper pillar, one end of the second copper pillar is abutted to the end face of the chip, and the other end of the second copper pillar is connected with the corresponding copper connecting block.
According to some embodiments of the invention, the electronic package structure further comprises at least one second component electrically connected to a corresponding side of the copper connection block facing away from the first copper pillar.
According to some embodiments of the invention, the substrate comprises a bottom layer pad, a bottom layer network, a third layer network, a second layer network, a top layer network and a top layer pad which are stacked in sequence, and the layers are electrically connected through an electrical connection through hole.
According to some embodiments of the invention, the electronic unit is electrically connected to the substrate through the top layer pad.
The electronic packaging structure manufacturing method according to the second aspect of the embodiment of the invention comprises the following steps:
mounting an electronic unit on a substrate;
mounting a copper structure on the substrate, wherein the copper structure comprises a plurality of first copper columns, a plurality of copper connecting blocks and copper connecting layers which are sequentially stacked, one end of each first copper column is electrically connected with the substrate, the other end of each first copper column is electrically connected with the corresponding copper connecting block, the electronic unit is arranged between the substrate and the copper connecting blocks, the copper connecting layers are attached to the side surfaces, back to the first copper columns, of the copper connecting blocks, and the copper connecting blocks are connected with one another through the copper connecting layers;
plastically packaging the electronic unit and the copper structure through a plastic package adhesive;
and grinding the surface of the plastic sealant to grind off the surface layer of the plastic sealant and the copper connecting layer, so that the end face of the copper connecting block is exposed on the surface of the plastic sealant to form a welding pad.
According to some embodiments of the invention, further comprising:
an inductor is soldered to the solder pad.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of layers of a substrate of an electronic package structure according to an embodiment of the invention;
fig. 2 is a schematic diagram of a substrate, a chip, a first component, a first copper pillar, and a second copper pillar of an electronic package structure according to an embodiment of the invention;
fig. 3 is a schematic diagram of a substrate, a chip, a first component, a first copper pillar, a second copper pillar, and a copper connection block of an electronic package structure according to an embodiment of the invention;
fig. 4 is a schematic diagram of a substrate, a chip, a first component, a first copper pillar, a second copper pillar, a copper connection block, and a copper connection layer of an electronic package structure according to an embodiment of the invention;
FIG. 5 is a schematic diagram of the electronic package structure according to the embodiment of the invention after being molded;
FIG. 6 is a schematic diagram of the electronic package structure after being molded and then ground according to the embodiment of the invention;
fig. 7 is a schematic diagram of an electronic package structure with an inductor mounted thereon according to an embodiment of the invention;
fig. 8 is a flowchart of a method for manufacturing an electronic package structure according to an embodiment of the invention.
Reference numerals:
a chip 200;
a first component 300;
a second component 400;
a copper structure 500, a first copper pillar 510, a copper connection block 520, a copper connection layer 530, and a second copper pillar 540;
and molding the molding compound 600.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
With the progress of the wafer manufacturing process, the calculation speed of the CPU is faster and faster, and high calculation power brings many challenges to hardware. The CPU power consumption adopted in the data center and the server is higher and higher, and under the current process conditions, in order to meet the demand of high computational power, the CPU power consumption can be generally realized by reducing the voltage and increasing the output current. The increase in power consumption causes devices such as CPUs to consume even thousands of amperes of power and their power requirements can be rapidly shifted. How to realize large current in a limited PCB space by adopting a minimum area and meeting the condition of rapid power shifting, the multiphase inverse inductance type voltage regulator is provided at present. On the basis of the structure (the multi-phase inductance voltage regulating module, TLVR), the structure is packaged in a modularized mode to form an electronic packaging structure, and reliability and integration level of products can be further improved.
Referring to fig. 1, 2, 3, 4, 5, 6 and 7, an embodiment of a first aspect of the present invention proposes an electronic package structure, including: a substrate 100; an electronic unit disposed on the substrate 100; the copper structure 500 comprises a plurality of first copper columns 510 and a plurality of copper connecting blocks 520 which are sequentially stacked, one end of each first copper column 510 is electrically connected with the substrate 100, the other end of each first copper column 510 is electrically connected with the corresponding copper connecting block 520, and the electronic unit is arranged between the substrate 100 and the copper connecting block 520; the plastic package glue 600 is used for packaging the electronic unit and the copper structure 500 on the substrate 100, and the end face of the copper connecting block 520 is exposed on the surface of the plastic package glue 600.
It will be appreciated that the substrate 100 may generally include a bottom pad 110, a bottom network 120, a third network 130, a second network 140, a top network 150, and a top pad 160 stacked in this order, electrically connected by an electrical connection via 170, and may further include an epoxy layer. The electronic unit is electrically connected to the substrate 100 through the top layer pad 160. At least two first copper pillars 510 are connected to the same copper connection block 520 so that the two first copper pillars 510 are electrically connected through the same copper connection block 520. The electronic unit includes a chip 200 and a first component 300, and the chip 200 and the first component 300 are electrically connected to the substrate 100, respectively. The first component 300 is a capacitor. One end of the first copper pillar 510 is electrically connected to the substrate 100, and the other end is electrically connected to the corresponding copper connection block 520, and the electronic unit is disposed between the substrate 100 and the copper connection block 520. In one aspect, the substrate 100 may be electrically connected to the outside through the first copper pillar 510 and the copper connection block 520; on the other hand, heat generated by the substrate 100 itself or heat generated by the electronic unit of the substrate 100 may be transferred to the outside through the first copper pillar 510 and the copper connection block 520. The electronic packaging structure provided by the embodiment of the invention can improve the thickness of the copper connecting block 520 without increasing the area of the chip 200 tube core of the electronic unit, the improvement of the thickness is equivalent to reduction of resistance, and the reduction of the resistance and the reduction of heat productivity are realized, so that the overall heat dissipation efficiency of the electronic packaging structure is improved.
In some embodiments of the present invention, the copper structure 500 further includes a copper connection layer 530, the copper connection layer 530 is stacked on a side of the copper connection block 520 facing away from the first copper pillar 510, and the copper connection blocks 520 are connected to each other through the copper connection layer 530. On the basis of the copper connecting block 520 of the second layer, the copper branch connecting layer of the third layer is placed, the dispersed copper connecting blocks 520 are connected into a whole, the whole stability of the copper structure 500 is promoted in the machining process, and therefore the convenience of the machining process is promoted. After the plastic package of the chip 200 is completed, the end face of the plastic package adhesive 600 is ground, and the copper branch connecting layer of the third layer is completely ground until the copper connecting block 520 of the second layer leaks out, so as to be used as a welding pad at the top of the package of the chip 200.
It is understood that the copper connection block 520 may be configured to have a sectional area larger than that of the first copper pillar 510, thereby facilitating heat dissipation. One copper connection block 520 may also connect different first copper pillars 510, so that electrical connection between different first copper pillars 510 may be achieved. The copper connection layer 530 may be a copper plate of one layer, and the copper connection layer 530 covers the plurality of copper connection blocks 520 to connect the respective copper connection blocks 520 into a whole, so that the first copper pillar 510 and the copper connection blocks 520 may be installed as a whole when being installed on the substrate 100, and the installation efficiency may be effectively improved compared to individually installing the first copper pillar 510 and the copper connection blocks 520. The first copper pillar 510 may have a cylindrical shape or a prismatic shape. It is understood that in the subsequent process flow, the copper connection layer 530 is ground away by a grinder, so that the end surface of the copper connection block 520 is exposed on the surface of the molding compound 600. The first copper pillar 510, the copper connection block 520, and the copper connection layer 530 may be integrally formed by a stamping technique to form the copper structure 500. It is understood that the electronic package structure further includes at least one second component 400, the at least one second component 400 is electrically connected with a corresponding copper connection block 520 at a side facing away from the first copper pillar 510, and the second component 400 may be an inductor. The inductor is separated from the capacitor and the chip 200, so that the integration level of the electronic packaging structure can be effectively improved.
In some embodiments of the present invention, the chip further comprises at least one second copper pillar 540, one end of the second copper pillar 540 abuts against the end surface of the chip 200, and the other end of the second copper pillar 540 is connected to the corresponding copper connection block 520. By such an arrangement, heat generated by the chip 200 during use can be dissipated to the outside through the second copper pillar 540 and the corresponding copper connection block 520. It is understood that the second copper pillar 540 may have a cylindrical shape or a prism shape. A second copper pillar 540, placed on the chip 200, can be used to independently follow any second layer of copper connection block 520, since there is no electrical capability. In order to achieve better heat dissipation, a plurality of second copper pillars 540 may be disposed on the upper end surface of the same chip 200.
Referring to fig. 8, an embodiment of a second aspect of the present invention provides a method for manufacturing an electronic package structure, including the following steps:
step S100: the electronic unit is mounted on the substrate 100.
Step S200: the copper structure 500 is mounted on the substrate 100, wherein the copper structure 500 includes a plurality of first copper pillars 510, a plurality of copper connection blocks 520 and a copper connection layer 530 stacked in sequence, one end of each first copper pillar 510 is electrically connected to the substrate 100, the other end of each first copper pillar 510 is electrically connected to the corresponding copper connection block 520, the electronic unit is disposed between the substrate 100 and the copper connection block 520, the copper connection layer 530 is attached to the side of the copper connection block 520, which faces away from the first copper pillars 510, and the copper connection blocks 520 are connected to each other through the copper connection layer 530.
Step S300: the electronic unit and the copper structure 500 are plastically packaged by a molding compound 600.
Step S400: the surface of the plastic package adhesive 600 is ground to remove the surface layer of the plastic package adhesive 600 and the copper connection layer 530, so that the end surface of the copper connection block 520 is exposed on the surface of the plastic package adhesive 600 to form a welding pad.
Step S500: the inductor is soldered to the solder pad.
It is understood that one end of the first copper pillar 510 is electrically connected to the substrate 100 and the other end is electrically connected to the corresponding copper connection block 520, and the electronic unit is disposed between the substrate 100 and the copper connection block 520. In one aspect, the substrate 100 may be electrically connected to the outside through the first copper pillar 510 and the copper connection block 520; on the other hand, heat generated by the substrate 100 itself or heat generated by the electronic unit of the substrate 100 may be transferred to the outside through the first copper pillar 510 and the copper connection block 520. The electronic packaging structure provided by the embodiment of the invention improves the whole heat dissipation efficiency of the electronic packaging structure without increasing the area of the chip 200 tube core of the electronic unit. In addition, on the basis of the copper connecting block 520 of the second layer, the copper branch connecting layer of the third layer is placed, and the dispersed copper connecting blocks 520 are connected into a whole, so that the whole stability of the copper structure 500 is improved in the machining process, and the convenience of the machining process is improved. After the plastic package of the chip 200 is completed, the end face of the plastic package adhesive 600 is ground, and the copper branch connecting layer of the third layer is completely ground until the copper connecting block 520 of the second layer leaks out, so as to be used as a welding pad at the top of the package of the chip 200.
An electronic package structure according to an embodiment of the present invention is described in detail with reference to fig. 1 to 7. It is to be understood that the following description is only exemplary, and not a specific limitation of the invention.
An embodiment of the present invention provides an electronic package structure, including: a substrate 100; an electronic unit disposed on the substrate 100; the copper structure 500 comprises a plurality of first copper columns 510 and a plurality of copper connecting blocks 520 which are sequentially stacked, one end of each first copper column 510 is electrically connected with the substrate 100, the other end of each first copper column 510 is electrically connected with the corresponding copper connecting block 520, and the electronic unit is arranged between the substrate 100 and the copper connecting block 520; the plastic package glue 600 is used for packaging the electronic unit and the copper structure 500 on the substrate 100, and the end face of the copper connecting block 520 is exposed on the surface of the plastic package glue 600.
The copper structure 500 further includes a copper connection layer 530, the copper connection layer 530 is stacked on a side of the copper connection block 520 facing away from the first copper pillar 510, and the copper connection blocks 520 are connected to each other through the copper connection layer 530. The electronic unit includes a chip 200 and a first component 300, and the chip 200 and the first component 300 are electrically connected to the substrate 100, respectively. The first component 300 is a capacitor. The chip structure further comprises at least one second copper column 540, one end of the second copper column 540 is abutted to the end face of the chip 200, and the other end of the second copper column 540 is connected with the corresponding copper connecting block 520.
The electronic package structure further includes at least one second component 400, the at least one second component 400 being electrically connected to a side of the corresponding copper connection block 520 facing away from the first copper pillar 510. The substrate 100 includes a bottom pad 110, a bottom network 120, a third network 130, a second network 140, a top network 150, and a top pad 160 stacked in this order, and the layers are electrically connected by an electrical connection via 170. The electronic unit is electrically connected to the substrate 100 through the top layer pad 160.
According to the power module package structure of the embodiment of the invention, at least some effects can be achieved by such an arrangement, one end of the first copper pillar 510 is electrically connected to the substrate 100, the other end is electrically connected to the corresponding copper connection block 520, and the electronic unit is disposed between the substrate 100 and the copper connection block 520. In one aspect, the substrate 100 may be electrically connected to the outside through the first copper pillar 510 and the copper connection block 520; on the other hand, heat generated by the substrate 100 itself or heat generated by the electronic unit of the substrate 100 may be transferred to the outside through the first copper pillar 510 and the copper connection block 520. The electronic packaging structure provided by the embodiment of the invention improves the whole heat dissipation efficiency of the electronic packaging structure without increasing the area of the chip 200 tube core of the electronic unit.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (10)
Priority Applications (1)
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| CN202110102066.1A CN112768433A (en) | 2021-01-26 | 2021-01-26 | Electronic packaging structure and manufacturing method |
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| CN202110102066.1A CN112768433A (en) | 2021-01-26 | 2021-01-26 | Electronic packaging structure and manufacturing method |
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| CN112768433A true CN112768433A (en) | 2021-05-07 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170345735A1 (en) * | 2016-05-30 | 2017-11-30 | Industrial Technology Research Institute | Plug-in type power module and subsystem thereof |
| CN110767647A (en) * | 2019-11-15 | 2020-02-07 | 矽力杰半导体技术(杭州)有限公司 | Package structure and method for manufacturing the same |
| CN212209463U (en) * | 2019-10-10 | 2020-12-22 | 华为技术有限公司 | Packaging structure and electronic device |
| CN214043655U (en) * | 2021-01-26 | 2021-08-24 | 东莞市长工微电子有限公司 | Electronic packaging structure |
-
2021
- 2021-01-26 CN CN202110102066.1A patent/CN112768433A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170345735A1 (en) * | 2016-05-30 | 2017-11-30 | Industrial Technology Research Institute | Plug-in type power module and subsystem thereof |
| CN212209463U (en) * | 2019-10-10 | 2020-12-22 | 华为技术有限公司 | Packaging structure and electronic device |
| CN110767647A (en) * | 2019-11-15 | 2020-02-07 | 矽力杰半导体技术(杭州)有限公司 | Package structure and method for manufacturing the same |
| CN214043655U (en) * | 2021-01-26 | 2021-08-24 | 东莞市长工微电子有限公司 | Electronic packaging structure |
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