CN112737579B - Subsampling phase-locked loop - Google Patents
Subsampling phase-locked loop Download PDFInfo
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- CN112737579B CN112737579B CN201911032046.0A CN201911032046A CN112737579B CN 112737579 B CN112737579 B CN 112737579B CN 201911032046 A CN201911032046 A CN 201911032046A CN 112737579 B CN112737579 B CN 112737579B
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- 238000001514 detection method Methods 0.000 claims abstract description 35
- 238000005070 sampling Methods 0.000 claims abstract description 31
- 238000003079 width control Methods 0.000 claims description 22
- 230000011664 signaling Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 239000013256 coordination polymer Substances 0.000 description 2
- 238000003705 background correction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000026683 transduction Effects 0.000 description 1
- 238000010361 transduction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a subsampled phase-locked loop which comprises a phase detector, a charge pump, an oscillator and a buffer. In the operation of the sub-sampling phase-locked loop, the phase detector uses a reference frequency signal to sample a feedback signal to generate a first phase detection result, the charge pump generates a control signal according to the first phase detection result and a pulse signal, and the oscillator generates an output frequency signal according to the control signal; the buffer is used for receiving the output frequency signal and generating the feedback signal, and controlling the slew rate of the feedback signal according to a slew rate control signal.
Description
Technical Field
The present invention relates to a subsampled phase locked loop.
Background
In a pll, the bandwidth is affected by a number of parameters, such as the current of the charge pump, the coefficient of the frequency divider, and the gain of the vco, which are easily affected by the process, the voltage, and the temperature offset (process-voltage-temperature (PVT) variations), resulting in unstable performance of the pll.
Disclosure of Invention
It is therefore an object of the present invention to provide a subsampled phase locked loop which provides a stable bandwidth to solve the problems described in the prior art.
In one embodiment of the present invention, a sub-sampling phase-locked loop is disclosed, which includes a first phase detector, a first charge pump, an oscillator, and a first buffer. In the operation of the sub-sampling phase-locked loop, the first phase detector samples a feedback signal using a reference frequency signal to generate a first phase detection result, the first charge pump generates a first control signal according to the first phase detection result and a pulse signal, and the oscillator generates an output frequency signal according to the first signal; the first buffer is used for receiving the output frequency signal and generating the feedback signal, and controlling the slew rate of the feedback signal according to a slew rate control signal.
In another embodiment of the present invention, a sub-sampling phase-locked loop is disclosed, which comprises a phase detector, a pulse signal generating circuit, a charge pump, an oscillator and a pulse width control circuit. In operation of the sub-sampling phase-locked loop, the phase detector uses a reference frequency signal to sample a feedback signal to generate a phase detection result; the pulse signal generating circuit generates a pulse signal according to the reference frequency signal; the charge pump generates a control signal according to the phase detection result and the pulse signal; the oscillator generates an output frequency signal according to the control signal; and the pulse width control circuit generates a pulse width control signal to the pulse signal generating circuit according to the output frequency signal so as to control the pulse width of the pulse signal.
Drawings
Fig. 1 is a schematic diagram of a sub-sampling phase-locked loop according to an embodiment of the present invention.
Fig. 2 is a flowchart of a bandwidth correction method of a sub-sampling pll according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a pulse width control circuit according to an embodiment of the invention.
Fig. 4 is a schematic diagram of a buffer, a phase detection circuit and a slew rate control circuit according to an embodiment of the invention.
Detailed Description
Fig. 1 is a schematic diagram of a sub-sampling phase-locked loop (sub-SAMPLINGPHASE-locked loop) 100 according to one embodiment of the present invention. As shown in fig. 1, the sub-sampling pll 100 includes a pulse signal generating circuit 110, a first charge pump 120, a phase detector 130, a buffer 140, an oscillator 150, a slew rate control circuit 160, a pulse width control circuit 170, a coarse frequency selecting circuit 180, a phase frequency detector 192, a second charge pump 194, a frequency divider 196, capacitors CP and CS, and a resistor RS.
In the basic operation of the sub-sampling phase-locked loop 100, the pulse signal generating circuit 110 is configured to receive a reference clock signal ck_ref to generate a pulse signal Vp; the phase detector 130 samples a feedback signal ck_fb using the reference clock signal ck_ref to generate a first phase detection result Vsam; the first charge pump 120 generates a first signal V1 according to the first phase detection result Vsam and the pulse signal Vp for generating a control signal v_tune to the oscillator 150, wherein the voltage v_tune is generated by combining the first signal V1 with a second signal V2 and then passing through the filter circuit; the oscillator 150 generates an output clock signal ck_out according to a coarse clock signal b_code and the control signal v_tune; the buffer 140 receives the output clock signal ck_out to generate the feedback signal ck_fb. On the other hand, the frequency divider 196 performs a frequency dividing operation on the output clock signal ck_out to generate a frequency-divided output clock signal ck_div, the phase frequency detector 192 receives the reference clock signal ck_ref and the frequency-divided output clock signal ck_div to generate a phase frequency detection result, and the second charge pump 194 generates the second signal V2 according to the phase frequency detection result. It should be noted that the operations of the phase frequency detector 192, the second charge pump 194 and the divider 196 are used to make the integral part of the frequency of the output frequency signal ck_out correct, and the operations of the pulse signal generating circuit 110, the first charge pump 120, the phase detector 130 and the buffer 140 are used to make the fractional part of the frequency of the output frequency signal ck_out correct, for example, assuming that the frequency of the reference frequency signal ck_ref is 40MHz and the target of the output frequency signal ck_out is 2410MHz (the multiple is 60.25), the two sets of circuits are used to lock the integral part "60" and the fractional part "0.25" of the multiple, respectively. It should be noted that, since the basic operation of the above components is well known to those skilled in the art, and the present invention is not limited thereto, details thereof are not described herein.
In the subsampled phase locked loop 100, its bandwidth can be expressed as follows:
Where gain_ SSPD refers to the gain of the phase detector 130, gm is the transduction value of the first charge pump 120 and related circuits, KVCO is the gain of the oscillator 150, τ_pul is the pulse width of the pulse signal Vp, tref is the period of the reference frequency signal ck_ref. In addition, the gain gain_ SSPD of the phase detector 130 can be expressed as follows:
Wherein TVCO is a period of the output frequency signal ck_out. As described above, since the bandwidth of the sub-sampling pll 100 is determined by the parameters, which are easily affected by process, voltage and temperature deviations, the slew rate control circuit 160 and the pulse width control circuit 170 are provided to determine the slew rate of the feedback signal ck_fb generated by the buffer 140 (i.e. corresponding to the equation (2) ) The pulse width τ_pul of the pulse signal Vp generated by the pulse signal generating circuit 110 and (gm×rs) in the formula (1) can maintain a constant value by the design of the first charge pump 120 in the prior art, so as to achieve the above objective. Details thereof are detailed in the following examples.
Fig. 2 is a flowchart of a bandwidth correction method of the sub-sampling phase-locked loop 100 according to an embodiment of the present invention. Referring to fig. 1 and 2, at step 200, the process begins, and the sub-sampling pll 100 begins to operate to receive the reference clock signal ck_ref to generate the output clock signal ck_out. In step 202, the coarse frequency selecting circuit 180 determines the coarse frequency handle b_code for the oscillator 150 according to the output frequency signal ck_out and a target frequency of the sub-sampling phase-locked loop 100. Since the circuit architecture and related operations of the coarse frequency selection circuit 180 are well known to those skilled in the art, for example, a conventional binary search method can be used to determine the coarse frequency handle b_code, and the content of the coarse frequency selection circuit 180 is not important in the present invention, details thereof are not described herein.
In step 204, the pwm control circuit 170 generates a plurality of control signals v_tune with a plurality of different voltage levels to the oscillator 150, so that the oscillator 150 generates a plurality of output frequency signals ck_out with different frequencies, calculates the gain of the oscillator 150 according to the plurality of control signals v_tune and the plurality of output frequency signals ck_out, determines the pulse width τ_pul of the pulse signal Vp according to the gain of the oscillator 150, and generates a pulse width control signal p_code to the pulse signal generating circuit 110 according to the pulse width control signal p_code. In detail, referring to the schematic diagrams of the pwm control circuit 170 and the oscillator 150 shown in fig. 3, the pwm control circuit 170 includes two switches SW1 and SW2, a frequency divider 310, a counter 320, a calculating circuit 330 and a searching circuit 340, wherein VH and VL are respectively the highest voltage and the lowest voltage that the control signal v_tune can have. In the operation of the pulse width control circuit 170, first, the pulse width control circuit 170 controls the switch SW1 to be turned on and the switch SW2 to be turned off to output the highest voltage VH as the control signal v_tune into the oscillator 150 to generate the output frequency signal ck_out having the highest frequency. Next, the frequency divider 310 performs a frequency dividing operation on the output frequency signal ck_out to generate a frequency-divided output frequency signal ck_out', wherein the divisor of the frequency divider 310 may be "8" in the present embodiment. The counter 320 then counts a clock signal CK ' using the divided output clock signal ck_out ' to generate a first count value, wherein the clock signal CK ' may be obtained by dividing the reference clock signal ck_ref by a divider (e.g., having a divisor of "128") in the present embodiment. At this time, the first count value received by the calculation circuit 330 may reflect the highest frequency value fH of the output frequency signal ck_out corresponding to the highest voltage VH. Next, the pulse width control circuit 170 performs a similar operation to control the switch SW2 to be turned on and the switch SW1 to be turned off, so as to output the lowest voltage VL as the control signal v_tune to the oscillator 150 to generate the output frequency signal ck_out with the lowest frequency, and generates a second count value by the operation of the frequency divider 310 and the counter 320, wherein the second count value may reflect the lowest frequency value fL of the output frequency signal ck_out corresponding to the lowest voltage VL. Then, the calculation circuit 330 can calculate the gain KVCO of the oscillator 150 using the following formula:
KVCO＝(fH-fL)/(VH-VL)……………………………………………………(3)
After calculating the gain KVCO of the oscillator 150, the lookup circuit 340 can determine the pulse width control signal p_code by using a lookup table so that the product of the gain KVCO of the oscillator 150 and the pulse width τ_pul of the pulse signal Vp is a fixed value.
In step 206, the slew rate control circuit 160 generates a slew rate control signal s_code to control the buffer 140 to generate the feedback signal ck_fb according to the phase detection result Vsam' generated by the phase detector 130. In detail, refer to the schematic diagrams of the buffer 140, the phase detector 130, and the slew rate control circuit 160 shown in fig. 4. In fig. 4, the output clock signal ck_out includes the differential signal ck_outp and the differential signal ck_outn, the buffer 140 includes a first buffer 140_1 and a second buffer 140_2, wherein the second buffer 140_2 is a replica circuit (i.e. having the same structure and size) of the first buffer 140_1, and includes buffer circuits 402 and 404 and a plurality of switching resistors R1 and R2 coupled to the supply voltage VDD and the ground voltage; the phase detector 130 includes a first phase detector 130_1 and a second phase detector 130_2, wherein the second phase detector 130_2 is a replica circuit of the first phase detector 130_1, the first phase detector 130_1 includes a plurality of switches SW3 and capacitors C1 and C2 for sampling the feedback signal ck_fb outputted from the first buffer 140_1 by using the reference frequency signal ck_ref to generate a first phase detection result Vsam (including differential signals Vsamp and Vsamn), and the second phase detector 130_2 includes a plurality of switches SW3 'and capacitors C1', C2 'for directly using the feedback signal ck_fb as a second phase detection result Vsam' (including differential signals Vsamp 'and Vsamn'). The slew rate control circuit 160 comprises a peak value detection circuit 410, a comparator 420, a counter 430 and a frequency divider 440, wherein the peak value detection circuit 410 detects the peak value Vpk of the second phase detection result Vsam 'and the comparator 420 compares the peak value Vpk with a reference value Vpkref to generate a comparison result, the counter 430 counts the comparison result by using the frequency divided signal generated by the frequency divider 440 after dividing the reference frequency signal ck_ref to generate a slew rate control signal s_code to control the slew rate in the first buffer 140_1 and the second buffer 140_2, for example, the current flowing into the buffer circuit 402, the buffer circuit 404 in fig. 4 is adjusted or the equivalent resistance value of the switching resistor is adjusted to control the amplitudes of the first phase detection result Vsam and the second phase detection result Vsam' so that the slew rate shown in formula 2 is controlledMaintained at a default value.
It should be noted that the purpose of the first buffer 140_1 and the second buffer 140_2 and the purpose of the first phase detector 130_1 and the second phase detector 130_2 in fig. 4 are to perform the background correction while the sub-sampling pll 100 is operating normally, so as to adjust the slew rates in the first buffer 140_1 and the second buffer 140_2.
As described above, by the slew rate control circuit 160 and the pulse width control circuit 170 in the above embodiments, gain_ SSPD and (kvco_τ_pul) in equation (1) can be set to a fixed value, so that the bandwidth of the sub-sampling pll 100 is not affected by process, voltage, and temperature offset.
It should be noted that the embodiment shown in fig. 1 includes both the slew rate control circuit 160 and the pulse width control circuit 170, but this feature is not a limitation of the present invention, and in other embodiments of the present invention, the sub-sampling pll 100 may include only one of the slew rate control circuit 160 and the pulse width control circuit 170, which can also improve the bandwidth offset problem of the sub-sampling pll 100, and these related variations are all within the scope of the present invention.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
[ Symbolic description ]
100. Subsampling phase-locked loop
110. Pulse signal generating circuit
120. First charge pump
130. Phase detector
130_1 First phase detector
130_2 Second phase detector
140. Buffer device
140_1 First buffer
140_2 Second buffer
150. Oscillator
160. Control circuit for slew rate
170. Pulse width control circuit
180. Coarse frequency selection circuit
192. Phase frequency detector
194. Second charge pump
196. 310, 440 Frequency divider
200. 202, 204, 206 Steps
320. 430 Counter
330. Computing circuit
340. Search circuit
402. 404 Buffer circuit
410. Peak detection circuit
420. Comparator with a comparator circuit
CP, CS, C1, C2, C1', C2' capacitance
RS, R1, R2 resistance
Ck_ref reference frequency signal
CK_out output frequency signal
Ck_outp, ck_outn differential signal
Ck_fb feedback signal
CK div, CK_out' after frequency division to output frequency signal
CK' frequency signal
B_code coarse frequency handle
P_code pulse width control signal
S_code slew rate control signal
SW1, SW2, SW3' switches
Vp pulse signal
Vpkref reference value
V1 first signal
V2 second signal
Vcam first phase detection result
Vcam' second phase detection result
Vsfamp, vsfamp differential signal
Vstart ', vsamn' differential signals
V_tune control signal
VH maximum voltage
VL minimum voltage
VDD supply voltage
KVCO gain.
Claims (8)
1. A sub-sampling phase-locked loop, comprising:
a first phase detector for sampling a feedback signal using a reference frequency signal to generate a first phase detection result;
the first charge pump is coupled to the first phase detector and is used for generating a first signal according to the first phase detection result and a pulse signal;
An oscillator coupled to the first charge pump for generating an output frequency signal according to the first signal; and
The first buffer is coupled to the oscillator and used for receiving the output frequency signal and generating the feedback signal and generating the slew rate of the feedback signal according to a slew rate control signal;
A pulse signal generating circuit for generating the pulse signal according to the reference frequency signal; and
A pulse width control circuit for generating a pulse width control signal to the pulse signal generating circuit according to the output frequency signal to control the pulse width of the pulse signal;
The frequency divider is used for performing frequency division operation on the output frequency signal to generate a frequency-divided output frequency signal;
a phase frequency detector for receiving the reference frequency signal and the frequency-divided output frequency signal to generate a phase frequency detection result; and
A second charge pump coupled to the phase frequency detector for generating a second signal according to the phase frequency detection result;
the oscillator generates an output frequency signal according to the first signal and the second signal.
2. The sub-sampling pll according to claim 1, wherein the pwm control circuit generates a plurality of first signals having different voltage levels to the oscillator during a calibration phase, so that the oscillator generates a plurality of output frequency signals having different frequencies, calculates a gain of the oscillator according to the plurality of first signals and the plurality of output frequency signals, and determines a pwm of the pulse signal according to the gain of the oscillator.
3. The sub-sampling pll according to claim 2, wherein the pulse width control circuit determines the pulse width of the pulse signal according to the gain of the oscillator so that the product of the gain of the oscillator and the pulse width of the pulse signal is a default value.
4. A sub-sampling phase-locked loop, comprising:
a first phase detector for sampling a feedback signal using a reference frequency signal to generate a first phase detection result;
A pulse signal generating circuit for generating a pulse signal according to the reference frequency signal;
The first charge pump is coupled to the phase detector and used for generating a control signal according to the phase detection result and the pulse signal;
An oscillator coupled to the first charge pump for generating an output frequency signal according to the control signal;
the first buffer is coupled to the oscillator and used for receiving the output frequency signal and generating the feedback signal and generating the slew rate of the feedback signal according to a slew rate control signal;
A pulse width control circuit for generating a pulse width control signal to the pulse signal generating circuit according to the output frequency signal to control the pulse width of the pulse signal;
The second buffer is used for receiving the output frequency signal and generating another feedback signal according to the slew rate control signal;
A second phase detector for sampling the other feedback signal using the reference frequency signal to generate a second phase detection result; and
A slew rate control circuit for generating the slew rate control signal according to the second phase detection result.
5. The sub-sampling pll according to claim 4, wherein the pwm control circuit generates a plurality of control signals having different voltage levels to the oscillator during a calibration phase, so that the oscillator generates a plurality of output frequency signals having different frequencies, calculates a gain of the oscillator according to the plurality of control signals and the plurality of output frequency signals, and determines a pwm of the pulse signal according to the gain of the oscillator.
6. A sub-sampling phase-locked loop, comprising:
a first phase detector for sampling a feedback signal using a reference frequency signal to generate a first phase detection result;
the first charge pump is coupled to the first phase detector and is used for generating a first signal according to the first phase detection result and a pulse signal;
An oscillator coupled to the first charge pump for generating an output frequency signal according to the first signal; and
The first buffer is coupled to the oscillator and used for receiving the output frequency signal and generating the feedback signal and generating the slew rate of the feedback signal according to a slew rate control signal;
A second buffer for receiving the output frequency signal and generating another feedback signal according to the slew rate control signal;
A second phase detector for sampling the other feedback signal using the reference frequency signal to generate a second phase detection result; and
A slew rate control circuit for generating the slew rate control signal according to the second phase detection result.
7. The sub-sampling phase-locked loop of claim 6, wherein the second buffer is a replica of the first buffer and the second phase detector is a replica of the first phase detector.
8. The subsampled phase locked loop of claim 6, wherein the slew rate control circuit detects a peak of the second phase detection result to generate the slew rate control signal.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521508A (en) * | 2008-02-29 | 2009-09-02 | 瑞昱半导体股份有限公司 | Multi-loop phase-locked loop device |
| CN108471309A (en) * | 2018-02-12 | 2018-08-31 | 中国科学院上海微系统与信息技术研究所 | A kind of lock detecting circuit for phaselocked loop |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080208541A1 (en) * | 2007-02-27 | 2008-08-28 | International Business Machines Corporation | Method and Enhanced Phase Locked Loop Circuits for Implementing Effective Testing |
| KR100792044B1 (en) * | 2007-05-30 | 2008-01-04 | 인하대학교 산학협력단 | Spread Spectrum Clock Generator |
| CN102055467B (en) * | 2009-11-05 | 2013-02-06 | 晨星软件研发(深圳)有限公司 | Phase Locked Loop and Its Related Methods |
| US9225353B2 (en) * | 2011-06-27 | 2015-12-29 | Syntropy Systems, Llc | Apparatuses and methods for linear to discrete quantization conversion with reduced sampling-variation errors |
| EP3312996A1 (en) * | 2015-01-28 | 2018-04-25 | Huawei Technologies Co., Ltd. | Sub-sampling phase-locked loop |
| EP3059857B1 (en) * | 2015-02-17 | 2021-11-03 | Nxp B.V. | Time to digital converter and phase locked loop |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521508A (en) * | 2008-02-29 | 2009-09-02 | 瑞昱半导体股份有限公司 | Multi-loop phase-locked loop device |
| CN108471309A (en) * | 2018-02-12 | 2018-08-31 | 中国科学院上海微系统与信息技术研究所 | A kind of lock detecting circuit for phaselocked loop |
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