CN112736035A - Method for manufacturing semiconductor device - Google Patents
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- CN112736035A CN112736035A CN201910971630.6A CN201910971630A CN112736035A CN 112736035 A CN112736035 A CN 112736035A CN 201910971630 A CN201910971630 A CN 201910971630A CN 112736035 A CN112736035 A CN 112736035A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明涉及一种半导体器件的制作方法。该方法包括在存储单元阵列区和周边电路区中的第一绝缘介质层中定义出源/漏接触孔隔离沟槽；形成与第一绝缘介质层表面齐平的第二绝缘介质层；在存储单元阵列区和周边电路区表面形成图案转移层分步图形化存储单元阵列区的图案转移层和周边电路区的图案转移层，形成存储单元阵列区待转移图形和周边电路区待转移图形，且存储单元阵列区待转移图形和周边电路区待转移图形之间存在正高度差；以存储单元阵列区待转移图形和周边电路区待转移图形为窗口，去除相邻源/漏接触孔隔离沟槽之间的以及周边电路区中的第一绝缘介质层，在存储单元阵列区形成源/漏接触孔图形，并在周边电路区形成源/漏接触孔图形。
The present invention relates to a manufacturing method of a semiconductor device. The method includes defining source/drain contact hole isolation trenches in a first insulating medium layer in a memory cell array region and a peripheral circuit region; forming a second insulating medium layer flush with the surface of the first insulating medium layer; A pattern transfer layer is formed on the surface of the cell array area and the peripheral circuit area by stepwise patterning the pattern transfer layer in the memory cell array area and the pattern transfer layer in the peripheral circuit area to form the pattern to be transferred in the memory cell array area and the pattern to be transferred in the peripheral circuit area, and There is a positive height difference between the pattern to be transferred in the memory cell array area and the pattern to be transferred in the peripheral circuit area; the pattern to be transferred in the memory cell array area and the pattern to be transferred in the peripheral circuit area are used as windows, and the adjacent source/drain contact hole isolation trenches are removed The first insulating medium layer in the middle and in the peripheral circuit area forms a source/drain contact hole pattern in the memory cell array area, and forms a source/drain contact hole pattern in the peripheral circuit area.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a manufacturing method of a semiconductor device.
Background
With the continuous reduction of the critical dimension of semiconductor memories, the integration level of device structures is increasing, and especially in the manufacturing process of Dynamic Random Access Memories (DRAM) with a critical dimension smaller than 20nm, the requirements on the size of source/drain contact holes and the process technology are also increasing. The polysilicon filled in the source/drain contact hole is in good contact with the active region, so that the resistance value of the capacitor connecting line can be greatly reduced, and the performance of the device is improved.
In the prior art, a layer of photoresist covers the peripheral area, and then the sacrificial oxide material in the storage area is removed by an acid washing method, so that a source/drain contact hole is formed. However, in the process of removing the sacrificial oxide material by the acid washing method, since acid has strong chemical property, the acid reacts with the photoresist in the peripheral region, and the generated by-products fall into the formed source/drain contact holes, so that the filled polysilicon has poor contact with the active region, the resistance of the capacitor connecting wire is increased, and the performance of the device is affected.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor device, which aims to solve the problem of poor contact between a capacitance connecting line and an active region in the conventional semiconductor device.
The embodiment of the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a memory cell array area and a peripheral circuit area;
forming a first insulating medium layer in the memory cell array area and the peripheral circuit area, patterning the first insulating medium layer in the memory cell array area, and defining a source/drain contact hole isolation groove;
forming a second insulating medium layer, wherein the second insulating medium layer fills the source/drain contact hole isolation diagram groove and is flush with the surface of the first insulating medium layer;
forming a pattern transfer layer on the surfaces of the memory cell array area and the peripheral circuit area;
step-by-step patterning the pattern transfer layer of the memory cell array area and the pattern transfer layer of the peripheral circuit area to form a pattern to be transferred of the memory cell array area and a pattern to be transferred of the peripheral circuit area, wherein a positive height difference exists between the pattern to be transferred of the memory cell array area and the pattern to be transferred of the peripheral circuit area;
and taking the pattern to be transferred in the memory cell array area and the pattern to be transferred in the peripheral circuit area as windows, removing the first insulating medium layer between the adjacent source/drain contact hole isolation grooves and the first insulating medium layer in the peripheral circuit area to form a source/drain contact hole pattern in the memory cell array area and a source/drain contact hole pattern in the peripheral circuit area.
In one embodiment, the pattern transfer layer includes a hard mask layer and an anti-reflective coating over the hard mask layer.
In one embodiment, step-patterning the pattern transfer layer of the memory cell array region and the pattern transfer layer of the peripheral circuit region to form a memory cell array region to-be-transferred pattern and a peripheral circuit region to-be-transferred pattern includes:
forming a first photoresist layer on the anti-reflection coating, performing a first photoetching process, and patterning the anti-reflection coating to form anti-reflection coating patterns in the memory cell array area and the peripheral circuit area;
forming a second photoresist layer, performing a second photoetching process, and performing patterned etching on the second photoresist layer to expose the anti-reflection coating pattern in the peripheral circuit region;
etching the hard mask layer in the peripheral circuit area to transfer the anti-reflection coating pattern in the peripheral circuit area into the hard mask layer to form a pattern to be transferred in the peripheral circuit area;
and removing the second photoresist layer to expose the anti-reflection coating pattern in the memory cell array area and form a pattern to be transferred in the memory cell array area.
In one embodiment, the pattern in the second photoresist layer completely overlaps the anti-reflective coating pattern within the peripheral circuit region.
In one embodiment, etching the hard mask layer in the peripheral circuit region includes:
and etching the hard mask layer in the peripheral circuit region by using the anti-reflection coating pattern as a mask through a dry etching process.
In one embodiment, the etching selection ratio of the first insulating medium layer to the second insulating medium layer ranges from 1: 1 to 1: 10.
in one embodiment, the first insulating medium layer comprises a laminated structure composed of two insulating media.
In one embodiment, a conductive layer is formed in the source/drain contact hole patterns of the memory cell array region and the peripheral circuit region, and source/drain contact hole wires are formed.
In one embodiment, forming a conductive layer within the source/drain contact hole pattern, forming the source/drain contact hole conductive line, includes:
filling a non-metal conducting layer in the source/drain contact hole pattern, and etching back the non-metal conducting layer to enable the top surface of the non-metal conducting layer to be lower than the top surface of the source/drain contact hole pattern;
and filling a metal conducting layer in the source/drain contact hole pattern, wherein the metal conducting layer is positioned on the top surface of the nonmetal conducting layer, and the metal conducting layer and the nonmetal conducting layer jointly form a source/drain contact hole lead.
In one embodiment, the source/drain contact hole pattern comprises a capacitive contact hole pattern.
In summary, in the method for manufacturing a semiconductor device provided by the present invention, source/drain contact hole isolation trenches are defined in the first insulating medium layer in the memory cell array region, a second insulating medium layer is formed to fill the source/drain contact hole isolation trenches, a pattern transfer layer is formed on the surfaces of the memory cell array region and the peripheral circuit region, the pattern transfer layer in the memory cell array region and the pattern transfer layer in the peripheral circuit region are patterned step by step, a pattern to be transferred in the memory cell array region and a pattern to be transferred in the peripheral circuit region are formed, a positive height difference exists between the pattern to be transferred in the memory cell array region and the pattern to be transferred in the peripheral circuit region, and finally the first insulating medium layer between adjacent source/drain contact hole isolation trenches and the peripheral circuit region are removed using the pattern to be transferred in the memory cell array region and the pattern to be transferred in the peripheral circuit region as windows And the first insulating medium layer in the circuit area is used for forming a source/drain contact hole pattern in the memory cell array area and forming a source/drain contact hole pattern in the peripheral circuit area. According to the invention, the pattern to be transferred in the memory cell array area and the pattern to be transferred in the peripheral circuit area are formed step by step, then the source/drain contact hole pattern is formed in the memory cell array area synchronously, and the source/drain contact hole pattern is formed in the peripheral circuit area, so that the condition that PR residues fall off due to acid washing in the source/drain contact hole pattern is avoided, the filled conductive layer can be well contacted with the active area, the resistance value of a lead of the source/drain contact hole is reduced, and the problem that the first insulating medium layer in the range of the peripheral circuit area is damaged due to acid washing is avoided. In addition, the invention utilizes the photoetching technology to define the mask patterns of the source/drain contact hole patterns in the memory cell array area and the peripheral circuit area together, thereby simplifying the process flow for manufacturing the semiconductor device.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of defects present in a source/drain contact hole pattern formed using a conventional process;
fig. 4 is a schematic structural view of the source/drain contact hole filled isolation trench according to an embodiment of the present invention;
FIG. 5 is a flowchart of a method of forming a pattern transfer layer according to an embodiment of the present invention;
fig. 6 is a flowchart of a method for forming a source/drain contact hole conductive line according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 1 and fig. 2, an embodiment of the invention provides a method for manufacturing a semiconductor device, including:
step S110, providing a substrate 100, wherein the substrate 100 has a memory cell array region a1 and a peripheral circuit region a 2;
step S120, forming a first insulating dielectric layer 300 in the memory cell array region a1 and the peripheral circuit region a2, patterning the first insulating dielectric layer 300 in the memory cell array region a1, and defining a source/drain contact hole isolation trench GL;
step S130, forming a second insulating medium layer 400, wherein the second insulating medium layer 400 fills the source/drain contact hole isolation trench and is flush with the surface of the first insulating medium layer 300;
step S140 of forming a pattern transfer layer 500 on the surfaces of the memory cell array region a1 and the peripheral circuit region a 2;
step S150, step-patterning the pattern transfer layer 500 in the memory cell array region a1 and the pattern transfer layer 500 in the peripheral circuit region a2 to form a pattern to be transferred in the memory cell array region and a pattern to be transferred in the peripheral circuit region, where a positive height difference exists between the pattern to be transferred in the memory cell array region and the pattern to be transferred in the peripheral circuit region;
step S160, with the pattern to be transferred in the memory cell array region and the pattern to be transferred in the peripheral circuit region as windows, removing the first insulating medium layer 300 between the adjacent source/drain contact hole isolation trenches GL and the first insulating medium layer 300 in the peripheral circuit region, so as to form a source/drain contact hole pattern T1 in the memory cell array region, and form a source/drain contact hole pattern T2 in the peripheral circuit region.
Referring to fig. 3, in the conventional semiconductor process, a photoresist 810 is covered on the peripheral circuit region a2, and then the sacrificial oxide 820 in the memory cell array region a1 is removed by acid cleaning, thereby forming a source/drain contact hole pattern T1. Then, a source/drain contact hole pattern T2 is formed in the peripheral circuit region a2 by a subsequent process. It can be understood that, during the process of removing the sacrificial oxide material by the acid cleaning method, since the acid has a strong chemical property, the acid reacts with the photoresist of the peripheral circuit region a2 to generate by-products 830 similar to a ball shape and drops into the formed source/drain contact hole pattern T1, which causes poor contact between the filled polysilicon and the active region, increases the resistance of the capacitor connecting wires, and affects the performance of the device. Meanwhile, due to the poor acid resistance of the photoresist 810, the acid may penetrate into the peripheral circuit region a2 through the interface between the photoresist and the underlying material, causing damage to the underlying sacrificial oxide 820.
In this embodiment, a pattern transfer layer is formed on the surfaces of the memory cell array area a1 and the peripheral circuit area a2, then a pattern to be transferred in the memory cell array area and a pattern to be transferred in the peripheral circuit area are formed step by step, a source/drain contact hole pattern T1 is formed in the memory cell array area, and a source/drain contact hole pattern T2 is formed in the peripheral circuit area, so that a situation that PR residues fall off due to acid washing in the source/drain contact hole pattern T1 is avoided, it is ensured that the filled conductive layer can be well contacted with an active area, the resistance of a capacitive contact wire is reduced, and meanwhile, the problem that the acid washing damages the first insulating medium layer 300 in the peripheral circuit area a2 is avoided. In addition, in the present embodiment, the source/drain contact hole patterns T1 and T2 are simultaneously formed in the memory cell array region a1 and the peripheral circuit region a2 by the same etching process, which simplifies the process flow of the device.
In addition, the substrate 100 may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate, but is not limited thereto.
In one embodiment, the first insulating medium layer 300 includes a stacked structure of two insulating media.
In this embodiment, two insulating materials are sequentially deposited on the substrate 100 to form a first insulating layer 310 and a second insulating layer 320, and the first insulating layer 310 and the second insulating layer 320 are stacked to form the first insulating dielectric layer 300; wherein the first insulating layer 310 is disposed between the second insulating layer 320 and the substrate 100. In this embodiment, the insulating material may include silicon oxide, silicon oxynitride, silicon nitride, or the like, in which the first insulating layer 310 is formed using silicon nitride and the second insulating layer 320 is formed using silicon oxide. The process for forming the first insulating dielectric layer 300 may include a deposition process suitable for the material to be deposited. For example, the formation process may include Chemical Vapor Deposition (CVD), low pressure CVD (lpcvd), plasma enhanced CVD (pecvd), Atomic Layer Deposition (ALD), and plasma enhanced ALD (peald).
In one embodiment, the etching selection ratio of the first insulating dielectric layer 300 to the second insulating dielectric layer 400 is in a range of 1: 1 to 1: 10.
in this embodiment, the etching selection ratio of the first insulating dielectric layer 300 to the second insulating dielectric layer 400 is in a range of 1: 5 to 1: and 10, removing a part of the first insulating medium layer by utilizing the etching selection ratio of the first insulating medium layer 300 and the second insulating medium layer 400 in a self-aligned manner to form a source/drain contact hole pattern. It can be understood that when the first insulating dielectric layer 300 and the second insulating dielectric layer 400 are formed of materials having etching selectivity, the first insulating dielectric layer 300 may be rapidly etched by dry etching using a suitable etching gas, and the second insulating dielectric layer 400 may be etched at a relatively slow speed, even the second insulating dielectric layer 400 may not be affected by etching, and the second insulating dielectric layer 400 may be removed by dry etching instead of wet clean, so as to effectively avoid the problem of internal defects in the source/drain contact holes caused by wet etching, and define the mask patterns of the source/drain contact hole patterns in the memory cell array region a1 and the peripheral circuit region a2 together by using a photolithography process, thereby further simplifying the process flow.
In one embodiment, the second insulating layer 320 is made of silicon oxide, and the first insulating layer 310 and the second insulating dielectric layer 400 are made of silicon nitride. In addition, other insulating materials having an etching ratio with respect to silicon oxide, such as silicon oxynitride material, may be selected to form the second insulating dielectric layer 400. It is understood that silicon oxide materials, silicon nitride materials, and silicon oxynitride materials are commonly used to form dielectric layers. In the etching process, a small amount of hydrogen is doped into fluorine-based etching gas, so that the etching rate of the silicon oxide material is improved, the silicon oxide material has a higher etching rate relative to the silicon nitride material/silicon oxynitride material, the fluorine-based etching gas has good anisotropy, and the etching rate in the longitudinal direction is far greater than that in the transverse direction, so that the second insulating medium layer 400 is hardly etched when the first insulating layer 310 is etched, the second insulating medium layer 400 is guaranteed to be hardly damaged, and the electric leakage phenomenon is prevented.
Referring to fig. 2 and 4 together, in one embodiment, the step of forming the second insulating dielectric layer 400 includes:
depositing an insulating material to form the second insulating dielectric layer 400 for filling the source/drain contact hole isolation trenches GL;
the second insulating medium layer 400 is etched back or chemically mechanically polished to expose the top of the first insulating medium layer 300, and the top surface of the first insulating medium layer 300 is flush with the second insulating medium layer 400.
In this embodiment, an insulating material is deposited in the source/drain contact hole isolation trench GL to form the second insulating medium layer 400 filling the source/drain contact hole isolation trench GL, and then the second insulating medium layer 400 is planarized by an etching or chemical mechanical polishing process until the top of the first insulating medium layer 300 is exposed, and the top surface of the first insulating medium layer 300 is flush with the second insulating medium layer 400. The process for forming the second insulating dielectric layer 400 may include a deposition process suitable for the material to be deposited. For example, the formation process may include Chemical Vapor Deposition (CVD), low pressure CVD (lpcvd), plasma enhanced CVD (pecvd), Atomic Layer Deposition (ALD), plasma enhanced ALD (peald), and the like.
In one embodiment, the pattern transfer layer 500 includes a hard mask layer 510 and an anti-reflective coating 520, the anti-reflective coating 520 being located on the hard mask layer 510.
In this embodiment, when the hard mask layer 510 and the anti-reflection coating 520 are used to form the pattern transfer layer 500, the pattern to be transferred in the memory cell array region and the pattern to be transferred in the peripheral circuit region having a positive height difference may be formed by performing a layered etching process.
In one embodiment, the hard mask layer 510 is formed using a carbon material and the anti-reflective coating 520 is formed using a silicon-doped anti-reflective material. It will be appreciated that when the silicon-doped anti-reflective material is used to form the anti-reflective coating 520, the anti-reflective coating 520 can function as both an anti-reflective coating and a mask layer to control the reflection from the surface of the photoresist, so that the mask layer pattern can be transferred with high fidelity during the photolithography process. In this embodiment, the main components of the anti-reflective coating 520 are a resin capable of crosslinking, a thermal acid generator, a surfactant, and a solvent. Meanwhile, the hard mask layer 510 formed using a carbon material may also play a role of antireflection, the main component of which is an organic polymer having a high carbon content.
Referring to fig. 2 and 5 together, in one embodiment, the step-by-step patterning the pattern transfer layer of the memory cell array region and the pattern transfer layer of the peripheral circuit region to form a pattern to be transferred in the memory cell array region and a pattern to be transferred in the peripheral circuit region includes:
forming a first photoresist layer 530a on the anti-reflective coating layer 520, performing a first photolithography process, and patterning the anti-reflective coating layer 520, such that an anti-reflective coating pattern is formed in the memory cell array region a1 and the peripheral circuit region a 2;
forming a second photoresist layer 530b, performing a second photolithography process, and performing a patterned etching on the second photoresist layer 530b to expose the anti-reflective coating pattern in the peripheral circuit region;
etching the hard mask layer 510 in the peripheral circuit region to transfer the anti-reflection coating pattern in the peripheral circuit region into the hard mask layer 510, and forming a pattern to be transferred in the peripheral circuit region;
and removing the second photoresist layer 530b to expose the anti-reflection coating pattern in the memory cell array region, thereby forming a pattern to be transferred in the memory cell array region.
In this embodiment, a first photoresist layer 530a is formed on the surface of the anti-reflective coating 520, and then a laser is used to irradiate the first photoresist layer 530a through a mask to cause a chemical reaction of the photoresist in the exposed region; and then, the photoresist in the exposed area or the unexposed area (the former is called positive photoresist, and the latter is called negative photoresist) is dissolved and removed by a developing technology, the pattern on the photomask is transferred into the first photoresist layer 530a, and then the antireflection coating 520 is etched by taking the first photoresist layer 530a as a mask, so that antireflection coating patterns are formed in the memory cell array area a1 and the peripheral circuit area a 2. Similarly, a second photoresist layer 530b is formed on the surface of the anti-reflection layer 520, and a second photolithography process is performed to pattern the second photoresist layer 530b to expose the anti-reflection coating pattern in the peripheral circuit region, which is not repeated herein.
In one embodiment, the pattern in the second photoresist layer 530b completely overlaps the anti-reflective coating pattern in the peripheral circuit area a 2.
It is understood that the source/drain contact hole pattern T1 in the memory cell array region a1 and the source/drain contact hole pattern T2 in the peripheral circuit region a2 have a certain height difference, that is, a second mask pattern completely overlapping with the anti-reflective coating pattern in the peripheral circuit region a2 is formed in the second photoresist layer 530b through a second photolithography process, and then the hard mask layer 510 is etched using the second photoresist layer 530b as a mask to transfer the anti-reflective coating pattern in the peripheral circuit region a2 into the hard mask layer 510, so as to reduce the thickness of the film layer in the region corresponding to the anti-reflective coating pattern in the peripheral circuit region a2, and finally, the depth of the source/drain contact hole pattern T2 in the peripheral circuit region a2 is different from the depth of the source/drain contact hole pattern T1 in the memory cell array region a 1. The dry etching (or simply referred to as dry etching) process for forming the source/drain contact hole pattern T1 and the source/drain contact hole pattern T2 has the same etching speed in the longitudinal direction at each position, so that the first insulating dielectric layer 300 in the peripheral circuit region a2 is etched before the first insulating dielectric layer 300 in the memory cell array region a1 in the etching process, and then the substrate 100 is continuously etched, thereby forming the source/drain contact hole pattern T1 and the source/drain contact hole pattern T2 with different depths, and simplifying the manufacturing process of the device.
In one embodiment, etching the hard mask layer 510 in the peripheral circuit region a2 includes:
and etching the hard mask layer in the peripheral circuit region by using the anti-reflection coating pattern as a mask through a dry etching process.
It can be understood that the etchant used in the dry etching process is plasma, and is a process that utilizes the reaction of the plasma and the surface thin film to form a volatile substance, or directly bombards the surface of the thin film to corrode the thin film, so as to implement anisotropic etching.
In one embodiment, the hard mask 510 is formed using a carbide material and the anti-reflective coating 520 is formed using a silicon-doped anti-reflective material. It can be appreciated that when the silicon-doped anti-reflective material is used to form the anti-reflective coating 520, the anti-reflective coating 520 can simultaneously function as an anti-reflective coating and a mask layer to control the reflection of the photoresist surface, so that the mask layer pattern can be transferred with high fidelity during the photolithography process. In this embodiment, the main components of the anti-reflective coating 520 are a resin capable of crosslinking, a thermal acid generator, a surfactant, and a solvent. Meanwhile, the hard mask 510 formed of a carbide material, the main component of which is an organic polymer having a high carbon content, may also play a role of antireflection.
Referring to fig. 6, in one embodiment, the manufacturing method further includes:
a conductive layer is formed in the source/drain contact hole patterns of the memory cell array region a1 and the peripheral circuit region a2, and a source/drain contact hole conduction line 900 is formed.
Specifically, a non-metal conductive layer 910 is formed in the source/drain contact hole pattern, and the non-metal conductive layer 910 is etched back, so that the top surface of the non-metal conductive layer 910 is lower than the top surface of the source/drain contact hole pattern;
filling a metal conducting layer 920 in the source/drain contact hole pattern, wherein the metal conducting layer 920 is located on the top surface of the non-metal conducting layer 910, and the metal conducting layer 920 and the non-metal conducting layer 910 together form a source/drain contact hole wire 900.
It is understood that the source/drain contact hole conductors 900 include the use of a non-metallic conductive layer 910 and a metallic conductive layer 920. In this embodiment, to simplify the process flow, the same non-metal conductive material is used, and the non-metal conductive layer 910 of the source/drain contact hole conductive line in the memory cell array region a1 and the peripheral circuit region a2 is fabricated by the same process. In particular, polycrystalline silicon, amorphous silicon or other non-metallic conductive materials containing silicon or not containing silicon may be used. And, using the same metal conductive material, and using the same process to fabricate the metal conductive layer 920 of the source/drain contact hole conductive lines in the memory cell array region a1 and the peripheral circuit region a2, where the metal conductive layer 920 may specifically be made of aluminum, tungsten, copper, titanium-aluminum alloy, or other suitable low-resistance metal conductive material. In this embodiment, the non-metal conductive layer 910 is made of polysilicon, and the metal conductive layer 920 is made of tungsten.
In one embodiment, the source/drain contact hole pattern comprises a capacitive contact hole pattern.
To sum up, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, a source/drain contact hole isolation trench GL is defined in the first insulating medium layer 300 in the memory cell array region a1, a second insulating medium layer 400 is formed to fill the source/drain contact hole isolation trench, a pattern transfer layer 500 is formed on the surfaces of the memory cell array region a1 and the peripheral circuit region a2, the pattern transfer layer in the memory cell array region and the pattern transfer layer 500 in the peripheral circuit region are patterned step by step, a pattern to be transferred in the memory cell array region and a pattern to be transferred in the peripheral circuit region are formed, a positive height difference exists between the pattern to be transferred in the memory cell array region and the pattern to be transferred in the peripheral circuit region, and finally the pattern to be transferred in the memory cell array region and the pattern to be transferred in the peripheral circuit region are used as a window, the first insulating medium layer 300 between the adjacent source/drain contact hole isolation trenches GL and the first insulating medium layer 300 in the peripheral circuit region are removed to form a source/drain contact hole pattern T1 in the memory cell array region and a source/drain contact hole pattern T2 in the peripheral circuit region. In the embodiment of the invention, the pattern to be transferred in the memory cell array area and the pattern to be transferred in the peripheral circuit area are formed step by step, then the source/drain contact hole pattern is formed in the memory cell array area synchronously, and the source/drain contact hole pattern is formed in the peripheral circuit area, so that the condition that PR residues fall off due to acid cleaning in the source/drain contact hole pattern is avoided, filled polycrystalline silicon can be ensured to be in good contact with an active area, the resistance value of a lead of the source/drain contact hole is reduced, and the problem that the acid cleaning damages a first insulating medium layer 300 in the range of the peripheral circuit area A2 is avoided. In addition, the embodiment of the invention utilizes the photoetching process to define the mask patterns of the source/drain contact hole patterns in the memory cell array area and the peripheral circuit area together, thereby simplifying the process flow for manufacturing the device.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a memory cell array area and a peripheral circuit area;
forming a first insulating medium layer in the memory cell array area and the peripheral circuit area, patterning the first insulating medium layer in the memory cell array area, and defining a source/drain contact hole isolation groove;
forming a second insulating medium layer, wherein the second insulating medium layer fills the source/drain contact hole isolation groove and is flush with the surface of the first insulating medium layer;
forming a pattern transfer layer on the surfaces of the memory cell array area and the peripheral circuit area;
step-by-step patterning the pattern transfer layer of the memory cell array area and the pattern transfer layer of the peripheral circuit area to form a pattern to be transferred of the memory cell array area and a pattern to be transferred of the peripheral circuit area, wherein a positive height difference exists between the pattern to be transferred of the memory cell array area and the pattern to be transferred of the peripheral circuit area;
and taking the pattern to be transferred in the memory cell array area and the pattern to be transferred in the peripheral circuit area as windows, removing the first insulating medium layer between the adjacent source/drain contact hole isolation grooves and the first insulating medium layer in the peripheral circuit area to form a source/drain contact hole pattern in the memory cell array area and a source/drain contact hole pattern in the peripheral circuit area.
2. The method of claim 1, wherein the pattern transfer layer comprises a hard mask layer and an anti-reflective coating layer, the anti-reflective coating layer being located on the hard mask layer.
3. The method of manufacturing of claim 2, wherein step-patterning the pattern transfer layer of the memory cell array region and the pattern transfer layer of the peripheral circuit region to form a memory cell array region to-be-transferred pattern and a peripheral circuit region to-be-transferred pattern comprises:
forming a first photoresist layer on the anti-reflection coating, performing a first photoetching process, and patterning the anti-reflection coating to form anti-reflection coating patterns in the memory cell array area and the peripheral circuit area;
forming a second photoresist layer, performing a second photoetching process, and performing patterned etching on the second photoresist layer to expose the anti-reflection coating pattern in the peripheral circuit region;
etching the hard mask layer in the peripheral circuit area to transfer the anti-reflection coating pattern in the peripheral circuit area into the hard mask layer to form a pattern to be transferred in the peripheral circuit area;
and removing the second photoresist layer to expose the anti-reflection coating pattern in the memory cell array area and form a pattern to be transferred in the memory cell array area.
4. The method of claim 3, wherein the pattern in the second photoresist layer completely overlaps the anti-reflective coating pattern in the peripheral circuit region.
5. The method of claim 3, wherein etching the hard mask layer in the peripheral circuit region comprises:
and etching the hard mask layer in the peripheral circuit region by using the anti-reflection coating pattern as a mask through a dry etching process.
6. The method of claim 1, wherein the range of the etching selectivity of the first insulating dielectric layer to the second insulating dielectric layer is 1: 1 to 1: 10.
7. the method of claim 1, wherein the first dielectric layer comprises a stacked structure of two dielectric layers.
8. The method of manufacturing of claim 1, further comprising:
and forming a conductive layer in the source/drain contact hole patterns of the memory cell array area and the peripheral circuit area to form a source/drain contact hole lead.
9. The method of claim 8, wherein forming a conductive layer within the source/drain contact hole pattern to form the source/drain contact hole line comprises:
filling a non-metal conducting layer in the source/drain contact hole pattern, and etching back the non-metal conducting layer to enable the top surface of the non-metal conducting layer to be lower than the top surface of the source/drain contact hole pattern;
and filling a metal conducting layer in the source/drain contact hole pattern, wherein the metal conducting layer is positioned on the top surface of the nonmetal conducting layer, and the metal conducting layer and the nonmetal conducting layer jointly form a source/drain contact hole lead.
10. The method of any of claims 1-9, wherein the source/drain contact hole pattern comprises a capacitive contact hole pattern.
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