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CN112736028A - Display panel - Google Patents

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Publication number
CN112736028A
CN112736028A CN201910977058.4A CN201910977058A CN112736028A CN 112736028 A CN112736028 A CN 112736028A CN 201910977058 A CN201910977058 A CN 201910977058A CN 112736028 A CN112736028 A CN 112736028A
Authority
CN
China
Prior art keywords
display panel
substrate
layer
single crystal
crystal wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910977058.4A
Other languages
Chinese (zh)
Inventor
赵立新
王富中
张斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Geke Microelectronics Shanghai Co Ltd
Galaxycore Shanghai Ltd Corp
Original Assignee
Geke Microelectronics Shanghai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Geke Microelectronics Shanghai Co Ltd filed Critical Geke Microelectronics Shanghai Co Ltd
Priority to CN201910977058.4A priority Critical patent/CN112736028A/en
Publication of CN112736028A publication Critical patent/CN112736028A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The present invention provides a display panel including: a base plate and/or panel substrate; the single crystal wafer is provided with an epitaxial layer on a first surface, a part of device structures are arranged in the epitaxial layer, the first surface of the single crystal wafer is bonded or attached to the substrate and/or the panel substrate, at least one conductive interconnection layer is arranged on a second surface of the single crystal wafer, and the part of the device structures in the epitaxial layer are connected with the conductive interconnection layer through silicon through holes. According to the display panel, the monocrystalline wafer is adopted to replace an amorphous silicon layer or a polycrystalline silicon layer in the prior art, so that the structural defects of devices are reduced, the imaging quality of the display panel is improved, the yield of the display panel is improved, and the requirement for high performance of the display panel is met.

Description

Display panel
Technical Field
The present invention relates to a display panel.
Background
The display panel can be used in various fields such as a television set, various audio/video systems, a computer monitor device, a navigation terminal device, a portable terminal device, and the like. Various types of display panels are capable of outputting images to the outside using different types of display units. For example, the display unit may be a Liquid Crystal Display (LCD), a Light Emitting Diode (LED), an Organic Light Emitting Diode (OLED), an active matrix OLED (amoled), or the like.
With the rapid development of display technology, the requirements of the current market for display panels are gradually increasing, especially the requirements for miniaturization, low power consumption, low cost, high image quality, and the like are increasing. In the manufacturing method of the display panel in the prior art, an amorphous silicon or polysilicon layer is usually formed on a substrate, then an active region is etched on the amorphous silicon or polysilicon layer after excimer laser crystallization (ELA) processing, device structures such as a source, a drain, a gate channel region and the like are formed in the active region, and at least one conductive interconnection layer and the like are formed on the device structures, so that a complete display panel is formed. Since the device structure is formed in the amorphous silicon or polysilicon layer which may have more defects, it is easy to affect the imaging quality and yield of the display panel.
Disclosure of Invention
The invention aims to provide a display panel, which improves the imaging quality of the display panel, improves the yield of the display panel and meets the requirement on high performance of the display panel.
In view of the above, the present invention provides a display panel including: a base plate and/or panel substrate; the single crystal wafer is provided with an epitaxial layer on a first surface, a part of device structures are arranged in the epitaxial layer, the first surface of the single crystal wafer is bonded or attached to the substrate and/or the panel substrate, at least one conductive interconnection layer is arranged on a second surface of the single crystal wafer, and the part of the device structures in the epitaxial layer are connected with the conductive interconnection layer through silicon through holes.
Preferably, the partial device structure comprises a source electrode, a drain electrode, a grid electrode channel region and a device isolation region.
Preferably, the thickness of the epitaxial layer is 3-5 μm.
Preferably, the material of the panel substrate is polyimide or fluorinated polyimide.
Preferably, the thickness of the panel substrate is 50 to 100 μm.
Preferably, the first surface of the single crystal wafer and the substrate and/or the panel substrate are respectively provided with an oxide layer for bonding.
Preferably, the material of the oxide layer is silicon dioxide.
Preferably, the oxide layers have a thickness of 0.5 to 2 μm, respectively.
Preferably, the material of the conductive interconnection layer is metal or conductive metal compound.
Preferably, the thickness of the conductive interconnection layer is 1 to 2 μm.
Preferably, the substrate is made of glass.
Preferably, the depth of the through silicon via is 5-7 μm.
Compared with the prior art, the display panel provided by the invention has the advantages that the monocrystalline wafer is adopted to replace an amorphous silicon layer or a polycrystalline silicon layer in the prior art, the structural defects of devices are reduced, the imaging quality of the display panel is improved, the yield of the display panel is improved, and the requirement on high performance of the display panel is met.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.
Fig. 1 to 8 are process diagrams illustrating a method for manufacturing a display panel according to the present invention.
In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.
Detailed Description
To solve the above problems in the prior art, the present invention provides a display panel, including: a base plate and/or panel substrate; the single crystal wafer is provided with an epitaxial layer on a first surface, a part of device structures are arranged in the epitaxial layer, the first surface of the single crystal wafer is bonded or attached to the substrate and/or the panel substrate, at least one conductive interconnection layer is arranged on a second surface of the single crystal wafer, and the part of the device structures in the epitaxial layer are connected with the conductive interconnection layer through silicon through holes. According to the display panel, the monocrystalline wafer is adopted to replace an amorphous silicon layer or a polycrystalline silicon layer in the prior art, so that the structural defects of devices are reduced, the imaging quality of the display panel is improved, the yield of the display panel is improved, and the requirement for high performance of the display panel is met.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
The display panel of the present invention will be described in detail with reference to specific embodiments.
Fig. 1 to 8 are process diagrams illustrating a method of manufacturing a display panel according to an embodiment of the present invention.
Referring to fig. 1, a single crystal wafer is provided, preferably comprising a wafer substrate 100 and an epitaxial layer 101 disposed on a first side, the epitaxial layer 101 may have a thickness of 3-5 μm. A portion of the device structure 102 is formed in the epitaxial layer 101, where the portion of the device structure 102 includes, for example, a source, a drain, a gate channel region, and a device isolation region.
Referring to fig. 2, for the case where bonding with the substrate 104 is required in the subsequent step, an oxide layer 103 is preferably formed on the first surface of the single crystal wafer, and specifically, the oxide layer 103 is formed on the surface of the epitaxial layer 101.
Referring to fig. 3, a substrate 104 is provided, and the substrate 104 is made of glass, for example. In the case of a flexible display panel, a panel substrate 105 made of a flexible material such as polyimide or fluorinated polyimide may be formed on the base substrate 104, and the thickness of the panel substrate 105 may be 50 to 100 μm.
For the case where bonding to a single crystal wafer is required in a subsequent step, it is preferable to form the oxide layer 106 on the substrate 104. In the present embodiment, in the case where the panel substrate 105 exists on the base plate 104, the oxide layer 106 is formed on the surface of the panel substrate 105; for other embodiments not shown, in the case that the panel substrate 105 does not exist on the base plate 104, the oxide layer 106 is directly formed on the surface of the base plate 104.
Referring to fig. 4, a first side of the single crystal wafer is bonded or attached to a substrate 104. For the bonding case, the oxide layer 103 on the single crystal wafer provides a better bonding force with the oxide layer 106 on the substrate 104. Preferably, the oxide layers 103 and 106 are made of silicon dioxide, and have a thickness of 0.5-2 μm, respectively, and can be formed by a plasma enhanced chemical vapor deposition process. For the bonding case, the oxide layers 103 and 106 are not required to be formed, and the single crystal wafer and the substrate 104 can provide a good bonding force through an adhesive material such as an adhesive.
In order to solve the problems of warpage, shape and size matching of the single crystal wafer, it is preferable that the single crystal wafer is cut into a plurality of single crystal units, the shape and size of each single crystal unit is consistent with the shape and size of the finally required display panel, and then the first surfaces of the plurality of single crystal units are bonded or attached to the substrate 104 to form the structure shown in fig. 4.
Referring to fig. 5 and fig. 6, the single crystal wafer is thinned from the second side, preferably stopping on the epitaxial layer 101, at least one conductive interconnection layer 107 is formed on the thinned second side, the material of the conductive interconnection layer 107 is preferably metal or conductive metal compound, the thickness is 1-2 μm, and part of the device structure 102 in the epitaxial layer 101 is connected with the conductive interconnection layer 107 through the through silicon via 108. The depth of the through-silicon-via 108 is preferably 5-7 μm.
Referring to fig. 7, in the case where the base plate 104 is not required for the panel substrate 105 requiring only flexibility, the base plate 104 may be thinned and removed after the conductive interconnection layer 107 is formed, and then cut along a cutting line (dot-dash line in the figure) to form a single display panel structure as shown in fig. 8.
As shown in fig. 8, the display panel of the present invention includes: a panel substrate 105 (in the present embodiment shown in fig. 8, only the panel substrate 105 is included; in other embodiments not shown, there may be a case where only the base plate 104 is included or both the panel substrate 105 and the base plate 104 are included). Preferably, the panel substrate 105 is made of polyimide or fluorinated polyimide, the thickness is 50-100 μm, and the substrate 104 is made of glass.
The display panel of the present invention further comprises: and the first side of the single crystal wafer is bonded or attached with the base plate 104 and/or the panel substrate 105, and the second side of the single crystal wafer is provided with at least one conductive interconnection layer 107. Preferably, the conductive interconnection layer 107 is made of metal or conductive metal compound and has a thickness of 1-2 μm.
Wherein, an epitaxial layer 101 is arranged on the first surface of the monocrystalline wafer, and the thickness of the epitaxial layer 101 is preferably 3-5 μm. A partial device structure 102 is disposed in the epitaxial layer 101, and the partial device structure 102 includes a source, a drain, a gate channel region and a device isolation region. Portions of device structure 102 in epitaxial layer 101 are connected to conductive interconnect layer 107 by through-silicon-vias 108.
For the bonding condition, the first surface of the single crystal wafer and the substrate and/or the panel substrate are respectively provided with an oxide layer 103 and an oxide layer 106 for bonding, so as to provide better bonding force. The oxide layers 103 and 106 are made of silicon dioxide and have a thickness of 0.5-2 μm.
In summary, the present invention provides a display panel, including: a base plate and/or panel substrate; the single crystal wafer is provided with an epitaxial layer on a first surface, a part of device structures are arranged in the epitaxial layer, the first surface of the single crystal wafer is bonded or attached to the substrate and/or the panel substrate, at least one conductive interconnection layer is arranged on a second surface of the single crystal wafer, and the part of the device structures in the epitaxial layer are connected with the conductive interconnection layer through silicon through holes. According to the display panel, the monocrystalline wafer is adopted to replace an amorphous silicon layer or a polycrystalline silicon layer in the prior art, so that the structural defects of devices are reduced, the imaging quality of the display panel is improved, the yield of the display panel is improved, and the requirement for high performance of the display panel is met.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.

Claims (12)

1. A display panel, comprising:
a base plate and/or panel substrate;
the single crystal wafer is provided with an epitaxial layer on a first surface, a part of device structures are arranged in the epitaxial layer, the first surface of the single crystal wafer is bonded or attached to the substrate and/or the panel substrate, at least one conductive interconnection layer is arranged on a second surface of the single crystal wafer, and the part of the device structures in the epitaxial layer are connected with the conductive interconnection layer through silicon through holes.
2. The display panel of claim 1, wherein the portion of the device structure comprises a source, a drain, a gate channel region, and a device isolation region.
3. The display panel of claim 1, wherein the epitaxial layer has a thickness of 3-5 μ ι η.
4. The display panel according to claim 1, wherein the panel substrate is made of polyimide or fluorinated polyimide.
5. The display panel according to claim 1, wherein the thickness of the panel substrate is 50 to 100 μm.
6. The display panel according to claim 1, wherein the first surface of the single crystal wafer and the panel substrate and/or the panel substrate are provided with an oxide layer for bonding, respectively.
7. The display panel of claim 6, wherein the oxide layer is silicon dioxide.
8. The display panel according to claim 6, wherein the oxide layers have thicknesses of 0.5 to 2 μm, respectively.
9. The display panel of claim 1, wherein the conductive interconnection layer is made of a metal or a conductive metal compound.
10. The display panel of claim 1, wherein the conductive interconnect layer has a thickness of 1-2 μ ι η.
11. The display panel according to claim 1, wherein the substrate is made of glass.
12. The display panel of claim 1, wherein the through-silicon-via has a depth of 5-7 μ ι η.
CN201910977058.4A 2019-10-15 2019-10-15 Display panel Pending CN112736028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910977058.4A CN112736028A (en) 2019-10-15 2019-10-15 Display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910977058.4A CN112736028A (en) 2019-10-15 2019-10-15 Display panel

Publications (1)

Publication Number Publication Date
CN112736028A true CN112736028A (en) 2021-04-30

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Country Status (1)

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CN (1) CN112736028A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101783314A (en) * 2009-01-21 2010-07-21 台湾积体电路制造股份有限公司 Method of forming an isolation structure and corresponding device
CN102226999A (en) * 2011-05-11 2011-10-26 迈尔森电子（天津）有限公司 Substrate structure and fabrication method thereof
US20170110420A1 (en) * 2015-10-19 2017-04-20 Taiwan Semiconductor Manufacturing Co., Ltd. Trap layer substrate stacking technique to improve performance for rf devices
CN210897243U (en) * 2019-10-15 2020-06-30 格科微电子（上海）有限公司 Display panel

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101783314A (en) * 2009-01-21 2010-07-21 台湾积体电路制造股份有限公司 Method of forming an isolation structure and corresponding device
CN102226999A (en) * 2011-05-11 2011-10-26 迈尔森电子（天津）有限公司 Substrate structure and fabrication method thereof
US20170110420A1 (en) * 2015-10-19 2017-04-20 Taiwan Semiconductor Manufacturing Co., Ltd. Trap layer substrate stacking technique to improve performance for rf devices
CN210897243U (en) * 2019-10-15 2020-06-30 格科微电子（上海）有限公司 Display panel

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