CN112732612A

CN112732612A - Double-side read address event representation transmission protocol circuit

Info

Publication number: CN112732612A
Application number: CN201911033054.7A
Authority: CN
Inventors: 徐江涛; 邹佳伟; 聂凯明; 高静; 查万斌
Original assignee: Tianjin University Marine Technology Research Institute
Current assignee: Tianjin University Marine Technology Research Institute
Priority date: 2019-10-28
Filing date: 2019-10-28
Publication date: 2021-04-30

Abstract

A bilateral read address event representation transmission protocol circuit comprises a row arbiter, a row address encoder, a column arbiter 1, a column arbiter 2, a column address encoder 1, a column address encoder 2, an input 2^jIndividual line request and 2^kColumn request, output includes 2^jIndividual line answering, 2^kThe system comprises an individual column response and 2 event information external output channels, an event output channel 1 and an event output channel 2; the circuit groups the column requests of the circuit array, increases the path of the external output of the protocol circuit, and doubles the circuit speed; the large-scale column request arbiter is divided into two smaller-scale column arbiters, so that the delay of a circuit in column arbitration is reduced, the time for queuing and waiting required by the output units in the same row is reduced, and the accuracy of information contained in output data is improved.

Description

Double-side read address event representation transmission protocol circuit

Technical Field

The present invention relates to the field of integrated circuits, and more particularly to a circuit implementation of an address-event representation transfer protocol for a dual-sided read mode.

Background

Address-event Representation (AER) transport protocol is oneThe novel asynchronous high-speed serial data transmission protocol is suitable for high-speed serial output of a large-scale evened circuit array, and the circuit structure of the novel asynchronous high-speed serial data transmission protocol is shown in figure 1 and comprises a row arbiter, a row address encoder, a column arbiter and a column address encoder. The circuit array has 2^jStripe line request bus and 2^jA bar line reply bus, and 2^kRowbar request bus and 2^kThe columnar response bus is used for interacting with the AER protocol circuit. The operating principle of the AER protocol circuit is as follows: the circuit array generates requests on at least one row request bus; after the AER protocol circuit receives the row requests, the row arbiter sorts the row requests according to the principle of first-in first-out, and sequentially responds signals on the corresponding row response buses according to the sequence, and meanwhile, the row address encoder encodes the row number of the response signal; the circuit array generates a request on at least one column request bus after receiving the row response signal; after the AER protocol circuit receives the column requests, the column arbiter also sequences the row requests according to the principle of first-in first-out, and sequentially responds signals on the corresponding column response buses according to the sequence, and simultaneously, the column address encoder encodes the column number where the response signal is located; after one row response and one column response are completed, the protocol circuit outputs two groups of codes to the outside, the signal transmission process of one unit in the circuit array is completed, and the signal of the next unit is processed. According to the working principle, the AER protocol circuit serially completes the signal transmission process of each unit needing to be output in the circuit array.

The core of the AER protocol circuit is an arbiter, and the arbiter units of 2 to 1 are usually connected into a tree structure to complete the response sorting function. FIG. 2 shows a general formula of (2)ⁿ-1) an n-level binary tree structure composed of arbitration units, the bottom level (i.e. the n-th level) having from-req 0 to-req (2)ⁿ-1) 2 in allⁿA request signal input and from-ack 0 to-ack (2)ⁿ-1) 2 in allⁿAnd outputting the response signal. Each arbitration unit can complete the arbitration work of two simultaneously generated requests of the layer, generates a request signal of the previous layer, and returns a response signal to the next layer according to the arbitration sequence after receiving the response signal returned by the previous layerIn the cell. The top layer (i.e. layer 1) unit of the arbiter transmits the generated request signal to the external circuit, and receives the response signal returned by the external circuit to transmit to the lower layer. If the requests received by the arbitration unit are not generated simultaneously, the arbitration result is generated according to the sequence of the requests.

The existing AER protocol circuit has the defects that each external output unit of the circuit array can only be sequenced through one channel and output in series in the output process, and when a plurality of units in the circuit array need to output externally at the same time, the unselected units can only wait for the output of the unit sequenced before the unit to output externally. Since the accuracy of the event information is determined by the accuracy of the time stamp at the time of the event generation, this latency will cause errors to the output information. Furthermore, the time required for the arbitration process will increase as the number of requests increases, which means that circuit array scaling will result in worse event information accuracy.

When the number of requests is 1, the response delay of the arbiter to the request is

Whereint _reqIndicating the delay time for a request signal to travel one level from the lower level of the arbitration tree to the upper level,t _ackindicating the delay time for an acknowledgment signal to travel one level from the upper level to the lower level of the arbitration tree,t _ack-MEthe delay time of the acknowledgement signal of the arbitration unit at the topmost layer of the arbitration tree is transmitted to the lower layer by one level. And for a full request, the response delay of the arbiter to the last request is

Whereint _swThe delay time of one switching of the acknowledgement signal by each alternative arbiter is referred to,T _prefers to the time each time the arbiter waits for external processing.

It can be seen that as the size of the arbiter continues to grow, the arbitration delay will grow linearly, further degrading event information accuracy.

Disclosure of Invention

The utility model provides a bilateral address event that reads shows transmission protocol circuit, its advantage lies in changing the AER protocol circuit of current single channel mode serial output into the output of binary channels, reduces the time stamp error of event under the big array, improves the degree of accuracy of event information.

A bilateral read address event representation transmission protocol circuit is shown in figure 3, and the structure comprises a row arbiter, a row address encoder, a column arbiter 1, a column arbiter 2, a column address encoder 1, a column address encoder 2, and an input 2^jIndividual line request (line request)<0>Request to bank<2^j-1>) And 2^kIndividual column request (column request)<0>Request to rank<2^k-1>) The output comprises 2^jIndividual line response (line response)<0>To bank response<2^j-1>）、2^kIndividual column response (column response)<0>Pair response<2^k-1>) And 2 event information external output channels, an event output channel 1 and an event output channel 2; the connection mode of each module is as follows: line requests<0>Request to bank<2^j-1>All access the row arbiter, the row arbiter outputs the acknowledge signal to the bus row acknowledge<0>To bank response<2^j-1>Each row response bus is connected to a row address encoder and a return circuit array; column request<0>Request to rank<2^k-1-1>A column arbiter 1 positioned at the upper left of the array is accessed, and the column arbiter 1 outputs a response signal to a bus column response<0>Pair response<2^k-1-1>Each row response bus is connected to the row address encoder 1 and the return circuit array; column request<2^k-1>Request to rank<2^k-1>A column arbiter 2 positioned at the lower right of the array is accessed, and the column arbiter 2 outputs a response signal to the bus column response<2^k-1>Pair response<2^k-1>And each row reply bus is connected to the row address encoder 2 and the return circuit array.

A two-sided read address event representation transfer protocol circuit operating as follows: each unit needing to be output in the circuit array generates a row request on a row bus of a row where the unit is located and inputs the row request into a row arbiter; the row arbiter sequences all the generated row requests and generates response signals on a row response bus corresponding to the row request positioned at the head; the row address encoder encodes the row number of the row where the response signal is located; after the row response signal returns to the circuit array, the unit circuit needing to be output in the row generates a request signal on a corresponding row request bus, wherein the row number is 0 to (2)^k-1-1) column requests in the range are input to the column arbiter 1 with a column number of 2^k-1~(2^k-1) column requests in the range are input to the column arbiter 2. The column arbiter 1 and the column arbiter 2 respectively sequence the input column requests at the same time, and generate response signals on the column response bus corresponding to the first column request, that is, generate two column response signals at the same time; the column address encoder 1 encodes the column number of the column where the response signal generated by the column arbiter 1 is located, and the column address encoder 2 encodes the column number of the column where the response signal generated by the column arbiter 2 is located; at this time, the row address coded by the row address coder and the column address coded by the column address coder 1 form event information 1 to be output from an event output channel 1, and the row address coded by the row address coder and the column address coded by a column address coder 2 form event information 2 to be output from an event output channel 2; after the column response returns to the circuit array, the event information in the corresponding unit is eliminated, and the protocol circuit starts to process the next pair of units needing to be output.

An address event representation transfer protocol circuit for bilateral read-out, which is advantageous in that: 1. by grouping the column requests of the circuit array, the path of the external output of the protocol circuit is increased, and the circuit speed is doubled; 2. the large-scale column request arbiter is divided into two smaller-scale column arbiters, so that the delay of a circuit in column arbitration is reduced, the time for queuing and waiting required by the output units in the same row is reduced, and the accuracy of information contained in output data is improved.

Drawings

FIG. 1 is a basic block diagram of a conventional AER transport protocol circuit;

FIG. 2 is a block diagram of an arbiter;

fig. 3 is a diagram of a dual edge read AER transport protocol circuit architecture.

Detailed Description

A bilateral read address event representation transmission protocol circuit can adopt a structure as shown in figure 3, and comprises a row arbiter, a row address encoder, a column arbiter 1, a column arbiter 2, a column address encoder 1, a column address encoder 2, an input 2^jIndividual line request (line request)<0>Request to bank<2^j-1>) And 2^kIndividual column request (column request)<0>Request to rank<2^k-1>) The output comprises 2^jIndividual line response (line response)<0>To bank response<2^j-1>）、2^kIndividual column response (column response)<0>Pair response<2^k-1>) And 2 event information external output channels, an event output channel 1 and an event output channel 2; the connection mode of each module is as follows: line requests<0>Request to bank<2^j-1>All access the row arbiter, the row arbiter outputs the acknowledge signal to the bus row acknowledge<0>To bank response<2^j-1>Each row response bus is connected to a row address encoder and a return circuit array; column request<0>Request to rank<2^k-1-1>A column arbiter 1 positioned at the upper left of the array is accessed, and the column arbiter 1 outputs a response signal to a bus column response<0>Pair response<2^k-1-1>Each row response bus is connected to the row address encoder 1 and the return circuit array; column request<2^k-1>Request to rank<2^k-1>A column arbiter 2 positioned at the lower right of the array is accessed, and the column arbiter 2 outputs a response signal to the bus column response<2^k-1>Pair response<2^k-1>And each row reply bus is connected to the row address encoder 2 and the return circuit array.

Claims

1. A two-sided read address event representation transfer protocol circuit, characterized by: the structure comprises a row arbiter, a row address encoder, a column arbiter 1, a column arbiter 2, a column address encoder 1, a column address encoder 2, an input comprising 2^jIndividual line request, i.e. line request<0>Request to bank<2^j-1>，2^kIndividual column requests, i.e. column requests<0>Request to rank<2^k-1>The output comprises 2^jIndividual line response, i.e. line response<0>To bank response<2^j-1>、2^kIndividual column response, i.e. column response<0>Pair response<2^k-1>And 2 event information external output channels, an event output channel 1 and an event output channel 2; the connection mode of each module is as follows: line requests<0>Request to bank<2^j-1>All access the row arbiter, the row arbiter outputs the acknowledge signal to the bus row acknowledge<0>To bank response<2^j-1>Each row response bus is connected to a row address encoder and a return circuit array; column request<0>Request to rank<2^k-1-1>A column arbiter 1 positioned at the upper left of the array is accessed, and the column arbiter 1 outputs a response signal to a bus column response<0>Pair response<2^k-1-1>Each row response bus is connected to the row address encoder 1 and the return circuit array; column request<2^k-1>Request to rank<2^k-1>A column arbiter 2 positioned at the lower right of the array is accessed, and the column arbiter 2 outputs a response signal to the bus column response<2^k-1>Pair response<2^k-1>And each row reply bus is connected to the row address encoder 2 and the return circuit array.

2. The dual-sided read address event representation transfer protocol circuit of claim 1, wherein: each unit needing to be output in the circuit array generates a row request on a row bus of a row where the unit is located and inputs the row request into a row arbiter; the row arbiter sequences all the generated row requests and generates response signals on a row response bus corresponding to the row request positioned at the head; the row address encoder encodes the row number of the row where the response signal is positioned(ii) a After the row response signal returns to the circuit array, the unit circuit needing to be output in the row generates a request signal on a corresponding row request bus, wherein the row number is 0 to (2)^k-1-1) column requests in the range are input to the column arbiter 1 with a column number of 2^k-1~(2^k-1) column requests in range are input to a column arbiter 2; the column arbiter 1 and the column arbiter 2 respectively sequence the input column requests at the same time, and generate response signals on the column response bus corresponding to the first column request, that is, generate two column response signals at the same time; the column address encoder 1 encodes the column number of the column where the response signal generated by the column arbiter 1 is located, and the column address encoder 2 encodes the column number of the column where the response signal generated by the column arbiter 2 is located; at this time, the row address coded by the row address coder and the column address coded by the column address coder 1 form event information 1 to be output from an event output channel 1, and the row address coded by the row address coder and the column address coded by a column address coder 2 form event information 2 to be output from an event output channel 2; after the column response returns to the circuit array, the event information in the corresponding unit is eliminated, and the protocol circuit starts to process the next pair of units needing to be output.