CN112732003A - Voltage regulator with temperature compensation and full-range input - Google Patents
Voltage regulator with temperature compensation and full-range input Download PDFInfo
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- CN112732003A CN112732003A CN202110365124.XA CN202110365124A CN112732003A CN 112732003 A CN112732003 A CN 112732003A CN 202110365124 A CN202110365124 A CN 202110365124A CN 112732003 A CN112732003 A CN 112732003A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses a voltage regulator with temperature compensation and full-range input, which comprises a starting circuit, a band gap circuit, a control circuit and a driving circuit, wherein the driving circuit comprises a first output circuit and a second output circuit; the starting circuit generates a starting current based on the input voltage signal; when the input voltage signal is high voltage, the band gap circuit enables the control circuit to control the second output circuit of the drive circuit to be switched on, and the first output circuit is switched off; the band gap circuit is connected with the second output circuit through the negative feedback circuit, the band gap circuit is offset through positive temperature coefficient voltage and negative temperature coefficient voltage to form approximate zero temperature coefficient voltage, and the output voltage is compensated through the negative feedback circuit. The invention can work under the voltage of the full input range and automatically compensate the output voltage according to the temperature change.
Description
Technical Field
The invention relates to the technical field of Integrated Circuit (IC) chip power management, in particular to a full-range input voltage regulator with temperature compensation.
Background
With the development of integrated circuits, the performance requirements of chips in the industry are higher and higher, and the performance of chips needs to be supported by the voltage provided by the internal power supply module to a great extent, which poses a new challenge to the power supply module.
For the requirement of chip performance, the chip is required to be capable of keeping normal operation under the full-range input voltage, so that the voltage regulator is required to be capable of automatically adjusting the input voltage, correspondingly adjusting the driving circuit and realizing the load capacity.
In addition, components adopted by the chip are greatly influenced by temperature, the output voltage of the current voltage regulator can reach 1V under high and low temperature environments, and the influence on the performance of the chip is great.
Disclosure of Invention
The invention aims to: in view of the above problems, a voltage regulator with temperature compensation and full-range input is provided to adjust the full-range input voltage and automatically compensate the temperature.
The technical scheme adopted by the invention is as follows:
a voltage regulator with temperature compensation and full-range input comprises a starting circuit, a band gap circuit, a control circuit and a driving circuit, wherein the driving circuit comprises a first output circuit and a second output circuit; the starting circuit generates a starting current based on an input voltage signal; when the input voltage signal is low voltage, the band gap circuit transmits a first signal to the control circuit, so that the control circuit controls a first output circuit of the driving circuit to be started; when the input voltage signal is high voltage, the band gap circuit transmits a second signal to the control circuit, so that the control circuit controls a second output circuit of the driving circuit to be switched on, and a first output circuit is switched off; the band gap circuit offsets the temperature coefficient by combining positive temperature coefficient voltage and negative temperature coefficient voltage, and compensates the output voltage of the second output circuit by the negative feedback circuit.
Further, the bandgap circuit includes a first branch and a second branch, a PTAT current is formed between the first branch and the second branch, the PTAT current is loaded on an impedance element, and the output voltage of the second output circuit is compensated through the negative feedback circuit.
Further, the negative feedback circuit comprises a first capacitance circuit, and the first capacitance circuit performs dominant pole compensation on the negative feedback circuit.
Further, the first branch circuit comprises a first triode cascade circuit, the second branch circuit comprises a second triode cascade circuit, and a voltage difference between the first triode cascade circuit and the second triode cascade circuit realizes positive temperature coefficient voltage and is loaded on an impedance element to form PTAT current; the ratio of the number of the triodes constituting the first triode cascade circuit to the number of the triodes constituting the second triode cascade circuit is from 2:1 to 16: 1.
Further, the control circuit comprises a first mirror image circuit, a trigger circuit and a second mirror image circuit; the trigger circuit is connected with the band gap circuit to receive the first signal or the second signal, and is switched on when receiving the first signal and switched off when receiving the second signal; the first mirror image circuit is connected with the starting circuit and mirrors the starting current of the starting circuit; the second mirror image circuit is respectively connected with the trigger circuit and the first mirror image circuit so as to mirror the current of the trigger circuit and divide the voltage of the output end of the first mirror image circuit according to the magnitude of the mirrored current; the output end of the first mirror image circuit is connected with the first output circuit.
Furthermore, the trigger circuit is formed by cascading at least one P-type field effect transistor, and the trigger circuit switches on each P-type field effect transistor when receiving the first signal and switches off each P-type field effect transistor when receiving the second signal.
Furthermore, the second mirror image circuit comprises two field effect transistors in a current mirror image relationship, one of the field effect transistors is connected with the trigger circuit in series, and the other field effect transistor is connected with the output end of the first mirror image circuit, so that the current output by the first mirror image circuit is shunted according to the magnitude of the mirror image current.
Furthermore, the input end of the first output circuit and/or the input end of the second output circuit are connected with corresponding clamping circuits.
Furthermore, the clamping circuit is composed of a voltage stabilizing circuit or is formed by cascading at least one field effect transistor.
Furthermore, the input end of the first output circuit is connected with a first clamping circuit, the input end of the second output circuit is connected with a second clamping circuit, the first clamping circuit is formed by cascading 4P-type field effect transistors, and the second clamping circuit is formed by cascading 5N-type field effect transistors.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. the invention can automatically transit from the second output circuit to the first output circuit when the input voltage changes between high voltage and low voltage so as to realize the work under the full-range input voltage.
2. The band gap circuit designed by the invention can automatically compensate the output voltage according to the change of temperature, thereby reducing the influence of temperature drift on the circuit, having strong anti-interference capability and leading the circuit to have the characteristic of low temperature coefficient.
3. The clamping circuit designed by the invention can automatically divide the input voltage when the voltage is abnormal, prevent the high voltage from puncturing a field effect tube or other components and ensure the safety of the circuit.
4. The invention can slow down the change speed of the output voltage when the input voltage suddenly changes or the output circuit is switched, thereby ensuring the normal work of the load.
5. The invention can reduce the voltage redundancy loss when in low-voltage input.
Drawings
The invention will now be described, by way of example, with reference to the accompanying drawings, in which:
fig. 1 is an example of an implementation circuit of the full range input voltage regulator with temperature compensation of the present invention.
Fig. 2 is a schematic diagram of a transistor cascade circuit.
In the figure, A is a starting circuit, B is a band gap circuit, C is a control circuit, D is a clamping circuit, E is a driving circuit, and MP1Is a first P-type field effect transistor, MP2Is a second P-type field effect transistor, MP3Is a third P-type field effect transistor，MP4Is a fourth P-type field effect transistor, MP5Is a fifth P-type field effect transistor, MP6Is a sixth P-type field effect transistor, MP7Is a seventh P-type field effect transistor, MP8Is an eighth P-type field effect transistor, MP9Is a ninth P-type field effect transistor, MP10Is a tenth P-type field effect transistor, MP11Is an eleventh P-type field effect transistor, MP12Is a twelfth P-type field effect transistor, MP13Is a thirteenth P type field effect transistor, MP14Is a fourteenth P-type field effect transistor, MN1Is a first N-type field effect transistor, MN2Is a second N-type field effect transistor, MN3Is a third N-type field effect transistor, MN4Is a fourth N-type field effect transistor, MN5Is a fifth N-type FET, MN6Is a sixth N-type FET, MN7Is a seventh N-type field effect transistor, MN8Is an eighth N-type field effect transistor, MN9Is a ninth N-type field effect transistor, MN10Is a tenth N-type field effect transistor, MN11Is an eleventh N-type FET, MN12Is a twelfth N-type FET, MN13Is a thirteenth N-type field effect transistor, MN14Is a fourteenth N-type field effect transistor, R1Is a first resistance, R2Is a second resistance, R3Is a third resistance, R4Is a fourth resistance, R5Is a fifth resistance, R6Is a sixth resistor, Q1For a first transistor cascade circuit, Q2Is a second triode cascade circuit, VT is a triode, C1Is a first capacitor, C2And the second capacitor VM is an input end, and VOUT is an output end of the voltage regulator.
Detailed Description
All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.
Any feature disclosed in this specification (including any accompanying claims, abstract) may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
The design idea of the invention is as follows: the voltage regulator with the temperature compensation and full-range input comprises a starting circuit A, a band gap circuit B, a control circuit C and a driving circuit E, wherein the driving circuit E comprises a first output circuit and a second output circuit; the starting circuit A generates starting current based on the input voltage signal; the band gap circuit B transmits a first signal to the control circuit C when the input voltage signal is low voltage, and transmits a second signal to the control circuit C when the input voltage signal is high voltage; when receiving the first signal, the control circuit C controls the first output circuit of the driving circuit E to be turned on, and when receiving the second signal, the control circuit C controls the second output circuit of the driving circuit E to be turned on, and the first output circuit is turned off. By the aid of the design, the first output circuit is turned off and the second output circuit is turned on when high voltage is input, and output voltage VOUT of the voltage regulator is gradually transited to the first output circuit by the second output circuit when low voltage is input, so that full-range input voltage work is guaranteed, and voltage redundancy loss during low voltage input is reduced.
The temperature compensation of the invention is realized by the following modes: the band gap circuit B offsets the temperature coefficient by combining the positive temperature coefficient voltage and the negative temperature coefficient voltage, namely, the positive temperature coefficient voltage and the negative temperature coefficient voltage are offset to form an approximate zero temperature coefficient voltage, and then the output voltage of the second output circuit is compensated by the negative feedback circuit. The band gap circuit B can automatically realize the compensation of voltage according to the change of temperature, thereby reducing the influence of temperature drift on the output voltage of the circuit.
Generally, the withstand voltage between the gate oxides is not higher than 5V or 6V, so the operating voltage of the CMOS inside the chip is not higher than 5V or 6V, and generally, 6V is used as a voltage limit, and an input voltage lower than 6V is regarded as a low voltage, and an input voltage higher than 6V is regarded as a high voltage. Of course, the discrimination limits may be adjusted accordingly depending on the particular type of selection.
The following examples are provided to illustrate the design of the present invention:
description of the drawings: in the embodiment of the invention, "field effect transistor MP" means that the corresponding field effect transistor is a P-type field effect transistor, and "field effect transistor MN" means that the corresponding field effect transistor is an N-type field effect transistor.
As shown in fig. 1, the voltage regulator of the present invention includes a start-up circuit a, a bandgap circuit B, a control circuit C, a clamp circuit D and a driving circuit E, and the clamp circuit D is not designed for protection. The drive circuit E comprises a P-type field effect transistor output circuit (corresponding to the first output circuit) and an N-type field effect transistor output circuit (corresponding to the second output circuit), wherein the P-type field effect transistor output circuit adopts a fourteenth P-type field effect transistor MP14The output circuit of the N-type field effect tube adopts a thirteenth N-type field effect tube MN13. The output end is connected with a second capacitor circuit which prevents the output voltage from sudden change and slows down the voltage sudden change condition when the input voltage suddenly changes or the output circuit is switched. In some embodiments, the second capacitor circuit is formed by a capacitor, or a fourteenth N-type FET MN14Form a fourteenth N-type FET MN14Is connected in parallel to a low potential, and the gate is connected to an output terminal (an output terminal of a P-type fet output circuit or an N-type fet output circuit).
The starting circuit A generates a starting current based on the input voltage signal. As shown in FIG. 1, the start-up circuit A comprises a first P-type field effect transistor MP1And a second P-type field effect transistor MP2And a second resistor R2The branch is formed by a second resistor R after the circuit A is started2The branch obtains current
：
Where VM is the voltage at the input and VGS represents the voltage between the gate and source of the corresponding FET, e.g.
Representing a first P-type field effect transistor MP1Grid electrodeAnd a voltage between the source electrodes of the transistors,
representing a second P-type FET MP2The voltage between the gate and the source. Further calculating the starting current IS
Wherein W, L refer to the width and length, respectively, of the corresponding FET, e.g.
Then it represents the third P-type FET MP3The ratio of the width to the length of (c),
then it represents the second P-type FET MP2The ratio of the width to the length of (c),
then it represents the first N-type FET MN1The ratio of the width to the length of (c),
then it represents the second N-type FET MN2Width to length ratio of (a).
Third P-type field effect transistor MP3Mirror image second P type field effect transistor MP2Current of the first N-type FET MN1And a third P-type field effect transistor MP3Series, third P-type field effect transistor MP3Through a first resistor R1Connected to the input terminal, a first resistor R1Can balance the first P-type field effect transistor MP1The voltage loss of the transformer reduces the current adaptation proportion. Second N-type FET MN2Mirror image first N-type field effect transistor MN1A drain connected to the bandgap circuit, a second N-type field effect transistor MN2The drain electrode is also connected to the first capacitor C1The input terminal VM is connected to play a role of buffer isolation. In the third P-type field effect transistor MP3And a first N typeField effect transistor MN1A third N-type field effect transistor MN is also arranged3The third N-type field effect transistor MN3After being conducted, the third P-type field effect transistor MP is connected3The output voltage is divided. After the starting circuit A breaks the degenerated bias point, the band gap circuit starts to work, and after the whole voltage regulator is started, the third N-type field effect transistor MN3Starting, for the third P-type FET MP3The output voltage of the first N-type field effect transistor MN is divided, and then the first N-type field effect transistor MN is pulled down1And a second N-type field effect transistor MN2The first N-type FET MN1A second N-type field effect transistor MN2And closing.
The band gap circuit is connected with the output circuit of the N-type field effect tube through a negative feedback circuit, the band gap circuit is combined with the negative feedback circuit to generate a PTAT current, the PTAT current acts on the negative feedback circuit, and the negative feedback circuit compensates the output voltage of the output circuit of the N-type field effect tube. In some embodiments, the negative feedback circuit comprises a twelfth NFET MN12And a fifth resistor R5. The band gap circuit comprises a fourth P-type field effect transistor MP4And a first triode cascade circuit Q1The first branch is formed, and the fifth P-type field effect transistor MP5And a second triode cascade circuit Q2The second branch circuit is a first triode cascade circuit Q1And a second triode cascade circuit Q2The compensation circuit is formed by cascading a plurality of triodes, the number of cascades is not necessarily the same, the number of triodes of the first triode cascade circuit Q1 and the second triode cascade circuit Q2 is respectively designed according to the compensation requirement, a cascade structure formed by 4 triodes is shown in figure 2, wherein VT is a single triode. Fourth P-type field effect transistor MP4And a fifth P-type field effect transistor MP5And maintaining the currents of the two branches to be approximately equal, and forming negative feedback with the driving circuit E. Fourth P-type field effect transistor MP4And a fifth P-type field effect transistor MP5In a current mirror relationship, i.e. fourth P-type field effect transistor MP4And a fifth P-type field effect transistor MP5The source electrode of the first P-type field effect transistor MP is connected to the input end VM in parallel and the fourth P-type field effect transistor MP4And a fifth P-type field effect transistor MP5The gates of which are connected in parallel to the starting circuit a,i.e. the second N-type FET MN2Drain electrode of (1), fourth P-type field effect transistor MP4Is connected to the gate. Fourth P-type field effect transistor MP4The drain electrode of the first triode cascade circuit Q1By means of a fourth P-type field-effect transistor MP4Terminal triode (i.e. directly connected with fourth P-type field effect transistor MP4Triode of (d) and a fifth P-type field effect transistor MP5The drain electrodes of the first and second triodes are respectively connected with a second triode cascade circuit Q2By means of a fifth P-type field effect transistor MP5Terminal triode (i.e. directly connected with fifth P-type field effect transistor MP5Triode of (d) and a twelfth N-type field effect transistor MN12The output circuit of the N-type field effect transistor is connected with the twelfth N-type field effect transistor MN12The twelfth N-type FET MN12Is connected with a fifth resistor R5Fifth resistor R5Through a sixth resistor R6A first triode cascade circuit Q connected with low potential1And a second triode cascade short circuit Q2The base electrode of each triode VT is connected in parallel with the fifth resistor R5And a sixth resistor R6To (c) to (d); first triode cascade circuit Q1Far from the fourth P-type field effect transistor MP4Terminal triode (i.e. the first branch separated from the fourth P-type field effect transistor MP4The farthest transistor), and a second transistor cascade circuit Q2Far away from the fifth P-type field effect transistor MP5Terminal triode (i.e. second branch leaving fifth P-type field effect transistor MP5The farthest triode) is respectively loaded on the third resistors R3Two-terminal, second triode cascade circuit Q2Far away from the fifth P-type field effect transistor MP5Terminal triode (i.e. second triode cascade circuit Q)2Upper direct connection with a third resistor R3Triode) is also connected through a fourth resistor R4A low potential is connected. The band gap circuit is connected with a circuit Q through a first triode1And a second triode cascade circuit Q2Voltage difference of▽V BE Loaded to a third resistor R3In the above, a PTAT current is formed to achieve positive temperature coefficient voltage compensation. First triode cascade circuit Q1And a second triode cascade circuitWay Q2The ratio of the number of the middle triodes is between 2:1 and 16:1 (including a terminal value), and the ratio of the number of the middle triodes to the number of the middle triodes can be adjusted according to actual needs to improve compensation precision and reduce current mismatch. At this time, taking 2:1 as an example, the band gap reference passes through the first triode cascade circuit Q1A circuit Q cascaded with a second triode2Is/are as follows▽V BE The difference value realizes positive temperature coefficient voltage and is added to a third resistor R3Above, a PTAT current is formed:
wherein K represents Boltzmann's constant, T represents thermodynamic temperature, and Q represents a current flowing through the third resistor R3The amount of charge of (a) is,▽ V BE namely a first triode cascade circuit Q1Base and emitter voltage and second triode cascade circuit Q2Difference (absolute value) of base and emitter voltages.
Then the fourth resistor R4The voltage across (i.e. positive temperature coefficient voltage) is
VBEQ2Indicating a second transistor cascade circuit Q2The voltage between the base and the emitter. Fifth resistor R on negative feedback circuit5And a sixth resistor R6The ratio of the resistance values of the first and second N-type field effect transistors MN12The voltage of the gate is determined by the thirteenth N-type FET MN13The output voltage.
The negative feedback circuit further comprises a first capacitor circuit connected to the twelfth N-type FET MN12The first capacitor circuit performs dominant pole compensation on the negative feedback circuit. In some embodiments, the first capacitor circuit is formed by a capacitor, or an eleventh N-type FET MN11Form the eleventh N-type FET MN11Is connected in parallel to a low potential, and a gate is connected to a second potentialTwelve N type field effect transistor MN12A gate electrode of (1).
The control circuit C comprises a first mirror image circuit, a trigger circuit and a second mirror image circuit; the trigger circuit is connected with the band gap circuit to receive the first signal or the second signal, and is switched on when receiving the first signal and switched off when receiving the second signal; the first mirror image circuit is connected with the starting circuit A, and mirrors the starting current of the starting circuit A; the second mirror image circuit is respectively connected with the trigger circuit and the first mirror image circuit so as to mirror the current of the trigger circuit and divide the voltage of the output end of the first mirror image circuit according to the magnitude of the current of the mirror image; the output end of the first mirror image circuit is connected with the output circuit of the P-type field effect transistor. In some embodiments, the first mirror circuit is formed by an eighth PFET MP8And a ninth P-type field effect transistor MP9Formed by cascade connection, an eighth P-type field effect transistor MP8Mirror image first P type field effect transistor MP1Current of (1), ninth P-type field effect transistor MP9Mirror image second P type field effect transistor MP2This can improve the current mirror accuracy. The trigger circuit is formed by cascading at least one P-type field effect transistor, the grid electrode of each P-type field effect transistor of the trigger circuit is connected to the drain electrode of the fourth P-type field effect transistor MP4 in parallel, the source electrode of the P-type field effect transistor close to the B end of the band gap circuit is connected with the drain electrode of the fifth P-type field effect transistor MP5, and the drain electrode of the P-type field effect transistor close to the second mirror image circuit end is connected with the second mirror image circuit. In one embodiment, the trigger circuit is composed of a sixth P-type FET MP6And a seventh P-type field effect transistor MP7The number of field effect transistors can be changed according to the situation. Sixth P-type field effect transistor MP6And a seventh P-type field effect transistor MP7Is connected in parallel to the fourth P-type field effect transistor MP4The drain electrode of (1), the sixth P-type field effect transistor MP6The source electrode of the first P-type field effect transistor MP is connected with the fifth P-type field effect transistor MP5Drain electrode of (1), seventh P-type field effect transistor MP7Is connected to the second mirror circuit. The second mirror image circuit comprises a fourth N-type field effect transistor MN arranged in a mirror image mode4And a fifth N-type FET MN5Fourth N-type FET MN4Grid electrode of (1), fifth N-type field effect transistor MN5Of the gate electrodeAnd a fourth N-type field effect transistor MN4All the drains of the first and second transistors are connected to the output terminal of the trigger circuit (i.e. the seventh P-type FET MP7Drain electrode of) of the fourth N-type field effect transistor MN4And a fifth N-type FET MN5The source electrode of the first N-type field effect transistor MN is connected with a low potential in parallel5Is connected with the output end of the first mirror circuit (i.e. the ninth P-type field effect transistor MP9The drain electrode of (1).
The clamp D comprises a first clamp and/or a second clamp, and the clamp D is designed preventively and does not function under normal conditions. The first clamping circuit is connected with the input end of the P-type field effect transistor output circuit, the second clamping circuit is connected with the input end of the N-type field effect transistor output circuit, and the effect of preventing the fourteenth P-type field effect transistor MP from being broken down by high voltage is achieved14Thirteenth N type field effect transistor MN13The function of (1). In some embodiments, the first clamping circuit is formed by a voltage stabilizing circuit or cascaded by at least one fet, and similarly, the second clamping circuit is formed by a voltage stabilizing circuit or cascaded by at least one fet. The present invention preferably employs a clamp circuit in the form of a cascaded fet, which has the advantage of being smaller in size than a clamp circuit in the form of a diode or a zener diode. The first clamp circuit is designed by a tenth P-type field effect transistor MP in combination with the rated voltage of the field effect transistor in the output circuit10Eleventh P-type field effect transistor MP11And the twelfth P-type field effect transistor MP12And thirteenth P type field effect transistor MP13The second clamping circuit is formed by cascade connection of diodes, and the design of the second clamping circuit is that a sixth N-type field effect transistor MN is arranged6And a seventh N-type field effect transistor MN7And the eighth N-type field effect transistor MN8And a ninth N-type field effect transistor MN9And a tenth N-type FET MN10The diode is cascaded by adopting a diode connection method.
When the voltage inputted from the input terminal VM is high, the fourth P-type FET MP4And a fifth P-type field effect transistor MP5Are all in saturation state, therefore, the sixth P-type field effect transistor MP6The grid electrode and the source electrode are approximately equal in potential, and a sixth P-type field effect transistor MP6And a seventh P-type field effect transistor MP7And (4) cutting off corresponding to the action of the trigger circuit receiving the second signal. Fourth N-type field effect transistor MN4And a fifth N-type FET MN5No current, the eighth P-type FET MP8And a ninth P-type field effect transistor MP9A fourteenth P-type field effect transistor MP14The gate voltage is pulled to a high potential, and a fourteenth P-type field effect transistor MP14And (6) cutting off. Corresponding to the situation, the fifth P-type field effect transistor MP5Adding a thirteenth N-type field effect transistor MN13Gate voltage pulled to high potential, thirteenth N-type FET MN13In a conducting state, a thirteenth N-type FET MN13And outputting a voltage signal, namely, the output circuit of the P-type field effect transistor is turned off at the moment, and the output circuit of the N-type field effect transistor works. When the input voltage gradually decreases, the fifth P-type FET MP5The output voltage is not enough to provide the twelfth N-type FET MN12And thirteenth N-type field effect transistor MN13At the driving voltage of, the fifth P-type FET MP5Is pressed into the linear region, and at this time, the sixth P-type field effect transistor MP6Will be gradually lower than the source voltage and make the sixth P-type field effect transistor MP6Seventh P-type field effect transistor MP7Turning on the fourth N-type FET MN corresponding to the action of the trigger circuit receiving the first signal4And a fifth N-type FET MN5Gradually generate current to pull down the fourteenth P-type FET MP14Grid (i.e. MP)9Drain) and the fourteenth N-type fet is turned on to provide a load carrying capability. At this time, the drive to the load is gradually switched from the output circuit of the N-type FET to the output circuit of the P-type FET, and the thirteenth N-type FET MN13The VGS voltage margin loss will also gradually disappear, so that the output voltage is approximately equal to the input voltage, and an isobaric output is achieved. Fourteenth P type field effect transistor MP14Through a second capacitor C, and the input terminal VM2And carrying out buffer isolation.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed.
Claims (10)
1. The voltage regulator with the temperature compensation and the full-range input is characterized by comprising a starting circuit (A), a band gap circuit (B), a control circuit (C) and a driving circuit (E), wherein the driving circuit (E) comprises a first output circuit and a second output circuit; the starting circuit (A) generates a starting current based on an input voltage signal; when the input voltage signal is low voltage, the band gap circuit (B) transmits a first signal to the control circuit (C) so that the control circuit (C) controls a first output circuit of the driving circuit (E) to be started; when the input voltage signal is high voltage, the band gap circuit (B) transmits a second signal to the control circuit (C) so that the control circuit (C) controls a second output circuit of the driving circuit (E) to be switched on and a first output circuit to be switched off;
the band gap circuit (B) offsets the temperature coefficient by combining positive temperature coefficient voltage and negative temperature coefficient voltage, and compensates the output voltage of the second output circuit by a negative feedback circuit.
2. The voltage regulator with temperature compensated full-range input according to claim 1, wherein the bandgap circuit (B) comprises a first branch and a second branch, a PTAT current is formed between the first branch and the second branch, and the PTAT current is loaded on an impedance element, and the output voltage of the second output circuit is compensated by the negative feedback circuit.
3. The temperature compensated full range input voltage regulator of claim 2, wherein the negative feedback circuit comprises a first capacitive circuit that dominant pole compensates the negative feedback circuit.
4. The full-range input voltage regulator with temperature compensation of claim 2 or 3, wherein the first branch comprises a first transistor cascadeCircuit (Q)1) The second branch comprises a second triode cascade circuit (Q)2) Said first triode cascade circuit (Q)1) A circuit (Q) in cascade with the second transistor2) The voltage difference between the two resistors realizes positive temperature coefficient voltage and is loaded on the impedance element to form PTAT current; forming said first triode cascade circuit (Q)1) And forming said second transistor cascade circuit (Q)2) The ratio of the number of triodes (VT) is between 2:1 and 16: 1.
5. The voltage regulator with temperature compensated full range input of claim 2 or 3, wherein the control circuit (C) comprises a first mirror circuit, a trigger circuit and a second mirror circuit; the trigger circuit is connected with the band gap circuit (B) to receive the first signal or the second signal, and is switched on when receiving the first signal and switched off when receiving the second signal; the first mirror image circuit is connected with the starting circuit (A) and mirrors the starting current of the starting circuit (A); the second mirror image circuit is respectively connected with the trigger circuit and the first mirror image circuit so as to mirror the current of the trigger circuit and divide the voltage of the output end of the first mirror image circuit according to the magnitude of the mirrored current; the output end of the first mirror image circuit is connected with the first output circuit.
6. The full-range input voltage regulator with temperature compensation of claim 5, wherein the trigger circuit is cascaded by at least one PFET, and wherein the trigger circuit turns on the PFETs when receiving a first signal and turns off the PFETs when receiving a second signal.
7. The temperature compensated full range input voltage regulator of claim 5, wherein the second mirror circuit comprises two fets in a current mirror relationship, one fet being connected in series with the trigger circuit and the other fet being connected to the output of the first mirror circuit to shunt the current output by the first mirror circuit by the magnitude of the mirror current.
8. The full-range input voltage regulator with temperature compensation according to claim 1, characterized in that a respective clamping circuit (D) is connected to the input of the first output circuit and/or to the input of the second output circuit.
9. The full-range input voltage regulator with temperature compensation according to claim 8, characterized in that the clamping circuit (D) is constituted by a voltage regulation circuit or by at least one fet cascade.
10. The full-range input voltage regulator with temperature compensation of claim 9, wherein a first clamp is connected to an input of the first output circuit, a second clamp is connected to an input of the second output circuit, the first clamp is formed by cascading 4 PFETs, and the second clamp is formed by cascading 5 NFETs.
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| CN116827106A (en) * | 2023-08-28 | 2023-09-29 | 苏州贝克微电子股份有限公司 | High-precision high-reliability circuit structure |
| CN119292398A (en) * | 2024-11-15 | 2025-01-10 | 北京士模微电子有限责任公司 | A New Low-Noise, Low-Power Bandgap Reference |
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