CN112731101A - Integrated circuit connectivity testing system and manufacturing method thereof - Google Patents
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
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- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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Abstract
The invention discloses an integrated circuit connectivity testing system and a manufacturing method thereof, and relates to the technical field of semiconductor three-dimensional integration. Applied to a wafer for forming integrated circuits, the apparatus comprising: test subassembly and tester, this test subassembly includes: the test pads are connected with one or more through silicon vias to be tested in the wafer through the wires, and the tester comprises a plurality of probes; after the probes are electrically connected with the test pad, the tester is used for applying voltage and/or current to the tester through the probes so as to determine the connectivity of one or more through silicon vias to be tested according to the acquired resistivity. On the premise of ensuring the test accuracy, the communication rate test structure is simplified, and the test cost is reduced. The integrated circuit connectivity test system provided by the invention is used for testing the connectivity of the semiconductor three-dimensional integrated circuit.
Description
Technical Field
The invention relates to the technical field of semiconductor three-dimensional integration, in particular to an integrated circuit connectivity testing system and a manufacturing method thereof.
Background
Semiconductor devices have found widespread use in many industries, such as photovoltaics, bioelectronics, medical systems, electronic analysis, computer systems, military systems, satellite systems, and undersea systems, among others. Along with the continuous reduction of the nanometer level of the transistor, the integration degree inside the chip is higher and higher, and the geometric size of the device is smaller and smaller. It is becoming more and more difficult to reduce the transistor process size and shorten the length of the chip interconnect lines, and therefore new process costs are steadily increasing while margins are gradually decreasing.
To continue to maintain moore's law, free of the physical and electrical limitations that arise during the development of integrated circuits, three-dimensional stacked integrated circuits (or chips) have emerged. Different from the conventional two-dimensional chip manufacturing process, the three-dimensional chip manufacturing mainly uses Through Silicon Vias (TSVs) to vertically stack a plurality of wafers so as to connect integrated circuits. This technique reduces the overall area of the chip and improves the performance of the chip. However, three-dimensional stacked integrated circuits have many advantages and challenges. Specifically, the TSV technology is mainly used in the three-dimensional stacked integrated circuit, and the TSV is subjected to etching, depositing an oxide layer, depositing a seed layer, filling a conductive metal, and chemical mechanical polishing during the manufacturing process, wherein each process step may cause the connectivity problem of the TSV. In the bonding process, due to the height difference and the position difference of bonding pads or the pollution of a bonding interface and the like, the communication rate is reduced, so that the chips cannot normally communicate, and the problems are more pronounced in high-density small-size TSV.
In order to quantitatively characterize the through silicon via and the bonding pad connectivity thereof, the manufactured through silicon via needs to be tested and monitored for the connectivity before bonding (Pre-Bond) and after bonding (Post-Bond) so as to guide the optimization of the through silicon via manufacturing process and the bonding process. The connectivity testing method in the related art is complex in testing structure, complex in manufacturing process and high in cost, and the scheme for simplifying the manufacturing process and the testing structure is not accurate enough.
Disclosure of Invention
The invention aims to provide an integrated circuit connectivity testing system and a manufacturing method thereof, and aims to solve the problems that in the prior art, a testing structure is complex, a manufacturing process is complicated, the cost is high, and the testing accuracy cannot be guaranteed.
In order to achieve the above purpose, the invention provides the following technical scheme:
an integrated circuit connectivity test system for use with wafers used to form integrated circuits, the apparatus comprising: test subassembly and tester, the test subassembly includes: the testing device comprises a plurality of leads and a plurality of testing pads, wherein the leads and the testing pads are positioned on the upper surface and the lower surface of the wafer, the testing pads are connected with one or more through silicon vias to be tested in the wafer through the leads, and the tester comprises a plurality of probes;
after the probes are electrically connected with the test pads, the tester is used for applying voltage and/or current to the tester through the probes so as to determine the connectivity of the one or more through silicon vias to be tested according to the acquired resistivity.
Optionally, the plurality of test pads include a plurality of upper surface test pads disposed on an upper surface of the wafer and a plurality of lower surface test pads disposed on a lower surface of the wafer, the lower surface test pads being electrically connected to the upper surface through the wafer by test through-silicon-vias.
Optionally, each wire is communicated with each column of through silicon vias to be tested exposed on the upper surface and connected with the upper surface test pad;
and each wire is communicated with each row of silicon through holes to be tested exposed from the lower surface and is connected with the lower surface test bonding pad.
Optionally, the lower part of the wafer is bonded with the substrate, and each through silicon via to be tested exposed from the lower surface of the wafer is provided with a bonding pad;
each lead is communicated with each row of silicon through holes to be tested exposed out of the upper surface and is connected with the upper surface testing bonding pad;
and each wire is communicated with each row of bonding welding points exposed from the lower surface and is connected with the lower surface test bonding pad.
Optionally, after the probes are electrically connected to the test pad, the tester is configured to apply a voltage or a current to the tester through the probes to determine a connectivity rate of one or more of the bonding pads according to the obtained resistivity.
Optionally, the wafer has a plurality of groups of through silicon vias to be tested, each group of through silicon vias to be tested includes two through silicon vias to be tested connected in series through a wire located on a lower surface of the wafer, the plurality of test pads includes two upper surface test pad groups disposed on an upper surface of the wafer, and each upper surface test pad group includes two upper surface test pads connected to each other;
the two upper surface test pad groups and the plurality of groups of through silicon vias to be tested are connected in series through a lead positioned on the upper surface.
Optionally, the tester comprises two voltage probes and two current probes;
after the two voltage probes are electrically connected with a first upper surface test pad group of the two upper surface test pad groups, and the two current probes are electrically connected with a second upper surface test pad of the two upper surface test pad groups, the tester is configured to:
and applying voltage to the first upper surface testing pad through the two voltage probes, and applying current to the second upper surface testing pad through the two current probes so as to determine the communication rate of the one or more through silicon vias to be tested according to the obtained resistivity.
Compared with the prior art, the integrated circuit connectivity testing system provided by the invention can connect the through silicon vias through the conducting wires and the testing pads arranged on the wafer, further determine the connectivity of the through silicon vias according to the detection data acquired by the detector, simplify the connectivity testing structure and reduce the testing cost on the premise of ensuring the testing accuracy.
The invention also provides a manufacturing method of the integrated circuit connectivity test system, which is applied to a wafer for forming the integrated circuit, and the method comprises the following steps:
electrically connecting one or more through silicon vias to be tested in the wafer through a plurality of wires;
and electrically connecting one end of each wire with any one of a plurality of test pads, wherein the plurality of test pads are used for placing a plurality of probes in a detector for testing resistivity.
Optionally, the electrically connecting one or more through silicon vias to be tested in the wafer through a plurality of wires includes:
electrically connecting each row of through silicon vias to be tested exposed on the upper surface of the wafer through the lead;
each row of silicon through holes to be tested or bonding pads exposed on the lower surface of the wafer are electrically connected through the wires, and the bonding pads are used for bonding the lower part of the wafer with a substrate:
the electrically connecting one end of each of the wires with any one of a plurality of test pads includes:
arranging a plurality of upper surface test pads on the upper surface, and arranging a plurality of lower surface test pads on the lower surface;
connecting a lead communicated with each row of through silicon vias to be tested with each upper surface test pad;
connecting a lead which is communicated with each row of through silicon holes to be tested or bonding welding spots with each lower surface test bonding pad;
and carrying out hole opening processing at a position above the lower surface test pad of the wafer to obtain a test through silicon via, wherein the test through silicon via is used for electrically connecting the lower surface test pad to the upper surface through the wafer.
Optionally, the electrically connecting one or more through silicon vias to be tested in the wafer through a plurality of wires includes:
dividing a plurality of through silicon holes to be tested on the wafer into a plurality of groups of through silicon holes to be tested, wherein each group of through silicon holes to be tested comprises two through silicon holes to be tested which are connected in series through a lead positioned on the lower surface of the wafer;
the multiple groups of through silicon vias to be tested are connected in series through wires positioned on the upper surface;
the electrically connecting one end of each of the wires with any one of a plurality of test pads includes:
arranging two upper surface test bonding pad groups on the upper surface of the wafer, wherein each upper surface test bonding pad group comprises two upper surface test bonding pads which are connected with each other;
and connecting the two upper surface test pad groups in series to the plurality of groups of through silicon vias to be tested which are connected in series respectively through a lead positioned on the upper surface.
Compared with the prior art, the manufacturing method of the integrated circuit connectivity test system provided by the invention can construct the connectivity test structure by adding the lead and the test pad on the wafer, simplify the manufacturing process flow and lower the manufacturing cost on the premise of ensuring the test accuracy.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a top view of an integrated circuit connectivity testing system according to an embodiment of the present invention;
fig. 2 is a schematic perspective view of a system for testing connectivity of an integrated circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a head-up view of a testing assembly of an alternative integrated circuit connectivity testing system in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of a top view of another integrated circuit connectivity test system according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing a system for testing connectivity of an integrated circuit according to an embodiment of the present invention.
Detailed Description
In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.
Fig. 1 is a schematic plan view of an integrated circuit connectivity testing system according to an exemplary embodiment, referring to fig. 1, applied to a wafer 200 for forming integrated circuits, the apparatus 100 may include: test subassembly and tester, this test subassembly includes: a plurality of wires 120 and a plurality of test pads 130 located on the upper and lower surfaces of the wafer 200, the test pads 130 are connected to one or more through-silicon vias 210 to be tested in the wafer 200 through the wires 120, and the tester 110 includes a plurality of probes 111. The test pad may also be referred to as a test point, in english as pad.
Illustratively, the test assembly is physically attached to a wafer 200 that has been through-silicon-vias formed and through-silicon-via-fill completed for use in constructing integrated circuit chips. Wherein each through-silicon via 210 to be tested on the wafer 200 is exposed on the upper surface and the lower surface of the wafer 200. In the embodiment of the present disclosure, the exposed through-silicon vias 210 to be tested are connected in series through the wires 120 and are further electrically connected to the test pads 130 fixed on the surface of the wafer 200. The conductive wires 120 and the test pads 130 may be fixed to the upper and lower surfaces of the wafer 200. As shown in fig. 1, the rectangular boxes connecting the through-silicon vias 210 in fig. 1 are used to represent the conductive lines, wherein the solid rectangular boxes are used to represent the conductive lines fixed on the upper surface of the wafer 200, and the dotted rectangular boxes are used to represent the conductive lines fixed on the lower surface of the wafer 200. Similarly, the boxes connected to the wires in fig. 1 are used to characterize the test pads, wherein the solid line boxes are used to characterize the test pads affixed to the top surface of the wafer 200 and the dashed line boxes are used to characterize the test pads affixed to the bottom surface of the wafer 200. The tester is a double-probe resistivity tester or a four-probe resistivity tester.
After the probes 111 are electrically connected to the test pad 130, the tester 110 is configured to apply a voltage and/or a current to the tester 110 through the probes 111 to determine a connectivity rate of the one or more through-silicon vias 210 to be tested according to the obtained resistivity.
Illustratively, based on the structure of the integrated circuit connectivity test system provided in the embodiment shown in fig. 1, the plurality of probes 111 may be placed on the test pad 130 to apply a voltage and a current to the test pad 130 during a test process. The tester 110 determines the resistance of all through-silicon vias to be tested by the returned current or voltage. And if the resistance exceeds a preset threshold value, determining that the one or more through silicon vias to be tested have disconnected through silicon vias. And if the resistance does not exceed the preset threshold, the one or more through silicon vias to be tested are all considered to be communicated.
In summary, the integrated circuit connectivity test system provided in the embodiments of the present invention can connect the through-silicon vias through the wires and the test pads disposed on the wafer, and then determine the connectivity of the through-silicon vias according to the detection data obtained by the detector, so as to simplify the connectivity test structure and reduce the test cost on the premise of ensuring the test accuracy.
Illustratively, fig. 2 is a schematic perspective view illustrating an integrated circuit connectivity test system according to an exemplary embodiment, and referring to fig. 2, the plurality of test pads 130 includes a plurality of upper surface test pads 131 disposed on an upper surface of the wafer and a plurality of lower surface test pads 132 disposed on a lower surface of the wafer 200, and the lower surface test pads 132 are electrically connected to the upper surface through the wafer by test through-silicon vias 220. The tester 110 includes: probes 111a and probes 111 b. It should be noted that, for convenience of illustration, the wafer is not shown in fig. 2, and only the through-silicon-via to be tested 210 and the probing through-silicon-via 220 are illustrated. It is understood that the through-silicon-via to be tested 210 and the probing through-silicon-via 220 are both inside the wafer.
As shown in fig. 2, the lower surface of the wafer is typically bonded to a pedestal or other wafer and is difficult to expose. Therefore, in order to facilitate the placement of the probe, the lower surface test pad 132 disposed on the lower surface of the wafer may be led out to the upper surface of the wafer through the probing through-silicon via 220. In this way, the probes can be directly placed on the exposed portions of the probing through silicon vias 220 corresponding to the upper surface test pads 131 and the upper surface test pads 132 on the upper surface of the wafer by manual placement or robot placement, so as to electrically connect each probe with the upper surface test pad 131 or the upper surface test pad 132.
Illustratively, each of the wires 120 is connected to each of the columns of through-silicon vias 210 exposed on the upper surface and connected to the upper surface test pad 131; each of the wires 120 is connected to each of the rows of through-silicon vias to be tested 210 exposed from the lower surface and connected to the lower surface test pad 132. The connectivity measurement of the through silicon vias to be tested at the intersection of the line and the row can be realized by gating any line of through silicon vias to be tested on the lower surface of the wafer and any row of through silicon vias to be tested on the upper surface of the wafer and combining kirchhoff's law. Each row of the through silicon vias 210 to be tested and each row of the through silicon vias 210 to be tested are respectively gated, so that the connectivity of all the through silicon vias to be tested in the test structure can be independently measured, and the accurate test evaluation of the connectivity of the through silicon vias in the wafer 200 can be realized.
Illustratively, fig. 3 is a schematic diagram of a head-up structure of a testing assembly of another integrated circuit connectivity testing system according to an embodiment of the present invention, referring to fig. 3, wherein the wafer 200 is bonded to a substrate 300 under the wafer, and each of the through-silicon vias 210 to be tested exposed on the lower surface of the wafer 200 has a bonding pad 230; each of the wires 120 is connected to each of the columns of through-silicon vias 210 to be tested exposed from the upper surface and connected to the upper surface test pad 131; each of the wires 120 is connected to the lower surface test pad 132 in communication with each of the rows of the bonding pads 230 exposed at the lower surface. Based on this, after the plurality of probes are electrically connected with the test pad, the tester is used for applying voltage or current to the tester through the plurality of probes so as to determine the connectivity of the one or more bonding pads according to the acquired resistivity.
In one possible implementation, the wafer 200 is bonded to a substrate 300 (or other wafer), and the integrated circuit connectivity test system provided by the embodiment of the disclosure can also be used for testing the connectivity of a bonding pad. As shown in fig. 3, the structure and connection of the upper surface of the wafer 200 are the same as those shown in fig. 1 and 2, i.e., each row of through-silicon-vias to be tested is connected to the test pad through a wire. Except that the exposed portion of the through-silicon via to be tested on the lower surface of the wafer 200 is directly connected to the bonding pad 230. The bonding pads 230 may also be connected to the lower surface test pads 132 in row units, and the lower surface test pads 132 are also electrically connected to the upper surface of the wafer 200 through the test through-silicon vias 220. In this way, the connectivity test of the bonding pads 230 between the wafer 200 and the substrate 300 can be implemented in the same test manner as the above-mentioned test of the connectivity rate of the through-silicon vias to be tested in the wafer 200.
Therefore, the integrated circuit connectivity testing system provided by the embodiment of the invention can lead out a plurality of silicon through holes and bonding pads to the upper surface of the wafer through the wires and the testing pads arranged on the wafer, and further determine the connectivity of the silicon through holes and the bonding pads according to the detection data acquired by the detector, so that the connectivity testing structure is simplified and the testing cost is reduced on the premise of ensuring the testing accuracy.
For example, fig. 4 is a schematic top view structure diagram of another integrated circuit connectivity testing system according to an embodiment of the present invention, referring to fig. 4, the wafer 200 has a plurality of sets of through-silicon vias to be tested, each set of through-silicon vias to be tested includes two through-silicon vias to be tested 210 connected in series through a conducting wire 120a located on a lower surface of the wafer 200, the plurality of test pads include two upper surface test pad sets 131a and 131b disposed on an upper surface of the wafer 200, and each upper surface test pad set includes two upper surface test pads connected to each other; the two upper surface test pad groups and the plurality of groups of through-silicon vias to be tested are connected in series by a wire 120b on the upper surface.
Illustratively, in order to verify the accuracy of the test, the embodiment of the present disclosure further provides a test structure for collecting the resistance of each through silicon via 210 to be tested, and further determining the connectivity of each through silicon via 210 to be tested. Specifically, taking the wafer including 4 through-silicon vias to be tested as shown in fig. 4 as an example, the testing structure includes 4 upper surface testing pads, and the 4 upper surface testing pads are divided into two groups, i.e., two first upper surface testing pads 131a and two second upper surface testing pads 131 b. The solid line box corresponding to the number 120b in fig. 4 is used to represent the above-mentioned conductive line on the upper surface, and the dashed line box corresponding to the number 120a in fig. 4 is used to represent the above-mentioned conductive line on the lower surface. It can be seen that two first top surface test pads 131a, four through-silicon vias to be tested, and two second top surface test pads 131b in fig. 4 are sequentially connected in series. It should be noted that, for the test structure for detecting the connectivity of a plurality of through silicon vias connected in series provided in the embodiment shown in fig. 4, the number of the upper surface test pads is always 4, regardless of the number of through silicon vias to be tested included in the wafer.
As shown in FIG. 4, the tester 110 includes two voltage probes 112 and two current probes 113; after the two voltage probes 112 are electrically connected to a first top surface test pad group 131a of the two top surface test pad groups, and the two current probes 113 are electrically connected to a second top surface test pad 131b of the two top surface test pad groups, the tester 110 is configured to:
a voltage is applied to the first upper surface test pad 131a through the two voltage probes 112 and a current is applied to the second upper surface test pad 131b through the two current probes 113 to test the resistivity of each of the through silicon vias 210 to be tested.
For example, the test method may use a four-probe Kelvin test method. Specifically, first, a voltage is applied through the two voltage probes 112, and a current is applied through the two current probes 113, so as to eliminate the contact resistance. And then, whether the single silicon through hole is communicated or not can be verified by a four-probe Kelvin test method, and then, the resistance value of the single silicon through hole can be calculated by an Euler formula. For the four through-silicon-via series structure, the total resistance of the whole series circuit can be calculated by using Euler formula, and then compared with the resistance of a single through-silicon-via. If the resistance of a single through-silicon-via varies proportionally to the total resistance, four through-silicon-vias are connected. If the resistance of the individual through-silicon-vias varies disproportionately with respect to the total resistance, it can be determined that a short exists in the series path.
For example, the test structure provided in the embodiment shown in fig. 4 may also be applied to the through-silicon via connectivity test of a wafer having more than 4 through-silicon vias, and the connectivity test of a bonding pad in a wafer bonded to a base, in a manner similar to that in the embodiment shown in fig. 4.
In summary, the integrated circuit connectivity test system provided in the embodiments of the present invention can connect the through-silicon vias in series through the conductive wires and the test pads disposed on the wafer, and then lead the through-silicon vias to the upper surface of the wafer, and then determine the connectivity of each through-silicon via according to the detection data obtained by the detector, so as to simplify the connectivity test structure and reduce the test cost on the premise of ensuring the test accuracy.
Fig. 5 is a flow chart illustrating a method of fabricating an integrated circuit connectivity test system, see fig. 5, for application to a wafer used to form integrated circuits, the method comprising:
The plurality of test pads are used for placing a plurality of probes in a detector for testing resistivity.
In one possible implementation, the step 501 may include: electrically connecting each row of through silicon vias to be tested exposed on the upper surface of the wafer through the lead; and electrically connecting each row of silicon through holes to be tested or bonding pads exposed out of the lower surface of the wafer through the leads, wherein the bonding pads are used for bonding the lower part of the wafer with the substrate. In this case, the step 501 may include: arranging a plurality of upper surface test pads on the upper surface, and arranging a plurality of lower surface test pads on the lower surface; connecting a lead communicated with each row of through silicon vias to be tested with each upper surface test bonding pad; connecting a lead which is communicated with each row of through silicon holes to be tested or bonding welding spots with each lower surface test bonding pad; and performing hole opening processing on the position above the lower surface test pad of the wafer to obtain a test through silicon via, wherein the test through silicon via is used for electrically connecting the lower surface test pad to the upper surface through the wafer.
For example, for the test structure for detecting the connectivity of a plurality of through silicon vias connected in parallel provided in the embodiment shown in fig. 2, before step 501, it is first necessary to perform secondary wiring of wires by means of metal deposition, photolithography, etching, and the like on the upper surface of the wafer on which the through silicon vias have been fabricated. And leading out the silicon through holes in the same column to the test pad through secondary wiring. Metals such as Ti (titanium), TiN (titanium chloride), or Al (aluminum), and combinations thereof may be selected as the material for the wire and the test pad. For the lower surface of the wafer, the wafer needs to be thinned on the lower surface until the through silicon vias are exposed, the through silicon vias in the same row are connected and led out to the test pad through secondary wiring, and the manufacturing process and the material are the same as those of a front secondary wiring method. It should be noted that, before step 501, the manufacturing method further includes the step of fabricating and filling a through-silicon via on the wafer to form a fabricated through-silicon via. In the process, the through silicon via to be tested in the wafer and the probe through silicon via for leading out the lower surface test pad to the upper surface are manufactured and filled together.
For example, in the test structure for detecting the connectivity of a plurality of bonding pads connected in parallel according to the embodiment shown in fig. 3, after the connectivity of the through silicon vias is completed, the wire on the lower surface of the wafer is removed. And manufacturing the lead corresponding to the silicon through hole of the upper wafer on the substrate or the wafer to be bonded by using the same process and material. Then, a bonding bump (bump) is formed by a PVD (Physical vapor Deposition) process, and the material of the bonding bump is preferably Au-Sn (gold-tin), Au-In (gold-indium) and alloys thereof. And after bonding is finished, forming a row of leads on the upper surface of the wafer, connecting the silicon through holes exposed on the upper surface of the wafer, and forming a row of leads on the lower surface of the wafer, and connecting bonding pads on the lower surface of the wafer.
In a possible implementation manner, for the test structure for detecting connectivity of a plurality of through silicon vias connected in series provided in the embodiment shown in fig. 4, the step 501 may include: dividing a plurality of through silicon holes to be tested on the wafer into a plurality of groups of through silicon holes to be tested, wherein each group of through silicon holes to be tested comprises two through silicon holes to be tested which are connected in series through a lead positioned on the lower surface of the wafer; and the groups of through silicon vias to be tested are connected in series through a lead positioned on the upper surface. In this case, the step 502 includes: arranging two upper surface test bonding pad groups on the upper surface of the wafer, wherein each upper surface test bonding pad group comprises two upper surface test bonding pads which are mutually connected; and respectively connecting the two upper surface test pad groups in series to the plurality of groups of through silicon vias to be tested which are connected in series through a lead positioned on the upper surface. The materials of the adopted lead and the test pad are also metals such as Ti (titanium), TiN (titanium chloride) or Al (aluminum) and the like and combinations thereof.
Compared with the prior art, the manufacturing method of the integrated circuit connectivity test system provided by the embodiment of the invention can construct the connectivity test structure by adding the lead and the test pad on the wafer, simplify the manufacturing process flow and shorten the process period on the premise of ensuring the test accuracy, thereby lowering the manufacturing cost.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An integrated circuit connectivity test system applied to a wafer used to form an integrated circuit, the apparatus comprising: test subassembly and tester, the test subassembly includes: the testing device comprises a plurality of leads and a plurality of testing pads, wherein the leads and the testing pads are positioned on the upper surface and the lower surface of the wafer, the testing pads are connected with one or more through silicon vias to be tested in the wafer through the leads, and the tester comprises a plurality of probes;
after the probes are electrically connected with the test pads, the tester is used for applying voltage and/or current to the tester through the probes so as to determine the connectivity of the one or more through silicon vias to be tested according to the acquired resistivity.
2. The apparatus of claim 1, wherein the plurality of test pads comprises a plurality of upper surface test pads disposed on an upper surface of the wafer and a plurality of lower surface test pads disposed on a lower surface of the wafer, the lower surface test pads being electrically connected to the upper surface through the wafer by test through-silicon-vias.
3. The system for testing the connectivity of an integrated circuit of claim 2, wherein each of the conductive lines is connected to each of the columns of through-silicon vias to be tested exposed at the top surface and to the top surface test pads;
and each wire is communicated with each row of silicon through holes to be tested exposed from the lower surface and is connected with the lower surface test bonding pad.
4. The integrated circuit connectivity test system of claim 2, wherein the wafer is bonded to the substrate under the wafer, and each through-silicon via to be tested exposed on the lower surface of the wafer has a bonding pad;
each lead is communicated with each row of silicon through holes to be tested exposed out of the upper surface and is connected with the upper surface testing bonding pad;
and each wire is communicated with each row of bonding welding points exposed from the lower surface and is connected with the lower surface test bonding pad.
5. The integrated circuit connectivity test system of claim 4, wherein the tester is configured to apply a voltage or current to the tester via the plurality of probes after the plurality of probes are electrically connected to the test pads to determine the connectivity of one or more of the bond pads based on the obtained resistivity.
6. The integrated circuit connectivity test system of claim 1, wherein the wafer has a plurality of sets of through-silicon vias to be tested, each set of through-silicon vias to be tested including two through-silicon vias to be tested connected in series by a conductive line located on a lower surface of the wafer, the plurality of test pads include two sets of top surface test pads disposed on an upper surface of the wafer, each set of top surface test pads including two top surface test pads connected to each other;
the two upper surface test pad groups and the plurality of groups of through silicon vias to be tested are connected in series through a lead positioned on the upper surface.
7. The integrated circuit connectivity test system of claim 6, wherein the tester includes two voltage probes and two current probes;
after the two voltage probes are electrically connected with a first upper surface test pad group of the two upper surface test pad groups, and the two current probes are electrically connected with a second upper surface test pad of the two upper surface test pad groups, the tester is configured to:
and applying voltage to the first upper surface testing pad through the two voltage probes, and applying current to the second upper surface testing pad through the two current probes so as to determine the communication rate of the one or more through silicon vias to be tested according to the obtained resistivity.
8. A method for manufacturing an integrated circuit connectivity test system, applied to a wafer for forming an integrated circuit, the method comprising:
electrically connecting one or more through silicon vias to be tested in the wafer through a plurality of wires;
and electrically connecting one end of each wire with any one of a plurality of test pads, wherein the plurality of test pads are used for placing a plurality of probes in a detector for testing resistivity.
9. The method of claim 8, wherein the electrically connecting one or more through-silicon-vias to be tested in the wafer by a plurality of wires comprises:
electrically connecting each row of through silicon vias to be tested exposed on the upper surface of the wafer through the lead;
each row of silicon through holes to be tested or bonding pads exposed on the lower surface of the wafer are electrically connected through the wires, and the bonding pads are used for bonding the lower part of the wafer with a substrate:
the electrically connecting one end of each of the wires with any one of a plurality of test pads includes:
arranging a plurality of upper surface test pads on the upper surface, and arranging a plurality of lower surface test pads on the lower surface;
connecting a lead communicated with each row of through silicon vias to be tested with each upper surface test pad;
connecting a lead which is communicated with each row of through silicon holes to be tested or bonding welding spots with each lower surface test bonding pad;
and carrying out hole opening processing at a position above the lower surface test pad of the wafer to obtain a test through silicon via, wherein the test through silicon via is used for electrically connecting the lower surface test pad to the upper surface through the wafer.
10. The method of claim 8, wherein the electrically connecting one or more through-silicon-vias to be tested in the wafer by a plurality of wires comprises:
dividing a plurality of through silicon holes to be tested on the wafer into a plurality of groups of through silicon holes to be tested, wherein each group of through silicon holes to be tested comprises two through silicon holes to be tested which are connected in series through a lead positioned on the lower surface of the wafer;
the multiple groups of through silicon vias to be tested are connected in series through wires positioned on the upper surface;
the electrically connecting one end of each of the wires with any one of a plurality of test pads includes:
arranging two upper surface test bonding pad groups on the upper surface of the wafer, wherein each upper surface test bonding pad group comprises two upper surface test bonding pads which are connected with each other;
and connecting the two upper surface test pad groups in series to the plurality of groups of through silicon vias to be tested which are connected in series respectively through a lead positioned on the upper surface.
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