[go: up one dir, main page]

CN112701160A - Gallium nitride-based high-electron-mobility transistor epitaxial wafer and preparation method thereof - Google Patents

Gallium nitride-based high-electron-mobility transistor epitaxial wafer and preparation method thereof Download PDF

Info

Publication number
CN112701160A
CN112701160A CN202011450127.5A CN202011450127A CN112701160A CN 112701160 A CN112701160 A CN 112701160A CN 202011450127 A CN202011450127 A CN 202011450127A CN 112701160 A CN112701160 A CN 112701160A
Authority
CN
China
Prior art keywords
layer
semiconductor layer
epitaxial wafer
cap
gallium nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011450127.5A
Other languages
Chinese (zh)
Other versions
CN112701160B (en
Inventor
胡加辉
苏晨
李鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HC Semitek Zhejiang Co Ltd
Original Assignee
HC Semitek Zhejiang Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HC Semitek Zhejiang Co Ltd filed Critical HC Semitek Zhejiang Co Ltd
Priority to CN202011450127.5A priority Critical patent/CN112701160B/en
Publication of CN112701160A publication Critical patent/CN112701160A/en
Application granted granted Critical
Publication of CN112701160B publication Critical patent/CN112701160B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8171—Doping structures, e.g. doping superlattices or nipi superlattices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/854—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs further characterised by the dopants

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

本公开提供了一种氮化镓基高电子迁移率晶体管外延片及其制备方法，属于半导体技术领域。所述氮化镓基高电子迁移率晶体管外延片包括衬底以及层叠在所述衬底上的缓冲层、高阻缓冲层、沟道层、AlGaN势垒层和帽层，所述帽层包括依次层叠的第一半导体层和第二半导体层，所述第一半导体层为P型掺杂的InxGa1‑xN/MgN超晶格结构，0＜x＜1，所述第二半导体层为P型掺杂的AlyGa1‑yN/InzGa1‑zN超晶格结构，0＜y＜1，0＜z＜1。该外延片可以提高帽层中Mg的掺杂浓度，形成增强型HEMT，同时提高增强型HEMT外延片的晶体质量。

Figure 202011450127

The present disclosure provides a gallium nitride-based high electron mobility transistor epitaxial wafer and a preparation method thereof, belonging to the technical field of semiconductors. The gallium nitride-based high electron mobility transistor epitaxial wafer includes a substrate and a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer stacked on the substrate, and the cap layer includes A first semiconductor layer and a second semiconductor layer stacked in sequence, the first semiconductor layer is a P-type doped In x Ga 1-x N/MgN superlattice structure, 0<x<1, the second semiconductor layer The layer is a P-type doped AlyGa1 -yN / InzGa1 -zN superlattice structure, 0<y<1, 0<z<1. The epitaxial wafer can increase the doping concentration of Mg in the cap layer to form an enhancement type HEMT and at the same time improve the crystal quality of the enhancement type HEMT epitaxial wafer.

Figure 202011450127

Description

Gallium nitride-based high-electron-mobility transistor epitaxial wafer and preparation method thereof
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a gallium nitride-based high-electron-mobility transistor epitaxial wafer and a preparation method thereof.
Background
An HEMT (High Electron Mobility Transistor) based on an AlGaN (aluminum gallium nitride)/GaN (gallium nitride) heterostructure has High current density, critical breakdown voltage and Electron Mobility, and has very important application value in the fields of microwave power and High-temperature electronic devices.
HEMTs typically include a chip and source, drain and gate electrodes located on the chip. The chip is obtained from an epitaxial wafer. The structure of the gallium nitride epitaxial wafer generally comprises a substrate, and a buffer layer, a high-resistance buffer layer, a GaN channel layer, an AlGaN barrier layer and a cap layer which are sequentially stacked on the substrate. The common growth process for realizing the enhancement type GaN HEMT heterojunction generally comprises the growth of structures such as a non-polarization face heterojunction, a thin barrier layer, a P type GaN cap layer and the like, wherein the P type GaN cap layer is used for realizing the enhancement type GaN HEMT heterojunction most conveniently, and the difficulty is the problem of low P type doping concentration.
The P-type GaN cap layer is mainly doped with Mg at present, but the Mg doping has the problem of high activation energy caused by H passivation, the ionization rate of Mg is low, and the P-type GaN cap layer can realize the P-type GaN cap layer only by high doping concentration. Meanwhile, due to the fact that large lattice mismatch exists between the GaN layer and the silicon carbide substrate, the sapphire substrate or the monocrystalline silicon substrate, stress is easy to generate, the quality of crystals of the finally grown gallium nitride-based epitaxial wafer is poor, the quality of the crystals of the epitaxial wafer is poor, and doping of Mg in the P-type GaN cap layer can be affected.
Disclosure of Invention
The embodiment of the disclosure provides a gallium nitride-based high electron mobility transistor epitaxial wafer and a preparation method thereof, which can improve the doping concentration of Mg in a cap layer, form an enhanced HEMT and improve the crystal quality of the enhanced HEMT epitaxial wafer. The technical scheme is as follows:
in a first aspect, there is provided a gallium nitride-based high electron mobility transistor epitaxial wafer comprising a substrate and, stacked thereon, a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer,
the cap layer comprises a first semiconductor layer and a second semiconductor layer which are sequentially stacked, wherein the first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure, x is more than 0 and less than 1, and the second semiconductor layer is P-type doped AlyGa1-yN/InzGa1-zN superlattice structure, y is more than 0 and less than 1, and z is more than 0 and less than 1.
Optionally, the thickness of the cap layer is 4nm to 1 um.
Optionally, In the first semiconductor layerxGa1-xThe thickness of the N layer is 1 nm-100 nm, and the thickness of the MgN layer in the first semiconductor layer is 1 nm-50 nm.
Optionally, Al in the second semiconductor layeryGa1-yThe thickness of the N layer is 1 nm-100 nm, and In the second semiconductor layerzGa1-zThe thickness of the N layer is 1 nm-100 nm.
In a second aspect, a method for preparing an epitaxial wafer of a gallium nitride-based high electron mobility transistor is provided, the method comprising:
providing a substrate;
sequentially growing a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer and a cap layer on the substrate;
the cap layer comprises a first semiconductor layer and a second semiconductor layer which are sequentially stacked, wherein the first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure, x is more than 0 and less than 1, and the second semiconductor layer is P-type doped AlyGa1-yN/InzGa1-zN superlattice structure, y is more than 0 and less than 1, and z is more than 0 and less than 1.
Optionally, growing the cap layer comprises:
introducing nitrogen into the reaction cavity, stopping introducing hydrogen, and growing the first semiconductor layer;
introducing hydrogen into the reaction cavity, stopping introducing the nitrogen, and growing Al in the second semiconductor layeryGa1-yN layers;
introducing nitrogen into the reaction chamber, stopping introducing hydrogen, and growing In the second semiconductor layerzGa1-zAnd N layers.
Optionally, a growth temperature of the first semiconductor layer is lower than a growth temperature of the AlGaN barrier layer.
Optionally, the InxGa1-xThe growth temperature of the N layer is equal to that of the MgN layer.
Optionally, the growth temperature of the second semiconductor layer is 960-1000 DEG C
Alternatively, the AlyGa1-yThe growth temperature of the N layer is higher than that of the InzGa1-zGrowth temperature of the N layer.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
the cap layer is arranged to comprise a first semiconductor layer and a second semiconductor layer which are sequentially stacked, wherein the first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure. InxGa1-xThe lattice constant of the N layer is large, the lattice constant of the MgN layer is small, and the two layers are alternately arranged, so that the stress release is facilitated. The second semiconductor layer is P-type doped AlyGa1-yN/InzGa1-zAn N superlattice structure. Likewise, InxGa1-xThe lattice constant of the N layer is large, the lattice constant of the MgN layer is small, the two layers are alternately arranged, and the release of stress is facilitated, so that the stress gathered at the bottom layer of the epitaxial wafer can be released, the gallium nitride-based HEMT epitaxial wafer with high crystal quality is formed, and the doping of Mg in the cap layer is facilitated. Meanwhile, the first semiconductor layer and the second semiconductor layer both contain In, and the In can reduce the activation energy of Mg, so that the doping concentration of Mg In the cap layer can be improved, and the enhancement type HEMT is formed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a gallium nitride-based high electron mobility transistor according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a cap layer provided by the embodiment of the present disclosure;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a gallium nitride-based high electron mobility transistor according to an embodiment of the present disclosure;
fig. 4 is a flowchart of a method for manufacturing another gan-based hemt epitaxial wafer according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a gallium nitride-based high electron mobility transistor epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 1, the gallium nitride-based high electron mobility transistor epitaxial wafer includes a substrate 1, and a buffer layer 2, a high-resistance buffer layer 3, a channel layer 4, an AlGaN barrier layer 5, and a cap layer 6 stacked on the substrate 1.
Fig. 2 is a schematic structural diagram of a cap layer provided by an embodiment of the present disclosure, and as shown in fig. 2, the cap layer 6 includes a first semiconductor layer 61 and a second semiconductor layer 62 that are sequentially stacked. The first semiconductor layer 61 is P-type doped InxGa1-xN/MgN superlattice structure, x is more than 0 and less than 1, and the second semiconductor layer 62 is P-type doped AlyGa1-yN/InzGa1-zN superlattice structure, y is more than 0 and less than 1, and z is more than 0 and less than 1.
The embodiment of the disclosure sets the cap layer to include a first semiconductor layer and a second semiconductor layer which are sequentially stacked, wherein the first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure. InxGa1-xThe lattice constant of the N layer is large, the lattice constant of the MgN layer is small, and the two layers are alternately arranged, so that the stress release is facilitated. The second semiconductor layer is P-type doped AlyGa1-yN/InzGa1-zAn N superlattice structure. Likewise, InxGa1-xThe lattice constant of the N layer is large, the lattice constant of the MgN layer is small, the two layers are alternately arranged, and the release of stress is facilitated, so that the stress gathered at the bottom layer of the epitaxial wafer can be released, the gallium nitride-based HEMT epitaxial wafer with high crystal quality is formed, and the doping of Mg in the cap layer is facilitated. Meanwhile, the first semiconductor layer and the second semiconductor layer both contain In, and the In can reduce the activation energy of Mg, so that the doping concentration of Mg In the cap layer can be improved, and the enhancement type HEMT is formed.
Wherein In the first semiconductor layer 61xGa1-xThe N layer is in contact with the AlGaN barrier layer 5, which is beneficial to improving the stress accumulated on the AlGaN barrier layer, thereby improving the crystal quality of the epitaxial wafer.
Optionally, the number of superlattices of the first semiconductor layer 61 and the second semiconductor layer 62 is greater than 2, so as to ensure that each semiconductor layer can achieve a better stress relief effect.
Optionally, the thickness of the cap layer 6 is 4nm to 1 um.
If the thickness of the cap layer 6 is less than 4nm, the GaN-based enhancement mode hemt device cannot be realized. If the thickness of the cap layer 6 is greater than 1um, the two-dimensional electron gas concentration of the GaN/AlGaN heterojunction interface is affected due to the excessive thickness of the cap layer.
Optionally, both the first semiconductor layer 61 and the second semiconductor layer 62 are Mg doped. Wherein the doping concentration of Mg in the first semiconductor layer 61 is 1 × 1020cm-3～5*1020cm-3The doping concentration of Mg in the second semiconductor layer 62 is 1 x 1019cm-3～9*1019cm-3。
By doping Mg in the cap layer, high doping concentration can be obtained, so that high hole concentration is obtained, and the enhancement type HEMT is realized.
Optionally, In the first semiconductor layer 61xGa1-xThe thickness of the N layer is1nm to 100nm, and the thickness of the MgN layer in the first semiconductor layer 61 is 1nm to 50 nm.
If InxGa1-xThe thickness of the N layer is too thick, which may cause a large stress in the first semiconductor layer 61, thereby affecting the crystalline quality of the cap layer. If InxGa1-xIf the thickness of the N layer is too thin, it does not function to lower the activation energy of Mg. However, the MgN material itself does not grow well, and if the thickness of the MgN is too thick, more defects are generated, and meanwhile, the diffusion of Mg is caused to influence the performance of the device.
Optionally, Al in the second semiconductor layer 62yGa1-yThe thickness of the N layer is 1nm to 100nm, and In the second semiconductor layer 62zGa1-zThe thickness of the N layer is 1 nm-100 nm.
Due to AlyGa1-ySmall compressive strain of N layer, InzGa1-zThe tensile strain of the N layer is large, so that the stress of the epitaxial layer can be further improved by controlling the thicknesses of the AlGaN sublayer and the InGaN sublayer within the value range, and the growth quality of the epitaxial wafer can be improved.
Alternatively, 0 < x < 0.5, 0 < y < 0.4, 0 < z < 0.5.
Illustratively, the first semiconductor layer 61 is P-type doped In0.1Ga0.9A superlattice structure of N/MgN, and the second semiconductor layer 62 is P-type doped Al0.25Ga0.75N/In0.2Ga0.8An N superlattice structure. The doping concentration and the crystal quality of the epitaxial wafer obtained in this case are the best.
Optionally, the buffer layer 2 is an AlN/AlGaN layer, wherein the AlN layer has a thickness of 30nm and the AlGaN layer has a thickness of 300 nm.
Optionally, the high resistance buffer layer 3 is a C-doped GaN layer. Wherein, the thickness of the high resistance buffer layer 3 is 1.2 um. The high-resistance buffer layer 3 can realize the beneficial effect of dislocation filtering and improve the crystal quality of the epitaxial wafer.
Optionally, the channel layer 4 is a GaN layer with a thickness of 400 nm. The channel layer 4 is a transport channel for two-dimensional electron gas, and is required to have a flat surface and a low doping concentration so as to reduce scattering of the two-dimensional electron gas.
Optionally, the gallium nitride-based high electron mobility transistor epitaxial wafer further comprises an AlN insertion layer 7 disposed between the channel layer 4 and the AlGaN barrier layer 5, and the AlN insertion layer 7 has a thickness of 2 nm. The AlN insert layer 7 can increase the polarization effect of the interface, reduce the scattering of the interface and obviously improve the concentration and the mobility of the two-dimensional electron gas.
Optionally, the AlGaN barrier layer 5 has a thickness of 100 nm. The AlGaN barrier layer 5 generates a large amount of positive polarization charges at the interface between the barrier layer 5 and the channel layer 4 by its own large spontaneous polarization or piezoelectric polarization, and the positive polarization charges attract electrons to form a two-dimensional electron gas.
Fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a gallium nitride-based high electron mobility transistor according to an embodiment of the present disclosure, and as shown in fig. 3, the method includes:
step 301, a substrate is provided.
Step 302, growing a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer and a cap layer on a substrate in sequence.
The cap layer comprises a first semiconductor layer and a second semiconductor layer which are sequentially stacked. The first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure, x is more than 0 and less than 1, and the second semiconductor layer is P-type doped AlyGa1-yN/InzGa1-zN superlattice structure, y is more than 0 and less than 1, and z is more than 0 and less than 1.
The embodiment of the disclosure sets the cap layer to include a first semiconductor layer and a second semiconductor layer which are sequentially stacked, wherein the first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure. InxGa1-xThe lattice constant of the N layer is large, the lattice constant of the MgN layer is small, and the two layers are alternately arranged, so that the stress release is facilitated. The second semiconductor layer is P-type doped AlyGa1-yN/InzGa1-zAn N superlattice structure. Likewise, InxGa1-xThe lattice constant of the N layer is large, the lattice constant of the MgN layer is small, the two layers are alternately arranged, the release of stress is facilitated, and therefore the stress gathered at the bottom layer of the epitaxial wafer can be released,and forming the gallium nitride-based HEMT epitaxial wafer with higher crystal quality, thereby being beneficial to doping Mg in the cap layer. Meanwhile, the first semiconductor layer and the second semiconductor layer both contain In, and the In can reduce the activation energy of Mg, so that the doping concentration of Mg In the cap layer can be improved, and the enhancement type HEMT is formed.
Fig. 4 is a flowchart of a method for manufacturing another gan-based hemt epitaxial wafer according to an embodiment of the present disclosure, where as shown in fig. 4, the method includes:
step 401, a substrate is provided.
Illustratively, the substrate may be a sapphire, Si, or SiC substrate.
In this embodiment, a buffer layer, a high-resistance buffer layer, a channel layer, an AlN insertion layer, an AlGaN barrier layer, and a cap layer may be sequentially grown on a substrate by MOCVD (Metal organic chemical vapor Deposition). The temperature and pressure controlled during growth are actually the temperature and pressure within the reaction chamber of the MOCVD tool.
Illustratively, high purity H is employed2Or N2As the carrier gas, TMGa, TMAl, TMIn and NH were used3Respectively as Ga source, Al source, In source and N source, adopting CCl4As the C dopant of the high-resistance buffer layer, Cp is used2And Mg is used as a P-type dopant, and the epitaxial wafer growth is completed by adopting metal organic chemical vapor deposition equipment or other equipment.
Exemplarily, step 401 may further include:
subjecting the substrate to high temperature H2And (5) chemical annealing treatment.
The annealing treatment mode comprises the following steps: and (3) processing the substrate for 5-6 min at high temperature in a reaction chamber of the MOCVD equipment under the atmosphere of hydrogen (serving as carrier gas). Wherein the temperature of the reaction chamber is 1000-1300 ℃, and the pressure of the reaction chamber is controlled at 200-500 torr.
Step 402, growing a buffer layer on a substrate.
Wherein, the buffer layer is an AlN/AlGaN layer.
Illustratively, in pure H2Atmosphere, temperature of 600-900 ℃, reaction chamberIntroducing TMAl as a group III source and NH3 as a group V source under the pressure of 25-300 torr, and growing an AlN layer with the thickness of 30nm by taking the V/III ratio of 100-2000.
Illustratively, in pure H2Introducing TMAl/TMGa as a III group source, NH under the conditions of atmosphere, temperature of 950-1200 ℃ and reaction chamber pressure of 25-200 torr3As a V group source, an AlGaN layer with a V/III ratio of 100-2000 and a thickness of 300nm is grown.
Step 403, growing a high-resistance buffer layer on the buffer layer.
Wherein, the high-resistance buffer layer is a GaN layer doped with C.
Illustratively, in pure H2Introducing TMGa as a III group source and NH under the conditions of atmosphere, temperature of 950-1200 ℃ and pressure of 25-200 torr in a reaction chamber3As a V-group source, a high-resistance buffer layer with a V/III ratio of 100-2000 and a growth thickness of 1.2um is taken.
Step 404, growing a channel layer on the high resistance buffer layer.
Exemplarily at N2、H2Introducing TMGa as a III group source and NH under the conditions of atmosphere, temperature of 1000-1200 ℃ and reaction chamber pressure of 100-500 torr3And as a V-group source, taking a GaN channel layer with the V/III ratio of 5000-10000 and the growth thickness of 400 nm.
Step 405, an AlN interposer is grown on the channel layer.
Illustratively, in pure N2Introducing TMAl as a group III source and NH under the conditions of atmosphere, temperature of 800-1010 ℃ and reaction chamber pressure of 50-200 torr3As a V group source, an AlN insertion layer with a V/III ratio of 100-2000 and a thickness of 2nm is grown.
Step 406, an AlGaN barrier layer is grown on the AlN interposer.
Illustratively, in pure H2Under the conditions of atmosphere, temperature of 950-1200 ℃ and reaction chamber pressure of 100-200 torr, introducing TMGa and TMAl as III group source, NH3As a V group source, an AlGaN barrier layer with a V/III ratio of 5000-10000 and a growth thickness of 100nm is taken.
Step 407, grow a cap layer on the AlGaN barrier layer.
The cap layer comprises a first semiconductor layer and a second semiconductor layer which are sequentially stacked. The first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure, x is more than 0 and less than 1, and the second semiconductor layer is P-type doped AlyGa1-yN/InzGa1-zN superlattice structure, y is more than 0 and less than 1, and z is more than 0 and less than 1.
Optionally, the number of superlattices of the first semiconductor layer and the second semiconductor layer is greater than 2, so as to ensure that each semiconductor layer can achieve a better stress release effect.
Optionally, the cap layer has a thickness of 4nm to 1 um.
If the thickness of the cap layer is less than 4nm, the cap layer does not function to realize the GaN-based enhanced HEMT device. If the thickness of the cap layer is larger than 1um, the two-dimensional electron gas concentration of the GaN/AlGaN heterojunction interface is influenced due to the excessive thickness of the cap layer.
Optionally, both the first semiconductor layer and the second semiconductor layer are Mg doped. Wherein the doping concentration of Mg in the first semiconductor layer is 1 x 1020cm-3～5*1020cm-3The doping concentration of Mg in the second semiconductor layer is 1 x 1019cm-3～9*1019cm-3。
By doping Mg in the cap layer, high doping concentration can be obtained, so that high hole concentration is obtained, and the enhancement type HEMT is realized.
Optionally, In the first semiconductor layerxGa1-xThe thickness of the N layer is 1 nm-100 nm, and the thickness of the MgN layer in the first semiconductor layer is 1 nm-50 nm.
If InxGa1-xThe thickness of the N layer is too thick, which may cause a large stress in the first semiconductor layer, thereby affecting the crystalline quality of the cap layer. If InxGa1-xThe thickness of the N layer is too thin to serve as a complementary effect in reducing the gallium nitride material. However, the MgN material itself does not grow well, and if the thickness of the MgN is too thick, more defects are generated, and meanwhile, the diffusion of Mg is caused to influence the performance of the device.
Optionally, a second semiconductor layerAl in (1)yGa1-yThe thickness of the N layer is 1 nm-100 nm, and In the second semiconductor layerzGa1-zThe thickness of the N layer is 1 nm-100 nm.
Due to AlyGa1-ySmall compressive strain of N layer, InzGa1-zThe tensile strain of the N layer is large, so that the stress of the epitaxial layer can be further improved by controlling the thicknesses of the AlGaN sublayer and the InGaN sublayer within the value range, and the growth quality of the epitaxial wafer can be improved.
Alternatively, 0 < x < 0.5, 0 < y < 0.4, 0 < z < 0.5.
Illustratively, the first semiconductor layer is P-type doped In0.1Ga0.9N/MgN superlattice structure, and P-type doped Al as the second semiconductor layer0.25Ga0.75N/In0.2Ga0.8An N superlattice structure. The doping concentration and the crystal quality of the epitaxial wafer obtained in this case are the best.
Illustratively, step 407 may include:
introducing nitrogen into the reaction cavity, stopping introducing hydrogen, and growing a first semiconductor layer;
introducing hydrogen into the reaction cavity, stopping introducing the nitrogen, and growing Al in the second semiconductor layeryGa1-yN layers;
introducing nitrogen into the reaction chamber, stopping introducing hydrogen, and growing In the second semiconductor layerzGa1-zAnd N layers.
The first semiconductor layer grows In a pure nitrogen atmosphere, and doping of In atoms and Mg atoms In the first semiconductor layer is facilitated. While Al is grown only when the second semiconductor layer is grownyGa1-yAnd hydrogen is introduced during the N layer, so that the introduction of hydrogen can be reduced, the probability that Mg in the cap layer is passivated by H is reduced, and the doping of Mg is further improved. Meanwhile, the AlGaN sublayer grows under the pure hydrogen atmosphere, and the hydrogen is strong reducing gas and can take away impurities, so that a cap layer with higher crystal quality can be obtained.
Optionally, the growth temperature of the first semiconductor layer is lower than the growth temperature of the AlGaN barrier layer.
In the embodiment of the present disclosure, the growth temperature of the first semiconductor layer is 950 ℃ to 980 ℃.
The growth temperature of the AlGaN barrier layer is 950-1200 ℃, so that a first semiconductor layer is grown on the barrier layer, and the growth temperature of the first semiconductor layer is lower than that of the barrier layer, so that the influence of Mg on a device caused by rapid diffusion of Mg to a channel layer can be relieved. If the growth temperature of the first semiconductor layer is too high, the barrier layer crystals may be damaged, and in severe cases, the epitaxial wafer may be cracked. If the growth temperature of the first semiconductor layer is too low, the crystal quality of the grown first semiconductor layer is poor.
Alternatively, InxGa1-xThe growth temperature of the N layer is equal to that of the MgN layer, so that the growth control is facilitated.
Optionally, the growth temperature of the second semiconductor layer is 960 ℃ to 1000 ℃.
If the growth temperature of the second semiconductor layer is too high, the crystal quality of the previously grown epitaxial layer may be deteriorated. If the growth temperature of the second semiconductor layer is too low, the crystal quality of the grown first semiconductor layer is poor.
Alternatively, AlyGa1-yThe growth temperature of the N layer is higher than InzGa1-zGrowth temperature of the N layer. Wherein, AlyGa1-yThe growth temperature of the N layer is higher, which is beneficial to improving the crystal quality of the cap layer, thereby improving the crystal quality of the GaN-based HEMT device. High temperature will affect the In doping, thus In will be introducedzGa1-zThe growth temperature of the N layer is set lower.
And step 408, annealing the epitaxial wafer in a furnace.
Illustratively, after the epitaxial growth is finished, the temperature in a reaction chamber of the MOCVD equipment is reduced, annealing treatment is carried out in a nitrogen atmosphere, the annealing temperature can be 600-900 ℃, the annealing time is 5-15 minutes, and then the temperature is reduced to room temperature, so that the epitaxial growth is finished. The decomposition of the complex in the cap layer can be enhanced by annealing the epitaxial wafer, so that the Mg acceptor which is passivated by H originally can be activated, and a current carrier is provided for P-type conductivity.
The disclosed embodiment is realized by combining the cap layerThe method comprises sequentially stacking a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure. InxGa1-xThe lattice constant of the N layer is large, the lattice constant of the MgN layer is small, and the two layers are alternately arranged, so that the stress release is facilitated. The second semiconductor layer is P-type doped AlyGa1-yN/InzGa1-zAn N superlattice structure. Likewise, InxGa1-xThe lattice constant of the N layer is large, the lattice constant of the MgN layer is small, the two layers are alternately arranged, and the release of stress is facilitated, so that the stress gathered at the bottom layer of the epitaxial wafer can be released, the gallium nitride-based HEMT epitaxial wafer with high crystal quality is formed, and the doping of Mg in the cap layer is facilitated. Meanwhile, the first semiconductor layer and the second semiconductor layer both contain In, and the In can reduce the activation energy of Mg, so that the doping concentration of Mg In the cap layer can be improved, and the enhancement type HEMT is formed.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims (10)

1. A gallium nitride-based high electron mobility transistor epitaxial wafer comprising a substrate, and a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer, and a cap layer laminated on the substrate,
the cap layer comprises a first semiconductor layer and a second semiconductor layer which are sequentially stacked, wherein the first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure, x is more than 0 and less than 1, and the second semiconductor layer is P-type doped AlyGa1-yN/InzGa1- zN superlattice structure, y is more than 0 and less than 1, and z is more than 0 and less than 1.
2. The GaN-based high electron mobility transistor epitaxial wafer of claim 1, wherein the thickness of the cap layer is 4nm to 1 um.
3. The gallium nitride-based high electron mobility transistor epitaxial wafer of claim 1, wherein In the first semiconductor layerxGa1-xThe thickness of the N layer is 1 nm-100 nm, and the thickness of the MgN layer in the first semiconductor layer is 1 nm-50 nm.
4. The gallium nitride-based high electron mobility transistor epitaxial wafer of claim 1, wherein the Al in the second semiconductor layeryGa1-yThe thickness of the N layer is 1 nm-100 nm, and In the second semiconductor layerzGa1-zThe thickness of the N layer is 1 nm-100 nm.
5. A preparation method of a gallium nitride-based high electron mobility transistor epitaxial wafer comprises the following steps:
providing a substrate;
sequentially growing a buffer layer, a high-resistance buffer layer, a channel layer, an AlGaN barrier layer and a cap layer on the substrate;
it is characterized in that the preparation method is characterized in that,
the cap layer comprises a first semiconductor layer and a second semiconductor layer which are sequentially stacked, wherein the first semiconductor layer is P-type doped InxGa1-xN/MgN superlattice structure, x is more than 0 and less than 1, and the second semiconductor layer is P-type doped AlyGa1-yN/InzGa1- zN superlattice structure, y is more than 0 and less than 1, and z is more than 0 and less than 1.
6. The method of fabricating of claim 5, wherein growing the cap layer comprises:
introducing nitrogen into the reaction cavity, stopping introducing hydrogen, and growing the first semiconductor layer;
introducing hydrogen into the reaction cavity, stopping introducing the nitrogen, and growing Al in the second semiconductor layeryGa1-yN layers;
introducing nitrogen into the reaction cavity, stopping introducing hydrogen, and growingIn the second semiconductor layerzGa1-zAnd N layers.
7. The method according to claim 5, wherein a growth temperature of the first semiconductor layer is lower than a growth temperature of the AlGaN barrier layer.
8. The method according to claim 7, wherein the In isxGa1-xThe growth temperature of the N layer is equal to that of the MgN layer.
9. The method according to claim 5, wherein the second semiconductor layer is grown at a temperature of 960 ℃ to 1000 ℃.
10. The method according to claim 9, wherein the Al is presentyGa1-yThe growth temperature of the N layer is higher than that of the InzGa1-zGrowth temperature of the N layer.
CN202011450127.5A 2020-12-09 2020-12-09 Gallium nitride-based high-electron-mobility transistor epitaxial wafer and preparation method thereof Active CN112701160B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011450127.5A CN112701160B (en) 2020-12-09 2020-12-09 Gallium nitride-based high-electron-mobility transistor epitaxial wafer and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011450127.5A CN112701160B (en) 2020-12-09 2020-12-09 Gallium nitride-based high-electron-mobility transistor epitaxial wafer and preparation method thereof

Publications (2)

Publication Number Publication Date
CN112701160A true CN112701160A (en) 2021-04-23
CN112701160B CN112701160B (en) 2022-08-09

Family

ID=75508594

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011450127.5A Active CN112701160B (en) 2020-12-09 2020-12-09 Gallium nitride-based high-electron-mobility transistor epitaxial wafer and preparation method thereof

Country Status (1)

Country Link
CN (1) CN112701160B (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113659006A (en) * 2021-08-05 2021-11-16 王晓波 HEMT epitaxial device based on third-generation semiconductor GaN material and growth method thereof
CN114093757A (en) * 2021-10-14 2022-02-25 江苏第三代半导体研究院有限公司 Gallium nitride transistor epitaxial structure capable of improving surface electron concentration and preparation method thereof
CN114250510A (en) * 2021-12-20 2022-03-29 中电化合物半导体有限公司 Epitaxial structure for gallium nitride-based radio frequency device and preparation method thereof
US20220216304A1 (en) * 2021-01-03 2022-07-07 Cambridge Electronics, Inc. Iii-nitride transistor with non-uniform channel regions
CN114855273A (en) * 2022-04-20 2022-08-05 江西兆驰半导体有限公司 Epitaxial wafer preparation method, epitaxial wafer and light emitting diode
CN115954378A (en) * 2023-03-15 2023-04-11 江西兆驰半导体有限公司 Gallium nitride power device and preparation method thereof
WO2023184199A1 (en) * 2022-03-30 2023-10-05 Innoscience (suzhou) Semiconductor Co., Ltd. Nitride-based semiconductor device and method for manufacturing the same
CN117012809A (en) * 2023-09-27 2023-11-07 江西兆驰半导体有限公司 Gallium nitride-based high electron mobility transistor epitaxial wafer and preparation method thereof, HEMT
CN117613071A (en) * 2024-01-24 2024-02-27 英诺赛科（珠海）科技有限公司 Enhancement mode gallium nitride high electron mobility transistor device
CN118186577A (en) * 2024-03-15 2024-06-14 华厦半导体(宁波)有限公司 Gallium nitride epitaxial structure and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101183642A (en) * 2007-12-10 2008-05-21 厦门大学 A preparation method of p-GaN low-resistance ohmic contact
CN101572288A (en) * 2009-05-27 2009-11-04 厦门大学 GaN-based multi-quantum well super light-emitting diode (SLED) and preparation method thereof
EP2696365A2 (en) * 2012-08-09 2014-02-12 Samsung Electronics Co., Ltd Semiconductor buffer structure, semiconductor device including the same, and method of manufacturing semiconductor device using semiconductor buffer structure
WO2017092450A1 (en) * 2015-11-30 2017-06-08 天津三安光电有限公司 Light-emitting diode epitaxial wafer structure and preparation method thereof
CN107393956A (en) * 2017-07-06 2017-11-24 中国科学院半导体研究所 Enhancement type high electron mobility transistor and preparation method comprising p-type superlattices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101183642A (en) * 2007-12-10 2008-05-21 厦门大学 A preparation method of p-GaN low-resistance ohmic contact
CN101572288A (en) * 2009-05-27 2009-11-04 厦门大学 GaN-based multi-quantum well super light-emitting diode (SLED) and preparation method thereof
EP2696365A2 (en) * 2012-08-09 2014-02-12 Samsung Electronics Co., Ltd Semiconductor buffer structure, semiconductor device including the same, and method of manufacturing semiconductor device using semiconductor buffer structure
WO2017092450A1 (en) * 2015-11-30 2017-06-08 天津三安光电有限公司 Light-emitting diode epitaxial wafer structure and preparation method thereof
CN107393956A (en) * 2017-07-06 2017-11-24 中国科学院半导体研究所 Enhancement type high electron mobility transistor and preparation method comprising p-type superlattices

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220216304A1 (en) * 2021-01-03 2022-07-07 Cambridge Electronics, Inc. Iii-nitride transistor with non-uniform channel regions
CN113659006A (en) * 2021-08-05 2021-11-16 王晓波 HEMT epitaxial device based on third-generation semiconductor GaN material and growth method thereof
CN113659006B (en) * 2021-08-05 2024-05-24 王晓波 A HEMT epitaxial device based on third-generation semiconductor GaN material and its growth method
CN114093757A (en) * 2021-10-14 2022-02-25 江苏第三代半导体研究院有限公司 Gallium nitride transistor epitaxial structure capable of improving surface electron concentration and preparation method thereof
CN114250510A (en) * 2021-12-20 2022-03-29 中电化合物半导体有限公司 Epitaxial structure for gallium nitride-based radio frequency device and preparation method thereof
WO2023184199A1 (en) * 2022-03-30 2023-10-05 Innoscience (suzhou) Semiconductor Co., Ltd. Nitride-based semiconductor device and method for manufacturing the same
CN114855273B (en) * 2022-04-20 2023-11-21 江西兆驰半导体有限公司 Epitaxial wafer preparation method, epitaxial wafer and light-emitting diode
CN114855273A (en) * 2022-04-20 2022-08-05 江西兆驰半导体有限公司 Epitaxial wafer preparation method, epitaxial wafer and light emitting diode
CN115954378A (en) * 2023-03-15 2023-04-11 江西兆驰半导体有限公司 Gallium nitride power device and preparation method thereof
CN117012809A (en) * 2023-09-27 2023-11-07 江西兆驰半导体有限公司 Gallium nitride-based high electron mobility transistor epitaxial wafer and preparation method thereof, HEMT
CN117012809B (en) * 2023-09-27 2023-12-22 江西兆驰半导体有限公司 Gallium nitride-based high electron mobility transistor epitaxial wafer and preparation method thereof, HEMT
CN117613071A (en) * 2024-01-24 2024-02-27 英诺赛科（珠海）科技有限公司 Enhancement mode gallium nitride high electron mobility transistor device
CN117613071B (en) * 2024-01-24 2024-03-29 英诺赛科（珠海）科技有限公司 Enhancement mode gallium nitride high electron mobility transistor device
CN118186577A (en) * 2024-03-15 2024-06-14 华厦半导体(宁波)有限公司 Gallium nitride epitaxial structure and manufacturing method thereof

Also Published As

Publication number Publication date
CN112701160B (en) 2022-08-09

Similar Documents

Publication Publication Date Title
CN112701160B (en) Gallium nitride-based high-electron-mobility transistor epitaxial wafer and preparation method thereof
CN112216742B (en) Gallium nitride-based high-electron-mobility transistor epitaxial wafer and preparation method thereof
JP2003059948A (en) Semiconductor device and production method therefor
WO2005015642A1 (en) Semiconductor device and manufacturing method thereof
JP2008521248A (en) Nitride-based transistors and cap and / or inert layers of transistor structures and methods for their manufacture
CN108767008B (en) A kind of HEMT with high resistance GaN buffer layer and preparation method thereof
EP2973658A1 (en) REO GATE DIELECTRIC FOR III-N DEVICE ON Si SUBSTRATE
TWI663635B (en) Semiconductor material growth of a high resistivity nitride buffer layer using ion implantation
CN108847435B (en) Light emitting diode epitaxial wafer and preparation method thereof
CN113782600B (en) Enhancement type GaN-based HEMT device, device epitaxy and preparation method thereof
CN116314278B (en) High electron mobility transistor epitaxial structure, preparation method and HEMT device
US8994032B2 (en) III-N material grown on ErAIN buffer on Si substrate
CN104303268A (en) Epitaxial substrate, semiconductor device, and method for manufacturing semiconductor device
CN112736131A (en) YAlN/GaN high electron mobility transistor and manufacturing method thereof
CN116960173B (en) High electron mobility transistor epitaxial structure, preparation method and HEMT device
CN117293240A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN110600547B (en) Gallium nitride-based semiconductor device and method of making the same
CN106972058A (en) A kind of semiconductor devices and preparation method thereof
CN107658374B (en) Epitaxial wafer of light emitting diode and preparation method thereof
CN118522763A (en) GaN-based high electron mobility transistor and preparation method thereof
CN109686823B (en) A kind of gallium nitride-based light-emitting diode epitaxial wafer and manufacturing method thereof
CN109166950B (en) Semiconductor chip of light emitting diode, quantum well layer of semiconductor chip and manufacturing method of quantum well layer
CN117497562A (en) A silicon-based GaN epitaxial structure with a stepped barrier layer and its preparation method
JP2009246307A (en) Semiconductor device and method of manufacturing the same
CN115101413A (en) Preparation method and device of enhanced field effect transistor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant