CN112701106B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112701106B CN112701106B CN201911006477.XA CN201911006477A CN112701106B CN 112701106 B CN112701106 B CN 112701106B CN 201911006477 A CN201911006477 A CN 201911006477A CN 112701106 B CN112701106 B CN 112701106B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 230000008569 process Effects 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 18
- 239000000463 material Substances 0.000 description 11
- 230000009467 reduction Effects 0.000 description 7
- 238000012546 transfer Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the semiconductor structure comprises a substrate, a plurality of first conductive layers, a plurality of first plugs, a plurality of conductive structures connected with the first plugs and electrically isolated from the first gate structures, wherein the substrate comprises an inactive area, the surface of the inactive area is provided with a plurality of first gate structures which are mutually separated, the substrate on two sides of each first gate structure is provided with source-drain doped areas, the first gate structures are arranged along a first direction, the first conductive layers are mutually separated, the top surfaces of the first conductive layers are positioned on one or more surfaces of the source-drain doped areas and are lower than the top surfaces of the first conductive layers, and the top surfaces of the first conductive layers are respectively provided with one first plug. The semiconductor structure reduces parasitic resistance and improves electrical properties of the semiconductor structure.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the development of the semiconductor manufacturing industry, there is a corresponding demand for improvement in device performance (e.g., increased processing speed, memory capacity, etc.), extension of battery life, and reduction in manufacturing costs. In order to meet the above requirements, the semiconductor industry is continually striving to reduce the size of semiconductor devices so that modern integrated circuits may include tens or hundreds of thousands or millions of semiconductor structures on a single semiconductor chip.
Typically, semiconductor structures have conductive lines and conductive plugs therein for making electrical connections to front-end-of-line (FEOL) process components and back-end-of-line (BEOL) process components to perform functions.
However, as semiconductor device dimensions continue to shrink, smaller sized conductive layers and first plugs tend to increase parasitic resistance, resulting in reduced performance of the formed semiconductor structure.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to reduce parasitic resistance and improve electrical performance of the semiconductor structure.
In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate, a plurality of first conductive layers, a plurality of first plugs, a plurality of first conductive structures, and a plurality of first conductive structures, wherein the first gate structures are separated from each other, the first gate structures are arranged on the surface of the substrate on two sides of each first gate structure, the first conductive layers are separated from each other along a first direction, the top surface of each first conductive layer is lower than the top surface of each first conductive layer, the first plugs are respectively arranged on the top surface of each first conductive layer, and the conductive structures are connected with the first plugs.
The semiconductor device comprises a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer and a third dielectric layer, wherein the first dielectric layer is positioned on the surface of a substrate, the surface of a source-drain doped region, the top surface and the side wall surface of a first grid structure, and the side wall surface of a first conductive layer, the second dielectric layer is positioned on the surface of the first dielectric layer, the top surface of the second dielectric layer is flush with the top surface of a first plug, the third dielectric layer is positioned on the surface of the second dielectric layer, the second conductive layers are positioned on the top surfaces of a plurality of first plugs, and the top surface of the third dielectric layer is flush with the top surface of the second conductive layer.
Optionally, the conductive structure is in contact with a plurality of first plug sidewall surfaces, and the conductive structure extends along a first direction.
Optionally, the top surface of the conductive structure is flush with the top surface of the second dielectric layer.
Optionally, the first conductive layer comprises a first end and a second end, and the first plugs are respectively positioned on the top surface of the first end of each first conductive layer.
Optionally, the conductive structure comprises a plurality of parallel first plugs and a parallel second conductive layer, wherein the parallel first plugs are respectively positioned on the top surfaces of the second ends of the first conductive layers, and the parallel second conductive layer is positioned on the top surfaces of the parallel first plugs.
Optionally, the conductive structure further comprises a plurality of parallel second plugs and a parallel third conductive layer, wherein the parallel second plugs are respectively positioned on the top surfaces of the second conductive layers and the top surfaces of the parallel second conductive layers, and the parallel third conductive layer is positioned on the surfaces of the parallel second plugs.
Optionally, the substrate further comprises an effective area adjacent to the ineffective area, the surface of the effective area is provided with mutually separated second grid structures, the plurality of second grid structures are arranged along the first direction, the source-drain doped areas are further located in the substrate at two sides of each second grid structure, and each first conductive layer is further located on one or more surfaces of the source-drain doped areas of the effective area.
Optionally, when the active region is located at two sides of the inactive region, the conductive structure is located above the second gate structure.
Optionally, the second conductive layer is electrically connected to an external voltage.
Correspondingly, the technical scheme of the invention also provides a method for forming any semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises an invalid region, a plurality of first grid structures which are separated from each other are arranged on the surface of the invalid region, source and drain doped regions are arranged in the substrate on two sides of each first grid structure, the plurality of first grid structures are arranged along a first direction, a plurality of first conductive layers which are separated from each other are formed on the surface of each source and drain doped region, one or more first conductive layers are arranged on the surface of one or more source and drain doped regions, the plurality of first conductive layers and the plurality of first grid structures are arranged alternately, a plurality of first plugs are formed on the top surface of the first conductive layer lower than the top surface of the first conductive layer, a first conductive structure is formed on the top surface of each first conductive layer, a conductive structure which is electrically connected with the plurality of first conductive layers is formed, and the conductive structure is electrically isolated from the first grid structure.
Optionally, the method further comprises the steps of forming a first grid electrode structure and a source-drain doping region, forming a first dielectric layer on the surface of the substrate before forming a first plug, wherein the first dielectric layer is located on the surface of the source-drain doping region, the top surface of the first grid electrode structure and the surface of the side wall, forming a plurality of first conductive layers in the first dielectric layer, forming a second dielectric layer on the surfaces of the first dielectric layer and the first conductive layer after forming the first conductive layers, wherein the top surface of the second dielectric layer is flush with the top surface of the first plug, forming a third dielectric layer on the surface of the second dielectric layer, and the third dielectric layer is provided with a second conductive layer located on the top surface of the plurality of first plugs, and the top surface of the third dielectric layer is flush with the top surface of the second conductive layer.
Optionally, in forming the first plug, the conductive structure is formed and contacts a surface of a sidewall of the first plug, and the conductive structure extends along a first direction.
Optionally, the forming method of the conductive structure and the first plug comprises the steps of forming a first mask layer on the surface of a second dielectric layer before forming a third dielectric layer, etching the second dielectric layer by taking the first mask layer as a mask until the top surfaces of a plurality of first conductive layers are exposed, forming a first opening and a second opening in the second dielectric layer, wherein the first opening exposes the top surfaces of the first conductive layers, the second opening is located between adjacent first openings and is connected with the second opening, forming a first plug in the first opening, and forming a conductive structure in the second opening.
Optionally, the first conductive layer comprises a first end and a second end, the first plugs are respectively located on the top surface of the first end of the first conductive layer, the forming process of the conductive structure comprises the steps of forming parallel first plugs in the second dielectric layer after forming the second dielectric layer and before forming the third dielectric layer, the parallel first plugs are respectively located on the top surface of the second end of the first conductive layer, forming a third dielectric layer on the top surface of the second dielectric layer and the parallel first plug after forming the parallel first plugs, and forming parallel second conductive layers in the third dielectric layer, wherein the parallel second conductive layers are located on the top surfaces of the parallel first plugs.
Optionally, the parallel first plugs are formed in the process of forming the first plugs, and the parallel second conductive layers are formed in the process of forming the second conductive layers.
Optionally, the forming process of the conductive structure further comprises the steps of forming a fourth dielectric layer on the surface of the second conductive layer and the surface of the third dielectric layer after forming the parallel second conductive layer, forming a plurality of parallel second plugs in the fourth dielectric layer, wherein the parallel second plugs are respectively positioned on the top surface of the second conductive layer and the top surface of the parallel second conductive layer, forming a fifth dielectric layer on the surface of the fourth dielectric layer and the surface of the parallel second plugs, forming a parallel third conductive layer in the fifth dielectric layer, and the parallel third conductive layer is positioned on the plurality of parallel second plugs.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the semiconductor structure provided by the technical scheme of the invention, the plurality of first conductive layers are electrically connected by the conductive structure, so that a plurality of conductive paths extending in parallel can be formed between the second conductive layers and the first conductive layers. When the second conductive layer is electrically connected to an external voltage, the number of conductive paths can increase the cross-sectional area (as compared to a single conductive path) for the transfer of current from the second conductive layer to the devices within the inactive region, thereby facilitating a reduction in parasitic resistance. Meanwhile, the conductive structure is electrically isolated from the first gate structure, so that the first gate structure can be prevented from being electrically connected with the second conductive layer through the conductive structure, and short circuit of the first gate structure is avoided. In conclusion, the semiconductor structure can reduce parasitic resistance and has higher electrical performance.
Further, when the effective area is located at two sides of the ineffective area, the conductive structure is located above the second gate structure, so that when the conductive structure electrically connects the first conductive layers on the surfaces of the ineffective areas at two sides of the effective area, that is, parasitic resistance can be reduced, the second gate structure in the effective area is not affected, short circuit of the second gate structure in the effective area is avoided, and electrical performance is further improved.
Drawings
FIGS. 1 and 2 are schematic diagrams of a semiconductor structure;
fig. 3 to 9 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 10 to 16 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to another embodiment of the present invention;
Fig. 17 to 19 are schematic structural views of a semiconductor structure in a further embodiment of the present invention.
Detailed Description
As described in the background, the performance of existing semiconductor structures is poor.
The following describes the reason why the performance of the semiconductor structure is poor with reference to the drawings, and fig. 1 and 2 are schematic structural views of a semiconductor structure.
Referring to fig. 1 and 2, fig. 1 is a top view of fig. 2 along the direction F, fig. 1 is a schematic view with conductive layers omitted, fig. 2 is a schematic view with cross-section structure along the tangential direction A-A1 of fig. 1, including a substrate 100, the substrate 100 including adjacent inactive areas I and active areas II, the inactive areas I having first and second gate structures 111 and 112 separated from each other on the surface of the active areas I, the active areas II having third gate structures 113 separated from each other on the surface of the substrate 100, first and second conductive layers 121 and 122 and a third conductive layer 123 separated from each other on the surface of the substrate 100, the first gate structure 111 being located between the first and second conductive layers 121 and 122, the second gate structure 112 being located between the second and third conductive layers 122 and 123, a first plug 131 located on the top surface of the first conductive layer 121, a second plug 132 located on the top surface of the second conductive layer 122, a third plug 132 located on the top surface of the third conductive layer 123, a first plug 131 located on the top surface of the third conductive layer 121, a third plug 132 located on the top surface of the third conductive layer 122, and a third gate structure located on the top surface 133 located on the top surface of the third conductive layer 122 and a top surface of the third conductive layer 122 located on the top surface of the third conductive layer 122.
In the above semiconductor structure, due to the requirement of circuit connection, the first plug 131, the second plug 132 and the third plug 133 are generally electrically connected to the first voltage through the conductive layer 150, so that the first gate structure 111 and the source-drain doped regions (not shown) in the substrate 100 on both sides of the first gate structure 111 form an inactive device, and the second gate structure 112 and the source-drain doped regions (not shown) in the substrate 100 on both sides of the second gate structure 112 also form an inactive device. Since the conductive structure 140 is electrically connected to the first conductive layer 121, the second conductive layer 122 and the third conductive layer 123, the conductive layer 150 and the second conductive layer 122, or the conductive layer 150 and the third conductive layer 123 form a first conductive path, a second conductive path and a third conductive path extending in parallel. The parallel first and second and third conductive paths increase the cross-sectional area (as compared to a single conductive path) for current to travel from conductive layer 150 to the active device formed by third gate structure 113, thereby reducing the parasitic resistance of the active device formed by third gate structure 113.
However, the conductive structure 140 is located not only on the top surface of the first conductive layer 121, the top surface of the second conductive layer 122, and the top surface of the third conductive layer 123, but also on the top surfaces of the first gate structure 111 and the second gate structure 112. Further, the first gate structure 111 is electrically connected to the conductive layer 150, and the second gate structure 112 is electrically connected to the conductive layer 150, so that a voltage is applied to the first gate structure 111 and the second gate structure 112, which is easy to adversely affect the first gate structure 111 and the second gate structure 112. For example, when different voltages are simultaneously applied to the first gate structure 111 or the second gate structure 112, the first gate structure 111 or the second gate structure 112 is caused to be shorted, so that the performance of the formed semiconductor structure is degraded.
In order to solve the technical problems, the embodiment of the method provides a semiconductor structure, which comprises a substrate, a plurality of first conductive layers, a plurality of first plugs, a plurality of first conductive structures, a plurality of first conductive layers, a plurality of first plugs, a plurality of conductive structures connected with the first plugs and electrically isolated from the first gate structures, wherein the substrate comprises an inactive area, the surface of the inactive area is provided with the plurality of first gate structures which are separated from each other, the substrate on two sides of each first gate structure is provided with the source-drain doped area, the plurality of first conductive layers which are separated from each other are arranged along a first direction, the top surface of each first conductive layer is lower than the top surface of the first conductive layer, and the first plugs are respectively arranged on the top surface of each first conductive layer. The semiconductor structure reduces parasitic resistance and improves electrical performance.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 9 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate 200 is provided, the substrate 200 includes an inactive area I, the surface of the inactive area I has a plurality of first gate structures 211 separated from each other, the substrate 200 on both sides of each of the first gate structures 211 has source-drain doped regions 201 therein, and the plurality of first gate structures 211 are arranged along a first direction X.
The material of the substrate 200 is a semiconductor material. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator. Wherein the III-V element comprises a multi-component semiconductor material comprising InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In this embodiment, the substrate 200 further includes an active region II adjacent to the inactive region I, the surface of the active region II has second gate structures 212 separated from each other, a plurality of the second gate structures 212 are arranged along the first direction X, and the source-drain doped regions 201 are further located in the substrate 200 at two sides of each of the second gate structures 212.
In this embodiment, the effective area II is located at two sides of the ineffective area I. In other embodiments, the active area is located on one side of the inactive area, or the inactive area is located on both sides of the active area.
A plurality of first conductive layers are formed on the surface of the source-drain doped region, wherein the first conductive layers are formed on the surface of one or more of the source-drain doped regions, the plurality of first conductive layers and the plurality of first gate structures are alternately arranged, the top surface of the first gate structure is lower than the top surface of the first conductive layer, and the process of forming the plurality of first conductive layers is shown in fig. 4 and 5.
Referring to fig. 4, a first dielectric layer 220 is formed on the surface of the substrate 200, where the first dielectric layer 220 is located on the surface of the source/drain doped region 201, the top surface of the first gate structure 211, and the sidewall surface.
The top surface of the first dielectric layer 220 is higher than the top surface of the first gate structure 211.
In this embodiment, the first dielectric layer 220 is further located on the top surface and the sidewall surface of the second gate structure 212, and the top surface of the first dielectric layer 220 is further higher than the top surface of the second gate structure 212.
The first dielectric layer 220 serves to electrically isolate, on the one hand, and to provide support for the subsequent formation of the first conductive layer, on the other hand.
The material of the first dielectric layer 220 includes an oxide, an ultra-low K dielectric material, or a low K dielectric material.
In this embodiment, the material of the first dielectric layer 220 is silicon oxide.
The process of forming the first dielectric layer 220 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 5, a plurality of first conductive layers 221 are formed in the first dielectric layer 220.
The method for forming the first conductive layer 221 includes forming a second mask layer (not shown) on the surface of the first dielectric layer 220, wherein the second mask layer exposes a part of the surface of the first dielectric layer 220, etching the first dielectric layer 220 with the mask of the second mask layer until the surface of the source/drain doped region 201 is exposed, forming a plurality of third openings (not shown) in the first dielectric layer 220, and forming the first conductive layer 221 in the third openings, wherein the top surface of the first conductive layer 221 is flush with the top surface of the first dielectric layer 220.
Specifically, in this embodiment, a plurality of first conductive layers 221 are formed on the surface of the source-drain doped region 201 separately, one first conductive layer 221 is formed on the surface of one source-drain doped region 201, a plurality of first conductive layers 221 and a plurality of first gate structures 211 are arranged alternately, and the top surface of the first gate structures 211 is lower than the top surface of the first conductive layers 221.
In other embodiments, a plurality of the source-drain doped regions have one of the first conductive layers on a surface thereof.
In this embodiment, the plurality of first conductive layers 221 and the plurality of second gate structures 212 are arranged alternately, and the top surface of the second gate structures 212 is lower than the top surface of the first conductive layers 221.
Referring to fig. 6, a second dielectric layer 230 is formed on the surface of the first dielectric layer 220 and the first conductive layer 221.
The second dielectric layer 230 serves, on the one hand, to electrically isolate and, on the other hand, to provide support for the subsequent formation of the first plugs and conductive structures.
The material of the second dielectric layer 230 includes an oxide, an ultra-low K dielectric material, or a low K dielectric material.
In this embodiment, the material of the second dielectric layer 230 is silicon oxide.
The process of forming the second dielectric layer 230 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 7, after the second dielectric layer 230 is formed, a plurality of first plugs 231 are formed on the top surface of the first conductive layer 221, and a portion of the top surface of each of the first conductive layers 221 has the first plugs 231.
Specifically, the first plug 231 is formed in the second dielectric layer of the inactive area I, and the top surface of the first plug 231 is flush with the top surface of the second dielectric layer 230.
With continued reference to fig. 7, forming a conductive structure 232 electrically connecting the plurality of first conductive layers 221 and electrically isolating the conductive structure 232 from the first gate structure 211 is also included.
In this embodiment, during the formation of the first plug 231, the conductive structure 232 is formed, the conductive structure 232 contacts the sidewall surface of the first plug 231, and the conductive structure 232 extends along the first direction X.
The method for forming the conductive structures 232 and the first plugs 231 includes forming a first mask layer (not shown) on the surface of the second dielectric layer 230, wherein the first mask layer exposes a part of the surface of the second dielectric layer 230, etching the second dielectric layer 230 by using the first mask layer as a mask until the top surfaces of the first conductive layers 221 are exposed, forming a first opening (not shown) and a second opening (not shown) in the second dielectric layer 230, wherein the first opening exposes the top surfaces of the first conductive layers 221, the second opening is located between adjacent first openings and is connected with the first opening, forming the first plugs 231 in the first opening, and forming the conductive structures 232 in the second opening.
Since the first opening and the second opening are connected, the first plug 231 formed in the first opening is connected to the conductive structure 232 formed in the second opening, and thus the first plug 231 and the conductive structure 232 are electrically connected. And, since the first plugs 231 are electrically connected to the plurality of first conductive layers 221, the conductive structures 232 can electrically connect the plurality of first conductive layers 221, so that a plurality of conductive paths extending in parallel can be formed between the second conductive layers and the first conductive layers 221, which are formed later.
Referring to fig. 8 and 9, fig. 9 is a top view of fig. 8 along the X direction, fig. 8 is a schematic cross-sectional view of fig. 9 along the tangential line A-A1, and fig. 9 is a schematic view in which the first dielectric layer 220, the second dielectric layer 230, and the third dielectric layer 240 are omitted, the conductive structure 232 is formed on the surface of the second dielectric layer 230, the third dielectric layer 240 has the second conductive layer 241 located on the top surfaces of the first plugs 231, and the top surfaces of the third dielectric layer 240 are flush with the top surfaces of the second conductive layer 241.
The method for forming the second conductive layer 241 includes forming a third mask layer (not shown) on the surface of the third dielectric layer 240, where the third mask layer exposes a portion of the surface of the third dielectric layer 240, etching the third dielectric layer 240 with the third mask layer as a mask until the surface of the first plug 231 and the surface of the conductive structure 232 are exposed, forming a fourth opening (not shown) in the third dielectric layer 240, forming the second conductive layer 241 in the fourth opening, and making the top surface of the second conductive layer 241 flush with the top surface of the third dielectric layer 240.
In this embodiment, the second conductive layer 241 is connected to an external voltage, and the second conductive layer 241 is located on the top surfaces of the first plugs 231. In other embodiments, the external voltage may be further connected through an nth conductive layer, and the nth conductive layer is electrically connected to the plurality of first plugs, where N is a natural number greater than 2.
Since the first plugs 231 and the conductive structures 232 are electrically connected, and the first plugs 231 and the plurality of first conductive layers 221 are electrically connected, the conductive structures 232 are able to electrically connect the plurality of first conductive layers 221. The conductive structure 232 is in turn capable of electrically connecting the plurality of first conductive layers 221 such that a plurality of conductive paths extending in parallel can be formed between the second conductive layer 241 and the first conductive layer 231. When the second conductive layer 241 is electrically connected to an external voltage, several conductive paths can increase the cross-sectional area (as compared to a single conductive path) for the transfer of current from the second conductive layer 241 to devices within the inactive region I, thereby facilitating a reduction in parasitic resistance. At the same time, the conductive structure 232 is electrically isolated from the first gate structure 211, so that it is possible to avoid the first gate structure 211 from being electrically connected to the second conductive layer 241 through the conductive structure 232, resulting in a short circuit of the first gate structure 211. In conclusion, the semiconductor structure can reduce parasitic resistance and has higher electrical performance.
In other embodiments, when the inactive area is located at two sides of the active area, the conductive structure may also be located above the second gate structure, so that when the conductive structure electrically connects the first conductive layers on the surfaces of the inactive area at two sides of the active area, that is, parasitic resistance can be reduced, and meanwhile, the second gate structure in the active area is not affected, thereby avoiding the second gate structure in the active area from being shorted, and further improving electrical performance.
Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above forming method, and please continue to refer to fig. 8 and 9, which includes a substrate 200, wherein the substrate 200 includes an inactive area I, the inactive area I includes a plurality of first gate structures 211 separated from each other, source/drain doped regions 201 are disposed in the substrate 200 at two sides of each of the first gate structures 211, the plurality of first gate structures 211 are aligned along a first direction X, a plurality of first conductive layers 221 separated from each other, each of the first conductive layers 221 is located on one or more surfaces of the source/drain doped regions 201, and a top surface of the first gate structures 211 is lower than a top surface of the first conductive layers 221, a plurality of first plugs 231, and a portion of a top surface of each of the first conductive layers 221 includes a first plug 231, a conductive structure 232 connected to the plurality of first plugs 231, and the conductive structure 232 is electrically isolated from the first gate structures 211.
In this embodiment, the conductive structures 232 are in contact with the sidewall surfaces of the first plugs 231, and the conductive structures 232 extend along the first direction X.
The following detailed description refers to the accompanying drawings.
The substrate further comprises an effective region II adjacent to the ineffective region I, wherein the surface of the effective region II is provided with mutually separated second gate structures 212, a plurality of second gate structures 212 are arranged along a first direction X, the source-drain doped regions 201 are further positioned in the substrate 200 at two sides of each second gate structure 212, and each first conductive layer 221 is further positioned on one or more surfaces of the source-drain doped regions 201 of the effective region II.
In this embodiment, each of the first conductive layers 221 is located on a surface of one of the source-drain doped regions 201 of the inactive region I, and each of the first conductive layers 221 is also located on a surface of one of the source-drain doped regions 201 of the active region I.
In this embodiment, the active area is located at two sides of the inactive area. In other embodiments, the active area is located on one side of the inactive area, or the inactive area is located on both sides of the active area.
In other embodiments, the conductive structure is also located over the second gate structure when the active region is located on both sides of the inactive region.
The semiconductor structure further comprises a first dielectric layer 220 positioned on the surface of the substrate 200, wherein the first dielectric layer 220 is positioned on the surface of the source-drain doped region 201, the top surface and the side wall surface of the first gate structure 211 and the side wall surface of the first conductive layer 221, a second dielectric layer 230 positioned on the surface of the first dielectric layer 220, the top surface of the second dielectric layer 230 is flush with the top surface of the first plug 231, a third dielectric layer 240 positioned on the surface of the second dielectric layer 230, the third dielectric layer 240 is internally provided with a second conductive layer 241 positioned on the top surfaces of the first plugs 231, and the top surface of the third dielectric layer 240 is flush with the top surface of the second conductive layer 241.
The top surface of the conductive structure 232 is flush with the top surface of the second dielectric layer 230.
In this embodiment, the semiconductor structure is electrically connected to an external voltage through the second conductive layer 241.
Since the conductive structures 232 electrically connect the plurality of first conductive layers 221, a plurality of conductive paths extending in parallel can be formed between the second conductive layers 241 and the first conductive layers 221. When the second conductive layer 241 is electrically connected to an external voltage, several conductive paths can increase the cross-sectional area (as compared to a single conductive path) for the transfer of current from the second conductive layer 241 to devices within the inactive region I, thereby facilitating a reduction in parasitic resistance. At the same time, the conductive structure 232 is electrically isolated from the first gate structure 211, so that it is possible to avoid the first gate structure 211 from being electrically connected to the second conductive layer 241 through the conductive structure 232, resulting in a short circuit of the first gate structure 211. In conclusion, the semiconductor structure can reduce parasitic resistance and has higher electrical performance.
Fig. 10 to 16 are schematic structural views illustrating steps of a semiconductor structure forming method according to another embodiment of the present invention. The present embodiment is different from the above embodiment in the method and structure of forming the conductive structure, and therefore the present embodiment continues the description of the process of forming the semiconductor structure on the basis of the above embodiment.
It should be noted that the first conductive layer 221 includes a first end 2211 and a second end 2212.
With continued reference to fig. 10 to 12 on the basis of fig. 6, fig. 10 is a schematic cross-sectional view of fig. 12 along a tangential line A-A1, fig. 11 is a schematic cross-sectional view of fig. 12 along a tangential line A2-A3, fig. 12 is a top view of fig. 10 along a direction F, and fig. 12 is a schematic view in which the first dielectric layer 220 and the second dielectric layer 230 are omitted, after the second dielectric layer 230 is formed, a plurality of first plugs 331 are formed in the second dielectric layer 230, and a portion of the top surface of each of the first conductive layers 221 has a first plug 331.
In this embodiment, the first plugs 331 are respectively located on the top surfaces of the first ends 2211 of the first conductive layers 221 on the inactive area I.
With continued reference to fig. 10 to 12, parallel first plugs 332 are formed in the second dielectric layer 230, and the parallel first plugs 332 are respectively located on top surfaces of the second ends 2212 of the first conductive layers 221.
In this embodiment, the parallel first plugs 332 are respectively located on the top surfaces of the first ends 2212 of the first conductive layers 221 on the inactive area I.
In this embodiment, the parallel first plugs 332 are formed during the process of forming the first plugs 331.
The method for forming the first plugs 331 and parallel first plugs 332 includes forming a fourth mask layer (not shown) on the surface of the second dielectric layer 230 and the surface of the first conductive layer 221, the fourth mask layer exposing a portion of the surface of the second dielectric layer 230, etching the second dielectric layer 230 until the surface of the first conductive layer 221 is exposed, forming a fifth opening (not shown) and a sixth opening (not shown) in the second dielectric layer 230, wherein the bottom of the fifth opening exposes the surface of the first end 2211, the bottom of the sixth opening exposes the surface of the second end 2212, forming a first plug 331 in the fifth opening, forming parallel first plugs 332 in the sixth opening, and the top surface of the first plug 331 and the top surface of the parallel first plug 332 are flush with the surface of the second dielectric layer 230.
Referring to fig. 13, fig. 13 is a schematic diagram of fig. 10, in which a third dielectric layer 340 is formed on the surface of the second dielectric layer 230 and parallel to the surface of the first plug 332.
In this embodiment, after forming the first plugs 331 and parallel first plugs 332, the third dielectric layer 340 is formed on the surface of the second dielectric layer 230 and the surfaces of the first plugs 331 and parallel first plugs 332.
The material and the forming process of the third dielectric layer 340 are the same as those of the third dielectric layer 240 in the above embodiment, and will not be described herein.
Referring to fig. 14 to 16, fig. 14 is a schematic cross-sectional view along A-A1 tangential direction of fig. 16, fig. 15 is a schematic cross-sectional view along A2-A3 tangential direction of fig. 16, fig. 16 is a top view along F direction of fig. 14, fig. 16 is a schematic view in which the first dielectric layer 220, the second dielectric layer 230 and the third dielectric layer 340 are omitted, a second conductive layer 341 is formed in the third dielectric layer 340, and the second conductive layer 341 is located on top surfaces of the first plugs 331.
In this embodiment, an external voltage is connected through the second conductive layer 341.
With continued reference to fig. 14 to 16, a parallel second conductive layer 342 is formed in the third dielectric layer 340, and the parallel second conductive layer 342 is located on top surfaces of the parallel first plugs 332.
In this embodiment, the parallel second conductive layer 342 is formed during the process of forming the second conductive layer 341.
The parallel first plugs 332 and parallel second conductive layers 342 form conductive structures 345.
The conductive structure 345 includes parallel first plugs 332 and parallel second conductive layers 342, the parallel first plugs 332 being located at the second ends 2212 of each first conductive layer 221, and the parallel second conductive layers 242 electrically connecting the plurality of parallel first plugs 332 such that the conductive structure 345 is capable of electrically connecting the plurality of first conductive layers 221.
The conductive structure 335 electrically connects the plurality of first conductive layers 221 such that a plurality of conductive paths extending in parallel can be formed between the second conductive layer 341 and the first conductive layer 231. When the second conductive layer 341 is electrically connected to an external voltage, several conductive paths can increase the cross-sectional area (compared to a single conductive path) for the transfer of current from the second conductive layer 341 to devices within the inactive region I, thereby facilitating a reduction in parasitic resistance. At the same time, the conductive structure 335 is electrically isolated from the first gate structure 211, so that it can be avoided that the first gate structure 211 is electrically connected to the second conductive layer 241 through the conductive structure 335, resulting in a short circuit of the first gate structure 211. In conclusion, the semiconductor structure can reduce parasitic resistance and has higher electrical performance.
In other embodiments, the forming process of the conductive structure further comprises forming a fourth dielectric layer on the surface of the second conductive layer and the surface of the third dielectric layer after forming the parallel second conductive layer, forming a plurality of parallel second plugs in the fourth dielectric layer, wherein the parallel second plugs are respectively positioned on the top surface of the second conductive layer and the top surface of the parallel second conductive layer, forming a fifth dielectric layer on the surface of the fourth dielectric layer and the surface of the parallel second plugs, forming a parallel third conductive layer in the fifth dielectric layer, and the parallel third conductive layer is positioned on the plurality of parallel second plugs.
Accordingly, the embodiment of the present invention further provides the semiconductor structure formed by the above method, and further provides fig. 14 to 16, which includes a substrate 200, wherein the substrate 200 includes an inactive area I, the inactive area I includes a plurality of first gate structures 211 separated from each other, source and drain doped regions 201 are formed in the substrate 200 at two sides of each of the first gate structures 211, the plurality of first gate structures 211 are aligned along a first direction X, a plurality of first conductive layers 221 separated from each other, each of the first conductive layers 221 is located on one or more surfaces of the source and drain doped regions 201, and a top surface of each of the first gate structures 211 is lower than a top surface of the first conductive layer 221, a plurality of first plugs 231, and a portion of a top surface of each of the first conductive layers 221 is respectively provided with a first plug 331, a conductive structure 345 connected to the plurality of first plugs 331, and the conductive structure 345 is electrically isolated from the first gate structures 211.
In this embodiment, the first conductive layer 221 includes a first end 2211 and a second end 2212, and the plurality of first plugs 331 are respectively located on a top surface of the first end 2211 of each first conductive layer 221.
The conductive structure 345 includes a plurality of parallel first plugs 332 and a parallel second conductive layer 342, the plurality of parallel first plugs 332 being respectively located on top surfaces of the second ends 2212 of the respective first conductive layers 241, the parallel second conductive layer 342 being located on top surfaces of the plurality of parallel first plugs 332.
The following detailed description refers to the accompanying drawings.
The substrate 200 further comprises an active region II adjacent to the inactive region I, wherein the surface of the active region II is provided with mutually separated second gate structures 212, a plurality of the second gate structures 212 are arranged along the first direction X, the source-drain doped regions 201 are further positioned in the substrate 200 at two sides of each second gate structure 212, and each first conductive layer 221 is further positioned on one or more surfaces of the source-drain doped regions 201 of the active region II.
The semiconductor structure further comprises a first dielectric layer 220 positioned on the surface of the substrate 200, wherein the first dielectric layer 220 is positioned on the surface of the source-drain doped region 201, the top surface and the side wall surface of the first gate structure 211 and the side wall surface of the first conductive layer 221, a second dielectric layer 230 positioned on the surface of the first dielectric layer 220, the top surface of the second dielectric layer 230 is flush with the top surface of the first plug 331, a third dielectric layer 340 positioned on the surface of the second dielectric layer 230, the third dielectric layer 340 is internally provided with a second conductive layer 341 positioned on the top surfaces of the first plugs 231, and the top surface of the third dielectric layer 340 is flush with the top surface of the second conductive layer 341.
In this embodiment, the parallel first plugs 332 are located in the second dielectric layer 230, and the top surfaces of the parallel first plugs 332 are flush with the surface of the second dielectric layer 230, the parallel second conductive layers 342 are located in the third dielectric layer 340, and the top surfaces of the parallel second conductive layers 342 are flush with the surface of the third dielectric layer 340.
In this embodiment, the semiconductor structure is electrically connected to an external voltage through the second conductive layer 241.
The conductive structure 345 includes parallel first plugs 332 and parallel second conductive layers 342, the parallel first plugs 332 being located at the second ends 2212 of each first conductive layer 221, and the parallel second conductive layers 242 electrically connecting the plurality of parallel first plugs 332 such that the conductive structure 345 is capable of electrically connecting the plurality of first conductive layers 221.
Since the conductive structures 345 electrically connect the plurality of first conductive layers 221, a plurality of conductive paths extending in parallel can be formed between the second conductive layers 341 and the first conductive layers 221. When the second conductive layer 341 is electrically connected to an external voltage, several conductive paths can increase the cross-sectional area (compared to a single conductive path) for the transfer of current from the second conductive layer 341 to devices within the inactive region I, thereby facilitating a reduction in parasitic resistance. At the same time, the conductive structure 345 is electrically isolated from the first gate structure 211, so that it is possible to avoid that the first gate structure 211 is electrically connected to the second conductive layer 341 through the conductive structure 345, resulting in a short circuit of the first gate structure 211. In conclusion, the semiconductor structure can reduce parasitic resistance and has higher electrical performance.
Fig. 17 to 19 are schematic structural views of a semiconductor structure in a further embodiment of the present invention.
Referring to fig. 17 to 19, fig. 17 is a schematic cross-sectional view taken along A-A1 tangential direction of fig. 19, fig. 18 is a schematic cross-sectional view taken along A2-A3 tangential direction of fig. 19, fig. 19 is a top view taken along F direction of fig. 17, and fig. 19 is a schematic view taken with the omission of a first dielectric layer and a second dielectric layer, a third dielectric layer, a fourth dielectric layer, and a fifth dielectric layer, the semiconductor structure includes a substrate 200, the substrate 200 includes an inactive area I, the surface of the inactive area I has a plurality of first gate structures 211 separated from each other, the substrate 200 on both sides of each first gate structure 211 has source-drain doped regions 201 therein, the plurality of first gate structures 211 are arranged along a first direction X, the plurality of first conductive layers 221 separated from each other are located on one or more surfaces of the source-drain doped regions 201, and the top surfaces of the first gate structures 211 are lower than the top surfaces of the first conductive layers 221, the plurality of first plugs 231, and the top surfaces of the first conductive layers 331 are electrically isolated from the first gate structures 445, respectively, and the first conductive structures 331 are electrically isolated from the first gate structures 211.
In this embodiment, the first conductive layer 221 includes a first end (not shown) and a second end 2212 (not shown), and the plurality of first plugs 331 are respectively located on top surfaces of the first ends 2211 of the first conductive layers 221.
The conductive structure 445 includes a plurality of parallel first plugs 332 and parallel second conductive layers 342, the plurality of parallel first plugs 332 being respectively located on top surfaces of the second ends 2212 of the respective first conductive layers 241, the parallel second conductive layers 342 being located on top surfaces of the plurality of parallel first plugs 332, a plurality of parallel second plugs 452 and a parallel third conductive layer 462, the plurality of parallel second plugs 452 being respectively located on top surfaces of the second conductive layers 341 and on top 342 surfaces of the parallel second conductive layers, the parallel third conductive layers 462 being located on surfaces of the plurality of parallel second plugs 452.
The conductive structure 445 may electrically connect not only the second conductive layer 341 through the parallel first plugs 332 and the parallel second conductive layer 342, but also the second conductive layer 341 through the parallel second plugs 452 and the parallel third conductive layer 462, so that the number of conductive paths extending in parallel between the second conductive layer 341 and the first conductive layer 331 can be further increased. The greater the number of conductive paths between the second conductive layer and the first conductive layer 221, the more advantageous is to increase the cross-sectional area (as compared to a single conductive path) for the transfer of current from the second conductive layer 341 to the devices within the inactive region I, thereby further facilitating a reduction in parasitic resistance.
The following detailed description refers to the accompanying drawings.
The substrate 200 further comprises an active region II adjacent to the inactive region I, wherein the surface of the active region II is provided with mutually separated second gate structures 212, a plurality of the second gate structures 212 are arranged along the first direction X, the source-drain doped regions 201 are further positioned in the substrate 200 at two sides of each second gate structure 212, and each first conductive layer 221 is further positioned on one or more surfaces of the source-drain doped regions 201 of the active region II.
The semiconductor structure further comprises a first dielectric layer 220 positioned on the surface of the substrate 200, wherein the first dielectric layer 220 is positioned on the surface of the source-drain doped region 201, the top surface and the side wall surface of the first gate structure 211 and the side wall surface of the first conductive layer 221, a second dielectric layer 230 positioned on the surface of the first dielectric layer 220 and the top surface of the second dielectric layer 230 is flush with the top surface of the first plug 331, a third dielectric layer 340 positioned on the surface of the second dielectric layer 230, a second conductive layer 341 positioned on the top surface of the first plugs 231 and the top surface of the third dielectric layer 340 is flush with the top surface of the second conductive layer 341, a fourth dielectric layer 450 positioned on the surface of the third dielectric layer and the top surface of the fourth dielectric layer 450 is flush with the top surface of the parallel second plugs 152, a fifth dielectric layer 460 positioned on the surface of the fourth dielectric layer 450 and the top surface of the fifth dielectric layer 460 is flush with the top surface of the parallel third conductive layer 462, and the top surface of the sixth dielectric layer 460 is flush with the top surface of the parallel third conductive layer 341.
In this embodiment, the semiconductor structure is electrically connected to an external voltage through the second conductive layer 241.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
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