CN112698321B - Digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment - Google Patents
Digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment Download PDFInfo
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Abstract
The invention relates to a digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment, which comprises the following steps: s1, carrying out staggered repetition frequency processing on the DSP and the FPGA by using a single pulse signal, and solving the speed blur of a high-speed moving target to obtain the real speed of the target; s2, calculating Doppler frequency to be compensated by the DSP; s3, calculating a phase increment in real time by the DSP; s4, transmitting the updated phase increment to an internal RAM of the FPGA through an external memory interface of the DSP; s5, the FPGA finishes mark reading and updating phase increment according to the signal processing of the current frame; s6, calling a DDS IP core in the FPGA to synthesize a signal with required frequency; and S7, the echo signal after Doppler compensation is mixed with a signal generated by the DDS IP core by the FPGA, and filtering processing is carried out to obtain a low-frequency baseband signal after digital down-conversion and Doppler compensation. The invention has the advantages of small calculated amount, easy realization of equipment, strong real-time property and easy maintenance and expansion.
Description
Technical Field
The invention relates to a digital down-conversion and Doppler compensation method, in particular to a digital down-conversion and Doppler compensation method for realizing adjustable phase increment by utilizing DSP and FPGA for cooperative processing, which can be applied to the field of radar signal processing in the aerospace field.
Background
As a key technology of intermediate frequency signal processing, digital down conversion can reduce the rate of a sampled signal while preserving the characteristics of the original signal. In order to solve the contradiction between the radar resolution and the action distance, the intermediate frequency signal needs to be subjected to pulse compression after being subjected to digital down-conversion. The bi-phase encoded signal has good autocorrelation properties but is sensitive to the doppler frequency of moving objects. When the target moving speed is high, the pulse compression effect is rapidly deteriorated, so that the effective compensation of the Doppler frequency shift has important significance for processing the two-phase encoding radar signals. With the development of the intermediate frequency signal processing technology and the improvement of the performance of the programmable hardware FPGA, the demand for quickly realizing the digital down conversion and the doppler compensation is increasingly urgent.
The input of the digital down-conversion and Doppler compensation processing is an intermediate frequency signal with a high speed, the input data volume is large, and the realization of the intermediate frequency signal is generally based on an FPGA chip. In recent years, with the development of signal processing technology, related researchers have proposed many methods for digital down-conversion and doppler compensation.
In a method and a system for realizing ultra-high-speed digital orthogonal down-conversion and decimation filtering in FPGA (patent application number: 201610227770.9; patent publication number: CN 105915241A), two groups of ADC (analog/digital conversion) data signals and one group of ADC clock signals are subjected to cross-time domain synchronization processing, and the two groups of synchronized ADC data signals are respectively multiplied by four paths of digital local oscillation signals output by a local numerically-controlled oscillator through four multipliers to complete the frequency shifting function of a digital domain.
In a patent of a method for realizing random extraction digital down-conversion based on the same FPGA multiplier resource (patent application number: CN201210590839.6; patent publication number: CN 103078592A), a shift register is utilized to change the data sequence, two paths of data with one time of data rate are converted into one path of data with two times of data rate, pre-processing is carried out according to the principle of coefficient symmetry, and a multiplier is multiplexed under the conditions of different extraction rates to realize random extraction digital down-conversion.
In a system and a method for processing high-speed parallel down-conversion FPGA data in vector signal analysis (patent application No. CN201810574092.2; patent publication No. CN 108762154A), multi-path parallel data acquisition is carried out on an input intermediate-frequency signal by means of analog front-end equipment, parallel data is received by the FPGA, and down-conversion of the multi-path high-speed parallel signal is completed by adopting a multi-path parallel cross frequency mixing method.
In the document "design and FPGA implementation of digital down conversion DDC" (published in "chinese integrated circuit", no.1, 2017), various filter designs of digital down conversion are introduced in detail, including a CIC filter, a HB filter, and a FIR filter, and verilog HDL programs are written to implement each module.
In the literature "design and implementation of digital down-conversion and pulse compression system" (published in "radar science and technology", no.2, 2010), digital down-conversion and pulse compression processing of 8K or 2K variable points on an actually acquired intermediate frequency Chirp signal is implemented on a single-chip FPGA.
In literature "research on doppler characteristics and compensation algorithms of two-phase encoded signals" (published in "electronic technology", no.9, 2013), a two-phase encoding doppler compensation method based on MTD is proposed, which performs DFT on data of the same distance unit, performs corresponding phase compensation on signals in each doppler channel of a frequency domain, and performs a pulse pressure modulo operation on each pulse.
As is known from the above patents and documents, no digital down-conversion method is currently available for converting an intermediate frequency signal into a low frequency signal with a varying frequency. The existing doppler compensation method needs to correct each data in the complex matrix, and the calculation amount is large.
Based on the above, the invention provides a digital down-conversion and doppler compensation method based on the adjustable phase increment of the DSP and the FPGA, which realizes the digital down-conversion and doppler compensation of the adjustable increment through the cooperative processing of the DSP and the FPGA, and has strong real-time performance and easy maintenance and expansion of the system.
Disclosure of Invention
The invention aims to provide a digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment, which has the advantages of small calculated amount, easy realization of equipment, strong real-time property and easy maintenance and expansion.
In order to achieve the above object, the present invention provides a digital down-conversion and doppler compensation method based on adjustable phase increment of DSP and FPGA, comprising the following steps:
s1, carrying out staggered repetition frequency processing on the DSP and the FPGA by using a single pulse signal, and solving the speed blur of a high-speed moving target to obtain the real speed of the target;
s2, the DSP calculates Doppler frequency to be compensated according to the real speed of the target, and Doppler compensation is carried out on echo signals reflected by the target after the radar is transmitted;
s3, calculating a phase increment in real time by the DSP;
s4, transmitting the phase increment updated in the S3 to an internal RAM of the FPGA through an external memory interface of the DSP;
s5, reading an updated phase increment from an internal RAM by the FPGA according to the signal processing completion mark of the frame;
s6, calling a DDS IP core in the FPGA, inputting a reference clock and an updated phase increment to the DDS IP core, and synthesizing a signal with required frequency;
s7, the FPGA mixes the echo signal after Doppler compensation with a signal generated by a DDS IP core, moves the echo signal frequency spectrum to a low-frequency baseband position, and carries out filtering processing; and the DSP and the FPGA cooperatively work to obtain the low-frequency baseband signal after digital down-conversion and Doppler compensation in real time.
In S2, according to the real speed of the target, the DSP calculates the compensation Doppler frequency f in real time d Real-time Doppler compensation is carried out on echo signals which are transmitted by a radar and then reflected by a target; the method specifically comprises the following steps:
f d ＝2×v_real/λ
wherein v _ real is the real speed of the target; λ is the wavelength of the echo signal.
In the step S3, according to the output frequency of the DDS IP output signal that needs to be achieved currently, a corresponding frequency control word, that is, a phase increment K, is calculated in real time; the method specifically comprises the following steps:
wherein clk is the reference clock frequency of DDS IP; n is the bit width of the phase data; f out DDS to be achieved for present needsThe output frequency of the IP output signal.
The step S5 specifically includes the following steps:
s51, setting a signal processing completion mark of the frame in the FPGA;
s52, judging whether the signal processing of the frame is finished by the FPGA; if so, the signal processing of the current frame finishes the sign turnover; if not, the signal processing completion flag of the frame is kept unchanged;
and S53, the FPGA selects the phase increment according to the signal processing completion flag of the frame.
In S53, specifically: when the signal processing of the frame is finished and the mark is turned over, the FPGA reads the updated phase increment from the internal RAM and uses the phase increment; and when the signal processing completion mark of the frame is kept unchanged, the FPGA continues to use the current phase increment.
The step S6 specifically includes the following steps:
s61, setting parameters of a system clock, a channel number, a spurious-free dynamic range and a frequency resolution of the DDS IP core;
and S62, inputting a reference clock and an updated phase increment to the DDS IP core, so that the DDS IP core takes the reference clock as a reference, samples the phase at controllable intervals, and synthesizes sine and cosine signals with required frequency.
The step S7 specifically includes the following steps:
s71, mixing: performing ADC discretization sampling on the echo signal subjected to Doppler compensation to obtain an intermediate frequency signal; calling a multiplier, multiplying the intermediate frequency signal by a sine and cosine signal generated by a DDS IP core, and moving the frequency spectrum of the echo signal to a low-frequency baseband position;
s72, filtering: and filtering harmonic components generated in the mixing processing process through an FIR filter to obtain a low-frequency baseband signal containing target information.
In summary, compared with the prior art, the digital down conversion and doppler compensation method based on the adjustable phase increment of the DSP and the FPGA provided by the present invention has the following advantages and beneficial effects:
1. according to the invention, each data in the complex matrix obtained by FPGA processing does not need to be corrected one by one, so that the overall calculation amount is small;
2. the invention calls the DDS IP core in the FPGA, does not need special DDS chips and other devices, has lower requirement on hardware equipment and is easy to realize;
3. the invention realizes real-time variable numerical control frequency synthesis and Doppler compensation by calling DDS IP core and a few multipliers;
4. the invention realizes the combined processing of digital down-conversion and Doppler compensation by adjusting the phase increment, and has flexible operation;
5. the invention does not need to construct a sine signal lookup table through an amplitude/phase conversion circuit, occupies less memory and has wider application range;
6. the invention realizes the quick update of the phase increment by means of the strong computing power of the DSP chip and has strong real-time performance.
Drawings
FIG. 1 is a flow chart of a digital down-conversion and Doppler compensation method based on DSP and FPGA adjustable phase increment in the present invention;
FIG. 2 is a schematic diagram of the connection relationship between the DSP and the FPGA in the present invention;
fig. 3 is a schematic diagram of a call process of a DDS IP core in the present invention.
Detailed Description
The technical contents, construction features, achieved objects and effects of the present invention will be described in detail by preferred embodiments with reference to fig. 1 to 3.
As shown in fig. 1, the digital down-conversion and doppler compensation method based on adjustable phase increment of DSP and FPGA provided by the present invention includes the following steps:
s1, performing staggered repetition frequency processing by using a single pulse signal through a DSP (digital signal processing) and an FPGA (field programmable gate array), and solving the speed ambiguity of a high-speed moving target to obtain the real speed of the target;
s2, the DSP calculates Doppler frequency to be compensated according to the real speed of the target, and Doppler compensation is carried out on echo signals reflected by the target after the radar is transmitted;
s3, calculating a phase increment in real time by the DSP;
s4, transmitting the phase increment updated in the S3 to an internal RAM (random access Memory) of the FPGA through an EMIF (External Memory Interface) of the DSP;
s5, reading an updated phase increment from an internal RAM by the FPGA according to the signal processing completion mark of the frame;
s6, calling a DDS IP core arranged on the FPGA, inputting a reference clock and an updated phase increment to the DDS IP core, and synthesizing a signal with required frequency;
s7, the FPGA carries out frequency mixing on the echo signal after Doppler compensation and a signal generated by a DDS IP core, the echo signal frequency spectrum is moved to a low-frequency baseband position, and filtering processing is carried out; and the DSP and the FPGA cooperatively work to obtain the low-frequency baseband signal after digital down-conversion and Doppler compensation in real time.
In S1, since the doppler frequency of a high-speed moving object tends to exceed a single PRF (pulse repetition frequency), the doppler spectrum is folded in the repetition frequency range, i.e., the speed is blurred. Under the condition, based on the sun theorem, the DSP and the FPGA utilize a single pulse signal to carry out staggered repetition frequency processing, a residual error table look-up method is adopted to solve the speed ambiguity of the high-speed moving target, and the real speed of the target is calculated.
In the embodiment, a target simulator is used for providing 20MHz intermediate frequency signals for a signal processing board where the DSP and the FPGA are located; setting the target speed to be 50m/s; setting the radar frequency to be f =10GHz; the 3 repetition frequencies were set to prf1=387hz, prf2=499hz, prf3=517hz, respectively. According to the method in the S1, the DSP and the FPGA carry out staggered repetition frequency processing by using a single pulse signal, the speed blur of the high-speed moving target is solved by adopting a residual error table look-up method, and the real speed of the target is calculated to be 50m/S.
The two-phase coded signal is sensitive to the Doppler frequency of a moving target, and is more obvious particularly when the target speed is higher. In order to avoid the mismatch between the received signal and the original matched filter, in S2, the doppler compensation is required to be performed on the echo signal. Specifically, the method comprises the following steps:
setting a radar emission signal s (t) as follows:
s(t)＝u(t)exp[j2πf c t]
wherein u (t) is a complex envelope signal; f. of c Is the carrier frequency; t is the current time;
echo signal r of radar emission signal s (t) reflected by target 0 (t) is:
wherein δ is an attenuation factor; f. of d Is the doppler frequency of the target;
is a constant, representing the phase shift produced by the reflection of the target;
for echo signal r 0 (t) performing down-conversion processing to obtain a signal r (t):
wherein, f d Is the doppler frequency of the target; it is apparent that the amplitude of the signal r (t) is doppler frequency modulated.
According to the above, in step S2, the compensation doppler frequency f needs to be calculated in real time according to the real speed of the target by using the fast processing capability of the DSP d The real-time Doppler compensation is carried out on the echo signal which is transmitted by the radar and then reflected by the target, and the real-time Doppler compensation method specifically comprises the following steps:
f d ＝2×v_real/λ
wherein v _ real is the real speed of the target; λ is the wavelength of the echo signal.
In this embodiment, v _ real is 50m/s; λ is 0.03m according to radar frequency f =10GHz; the compensated Doppler frequency f is thus calculated d Is 3333Hz.
When a traditional DDS chip is used for designing a signal generator, the coordination of modules comprising a phase accumulator, a sine ROM amplitude lookup table, a DAC (digital-to-analog converter), an LPF (low-pass filter) and the like is needed, the structure is complex, and the universality of the modules is highAnd (4) poor. With the improvement of the hardware level of the FPGA of the programmable logic device and the continuous development of the direct frequency synthesis technology, a DDS IP core (intellectual property core of a signal generator) has been developed on the FPGA platform. After numerical control frequency synthesis, the output frequency F of the output signal of the DDS IP core out Comprises the following steps:
wherein K is a frequency control word; clk is the reference clock frequency of the DDS IP core; n is the phase data bit width in the phase accumulator.
Thus, for a single channel in the DDS IP core, its frequency control word is:
it can be seen that the output frequency of the DDS IP core depends on the frequency control word. Therefore, in step S3 of the present invention, the advantage of the fast calculation of the DSP can be utilized, based on the compensated Doppler frequency f d And a digital down-conversion frequency f c Updating the output frequency F of the output signal of the desired DDS IP core out And F is out ＝f c +f d And calculates the corresponding frequency control word K, i.e. the phase increment, in real time.
In this embodiment, the reference clock frequency of the DDS IP core is clk =50MHz, the bit width of the phase data in the phase accumulator is N =16, and after the synthesis according to the numerical control frequency, it is desirable to make the output frequency F of the output signal of the DDS IP core equal to F out =20.0033MHz, so the DSP calculates the phase increment as
The DSP has strong EMIF and can access various external memories such as SRAM, ROM and FLASH. Therefore, in S4, the updated phase increment obtained in S3 can be quickly transmitted to the internal RAM of the FPGA by means of the EMIF of the DSP. As shown in fig. 2, taking an FPGA with model JFM4VSX55RT and a DSP with model SMJ320C6415 as examples, to access the internal RAM of the FPGA by the DSP, pins of the DSP required for EMIF communication are butted with corresponding pins of the FPGA.
In this embodiment, the phase of the update can be incremented by EMIF of the DSP
And quickly transmitting to the internal RAM of the FPGA.
The step S5 specifically includes the following steps:
s51, setting a signal processing completion mark of the frame in the FPGA;
s52, judging whether the signal processing of the frame is finished by the FPGA; if so, the signal processing of the current frame finishes the sign turnover; if not, the signal processing completion flag of the frame is kept unchanged;
s53, the FPGA selects a phase increment according to the signal processing completion flag of the frame; when the signal processing of the frame is finished and the mark is turned over, the FPGA reads the phase increment updated by the DSP from the internal RAM and uses the phase increment; when the signal processing completion flag of the present frame remains unchanged (not flipped), the FPGA continues to use the current phase increment (i.e., the FPGA does not read the phase increment updated by the DSP from the internal RAM).
In this embodiment, in S52, the pulse accumulation number is set to m, and a single pulse samples n points. After the FPGA finishes processing m pulses of the current frame, the signal processing of the current frame is considered to be finished, and a signal processing finishing mark of the current frame is turned over; when the FPGA does not finish processing m pulses of the current frame, the signal processing of the current frame is considered to be not finished, and the signal processing finishing mark of the current frame is kept unchanged. In the present invention, only after the signal processing of the present frame is completed, the relevant parameters of the signal processing, including of course the phase increment, can be modified.
In this embodiment, in S53, when the signal processing completion flag of the current frame is turned over, the FPGA reads the phase increment updated by the DSP from the internal RAM
And used.
The step S6 specifically comprises the following steps:
s61, setting parameters such as a system clock, a channel number, a spurious-free dynamic range, a frequency resolution and the like of the DDS IP core; the DDS IP core can carry out numerical control frequency synthesis according to the requirement;
s62, as shown in fig. 3, inputting a reference clock and an updated phase increment to the DDS IP core, so that the DDS IP core takes the reference clock as a reference, performs controllable interval sampling on the phase, and synthesizes a sine and cosine signal with a required frequency.
In this embodiment, the system clock of the DDS IP core is set to 50MHz, the number of channels is 1, the spurious free dynamic range is 91, and the frequency resolution is 461.4258. Inputting a 50MHz reference clock and updated phase increment to a DDS IP core
And taking the reference clock as a reference by the DDS IP core, carrying out controllable interval sampling on the phase, and synthesizing sine and cosine signals with the required frequency of 20.0033 MHz.
The step S7 specifically includes the following steps:
s71, mixing: performing discretization sampling on the echo signal subjected to Doppler compensation by an ADC (analog-to-digital converter) to obtain an intermediate frequency signal; calling a multiplier, multiplying the intermediate frequency signal by a sine and cosine signal generated by a DDS IP core, and moving the frequency spectrum of the echo signal to a low-frequency baseband position required by the DSP;
s72, filtering: and filtering harmonic components generated in the mixing processing process by an FIR (finite impulse response) filter to obtain a low-frequency baseband signal containing target information, and performing downsampling extraction filtering to obtain the low-frequency baseband signal after digital down-conversion and Doppler compensation.
In summary, compared with the prior art, the digital down conversion and doppler compensation method based on the adjustable phase increment of the DSP and the FPGA provided by the present invention has the following advantages and beneficial effects:
1. according to the invention, each data in the complex matrix obtained by FPGA processing does not need to be corrected one by one, so that the overall calculation amount is small;
2. the invention calls the DDS IP core in the FPGA, does not need special DDS chips and other devices, has lower requirement on hardware equipment and is easy to realize;
3. the invention realizes real-time variable numerical control frequency synthesis and Doppler compensation by calling DDS IP core and a few multipliers; the invention occupies less memory in the realization process, and generally only needs 4 BRAMs (embedded block RAMs) of 18 k;
4. the invention realizes the combined processing of digital down-conversion and Doppler compensation by adjusting the phase increment, and has flexible operation;
5. the invention does not need to construct a sine signal lookup table through an amplitude/phase conversion circuit, occupies less internal memory and has wider application range;
6. the invention realizes the quick update of the phase increment by means of the strong computing power of the DSP chip and has strong real-time performance.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (5)
1. A digital down-conversion and Doppler compensation method based on adjustable phase increment of DSP and FPGA is characterized by comprising the following steps:
s1, carrying out stagger repetition frequency processing on a DSP and an FPGA by using a single pulse signal, and solving the speed blur of a high-speed moving target to obtain the real speed of the target;
s2, the DSP calculates Doppler frequency to be compensated according to the real speed of the target, and Doppler compensation is carried out on echo signals reflected by the target after the radar is transmitted;
s3, calculating a phase increment in real time by the DSP;
s4, transmitting the phase increment updated in the S3 to an internal RAM of the FPGA through an external memory interface of the DSP;
s5, reading an updated phase increment from an internal RAM by the FPGA according to the signal processing completion mark of the frame;
s6, calling a DDS IP core in the FPGA, inputting a reference clock and an updated phase increment to the DDS IP core, and synthesizing a signal with required frequency;
s7, the FPGA carries out frequency mixing on the echo signal after Doppler compensation and a signal generated by a DDS IP core, the echo signal frequency spectrum is moved to a low-frequency baseband position, and filtering processing is carried out; the DSP and the FPGA work cooperatively to obtain a low-frequency baseband signal after digital down-conversion and Doppler compensation in real time;
in the step S3, according to the output frequency of the DDS IP output signal that needs to be achieved currently, a corresponding frequency control word, that is, a phase increment K, is calculated in real time; the method comprises the following specific steps:
wherein clk is the reference clock frequency of DDS IP; n is the bit width of the phase data; f out The output frequency of the DDS IP output signal which needs to be achieved currently;
the step S5 specifically includes the following steps:
s51, setting a signal processing completion mark of the frame in the FPGA;
s52, judging whether the signal processing of the frame is finished by the FPGA; if so, the signal processing of the current frame finishes the sign turnover; if not, the signal processing completion flag of the frame is kept unchanged;
and S53, the FPGA selects the phase increment according to the signal processing completion flag of the frame.
2. The digital down-conversion and Doppler compensation method based on adjustable phase increment of DSP and FPGA according to claim 1, characterized in that in S2, the DSP calculates the compensated Doppler frequency f in real time according to the real speed of the target d Real-time Doppler compensation is carried out on echo signals which are transmitted by a radar and then reflected by a target; the method comprises the following specific steps:
f d ＝2×v_real/λ
wherein v _ real is the real speed of the target; λ is the wavelength of the echo signal.
3. The DSP and FPGA adjustable phase increment-based digital down-conversion and doppler compensation method of claim 2, wherein in S53, specifically: when the signal processing of the frame is finished and the mark is turned over, the FPGA reads the updated phase increment from the internal RAM and uses the phase increment; and when the signal processing completion mark of the frame is kept unchanged, the FPGA continues to use the current phase increment.
4. The DSP and FPGA adjustable phase increment-based digital down-conversion and doppler compensation method of claim 3, wherein said S6 specifically comprises the steps of:
s61, setting parameters of a system clock, a channel number, a spurious-free dynamic range and a frequency resolution of the DDS IP core;
and S62, inputting a reference clock and an updated phase increment to the DDS IP core, so that the DDS IP core takes the reference clock as a reference, and carries out controllable interval sampling on the phase to synthesize a sine and cosine signal with a required frequency.
5. The DSP and FPGA adjustable phase increment based digital down conversion and doppler compensation method of claim 4, wherein said S7 specifically comprises the following steps:
s71, mixing: performing ADC discretization sampling on the echo signal subjected to Doppler compensation to obtain an intermediate frequency signal; calling a multiplier, multiplying the intermediate frequency signal by a sine and cosine signal generated by a DDS IP core, and moving the frequency spectrum of the echo signal to a low-frequency baseband position;
s72, filtering: and filtering harmonic components generated in the mixing processing process through an FIR filter to obtain a low-frequency baseband signal containing target information.
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