CN112688408B - Low-power-consumption ultrasonic energy collection circuit and use method thereof - Google Patents

Abstract

The invention discloses a low-power-consumption ultrasonic energy collection circuit and a using method thereof. The existing ultrasonic energy harvesting circuit is difficult to realize precise on-off control of the load. The present invention is a low power consumption ultrasonic energy collection circuit, comprising a rectifier module, a burst detection module, a switch tube, an ultrasonic collector and an energy storage capacitor. The input interface of the rectifier module is connected with the output interface of the ultrasonic collector; the output interface of the rectifier module is connected with the energy storage capacitor. The switch tube and the load are connected in series between the power supply voltage provided by the rectifier module and the energy storage capacitor and the ground wire. The burst detection module provides a state working signal for the switch tube. In the present invention, the waveform converter, the edge extraction module and the watchdog circuit are connected in series in sequence, the switch tube can be automatically controlled to be turned on when the ultrasonic wave is continuously input, and the switch tube can be controlled to be turned off immediately when the ultrasonic wave is stopped. The control of the signal source realizes the precise control of the load on and off.

Description

A low power consumption ultrasonic energy harvesting circuit and using method thereof

technical field

The invention belongs to the technical field of electric energy conversion, and in particular relates to a low-power consumption ultrasonic energy collection circuit and a using method thereof.

Background technique

The ultrasonic energy harvesting circuit is a circuit that converts mechanical energy into electrical energy and has broad application prospects; however, the capacitor used to stabilize the voltage in the existing ultrasonic energy harvesting circuit will continue to supply power to the load for a period of time after the external ultrasonic source is removed. , resulting in a difference between the working time of the load and the time of supplying and removing the external ultrasonic source, which makes it difficult to achieve precise on-off control of the load.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a low-power consumption ultrasonic energy collection circuit and a method of using the same.

A low-power consumption ultrasonic energy collection circuit of the present invention includes a rectifier module, a burst detection module, a switch tube, an ultrasonic collector Y1 and an energy storage capacitor C_stor. The input interface of the rectifier module is connected with the output interface of the ultrasonic collector Y1; the output interface of the rectifier module is connected with the energy storage capacitor C_stor. The switch tube and the load are connected in series between the power supply voltage V_Rec provided by the rectifier module and the energy storage capacitor C_stor and the ground wire. The burst detection module provides the state working signal Pas/Act for the switch tube. The switch tube controls the on-off of the load according to the state working signal Pas/Act. The burst detection module includes a waveform converter, an edge extraction module and a watchdog circuit which are connected in series. The input end of the waveform converter is connected to the ultrasonic collector Y1, and the signal at the output end of the ultrasonic collector Y1 is converted into a square wave signal. When the frequency of the alternating signal input to the waveform converter is less than the threshold, the switch keeps the load energized; when the frequency of the alternating signal input to the waveform converter is greater than the threshold, the switch controls the load to be powered off.

Preferably, the waveform converter is obtained by connecting an even number of digital inverters in series.

Preferably, the edge extraction module includes a delay unit and an exclusive OR gate. The delay unit includes an even number of inverters connected in series. The output signal of the waveform converter is divided into two channels, one is connected to the first input terminal of the XOR gate, and the other is connected to the second input terminal of the XOR gate after passing through the delay unit.

Preferably, the watchdog circuit includes a current source IS2, a MOS transistor M22, a capacitor C_WD and an inverter U3. The input end of the current source IS2 is connected to the power supply voltage V_Rec, and the output end is connected to the source of the MOS transistor M22, one end of the capacitor C_WD and the input end of the inverter U1. The drain of the MOS transistor M22 and the other end of the capacitor C_WD are both grounded. The gate of the MOS transistor M22 is used as the input end of the watchdog circuit. The output terminal of the inverter U1 outputs the state working signal Pas/Act.

Preferably, a low-power-consumption ultrasonic energy collection circuit of the present invention further includes a double-pass voltage stabilizer module and a start-up circuit module. The rectifier module uses an active rectifier. The dual-pass regulator module is regulated by a series regulator module and a shunt regulator module. The start-up circuit module provides the rectifier module with a start-up work signal SU.

Preferably, the rectifier module includes a field effect transistor MS3, a field effect transistor MS4 and two active diode modules. The grid of the FET MS3 and the drain of the FET MS4 are both connected to the IN1 terminal of the ultrasonic collector Y1; the drain of the FET MS3 and the grid of the FET MS4 are both connected to the IN2 terminal of the ultrasonic collector Y1; The source electrodes of the field effect transistor MS3 and the field effect transistor MS4 are connected together to provide a ground wire. The active diode module includes an active comparator module Comp1 and a dynamic bias module. The active comparator module Comp1 includes a field effect transistor MS1, field effect transistors M1-M8 and a buffer BUF; the gate of the field effect transistor M1 is connected to the externally input reference voltage V_BP1; the drain of the field effect transistor M1 is connected to the field effect transistor M2 The source of the FET M2 is connected to the drain of the FET M3; the gates of the FET M3, the FET M4 and the FET M5 are connected together; the FET M3, the FET M4 , The source of the field effect transistor M5 and the negative power supply terminal of the buffer BUF are connected to the input voltage V_LDO provided by the double-pass voltage regulator module. The drain of the field effect transistor M6 is connected to the drain of the field effect transistor M4, and the gate is connected to the gate of the field effect transistor M7.

The drain of the field effect transistor M7 is connected to the drain of the field effect transistor M5 and the signal input terminal of the buffer BUF. The first input signal end of the NOR gate NOR and the gate of the field effect transistor M2 are connected to the state operating signal Pas/Act provided by the burst detection module. The second input signal terminal of the NOR gate NOR is connected to the start working signal SU. The output signal of the NOR gate NOR is connected to the gate of the field effect transistor M8; the output signal of the buffer BUF is connected to the drain of the field effect transistor M8 and the gate of the field effect transistor MS1. The sources of the field effect transistors M1, M6 and M8, the drain of the field effect transistor MS1, the substrates of the field effect transistors M1 and M2 and the positive power supply terminal of the buffer BUF are connected together to provide the power supply voltage V_Rec. The source electrode of the field effect transistor M7 is connected with the source electrode of the field effect transistor MS1 as a signal input end of the active diode module. The signal input ends of the two active diode modules are respectively connected to the IN1 end and the IN2 end of the ultrasonic collector Y1.

Preferably, the dual-pass voltage regulator module includes a series voltage regulator module and a parallel voltage regulator module. The series regulator module includes a comparator OPAMP1 and a field effect transistor M9. The parallel regulator module includes a comparator OPAMP2, a resistor R1, a current source IS1 and a field effect transistor M10. The inverting input terminal of the comparator OPAMP1 is connected to the reference voltage V_Ref; the non-inverting input terminal of the comparator OPAMP1, the drain electrode of the field effect transistor M9, one end of the resistor R1, the positive power supply terminal of the comparator OPAMP2, and the source electrode of the field effect transistor M10 , One end of the capacitor C_LDO and one end of the resistor R_LDO are connected together to input the voltage V_LDO for the rectifier module. The positive power supply terminal of the comparator OPAMP1 is connected to the power supply voltage V_Rec, and the negative power supply terminal is grounded. The other end of the resistor R1 is connected to the negative electrode of the current source and the inverting input end of the comparator OPAMP2. The positive pole of the current source IS1, the negative power supply terminal of the comparator OPAMP2, the drain of the field effect transistor M10, the other terminal of the capacitor C_LDO and the other terminal of the resistor R_LDO are all grounded. The non-inverting input terminal of the comparator OPAMP2 is connected to the reference voltage V_Ref.

Preferably, the startup circuit module includes an inverter U1, an inverter U2 and field effect transistors M11-M21. One end of the resistor R2 and the sources of the field effect transistors M17 and M18 are all connected to the power supply voltage V_Rec. The gate of the field effect transistor M18, the gate and drain of the field effect transistor M17, the drain of the field effect transistor M21 and the source of the field effect transistor M15 are all connected to the reference voltage V_BP1; the other end of the resistor R2 is connected to the field effect transistor M21 The gate of the inverter U1 is connected to the drain of the field effect transistor M20. The drain of the field effect transistor M18 is connected to the source of the field effect transistor M16; the gate of the field effect transistor M16, the gate and the drain of the field effect transistor M15 and the drain of the field effect transistor M13 are all connected to the reference voltage V_BP2; The gate of the transistor M13, the gate and drain of the field effect transistor M14, the source of the field effect transistor M21, the gate of the field effect transistor M20 and the drain of the field effect transistor M16 are all connected to the reference voltage V_Ref; the field effect transistor M20 The source of the FET M19 is connected to the drain of the FET M19; the source of the FET M13 is connected to the drain of the FET M11. The gate of the field effect transistor M11, the gate and drain of the field effect transistor M12, the source of the field effect transistor M14 and the gate of the field effect transistor M19 are all connected to the reference voltage V_BN1; the source of the field effect transistor M11 is connected to the resistor R3 One end of the FET; the sources of the field effect transistors M12 and M19 and the other end of the resistor R3 are all grounded. The output end of the inverter U1 is connected to the input end of the inverter U2; the output end of the inverter U2 is used for outputting the start working signal SU provided to the rectifier module.

The method of using the low-power ultrasonic energy harvesting circuit is as follows:

An external ultrasonic generator is used to send out ultrasonic waves, and the ultrasonic collector Y1 receives ultrasonic signals and generates alternating voltages. The rectifier module rectifies the alternating voltage and provides the power supply voltage for the switch tube and the load. In the burst detection module, the waveform converter converts the input alternating voltage into a square wave signal; the edge extraction module extracts the rising and falling edges of the square wave signal to form a pulse signal; each pulse in the pulse signal makes the gatekeeper The continuously charged capacitor in the dog circuit is reset, so that the input of the inverter in the watchdog circuit is kept low and the output is kept high; .

When it is necessary to control the power off of the load, control the ultrasonic generator to turn off or make the output frequency of the ultrasonic generator greater than the preset value, so that the edge extraction module cannot continuously provide pulses for the watchdog circuit, and the capacitor in the watchdog circuit is charged to the The inverter outputs a high level; the inverter outputs a low level to the switch tube; the switch tube is turned off, so that the load is powered off.

The beneficial effects that the present invention has are:

1. In the present invention, through the waveform converter, the edge extraction module and the watchdog circuit connected in series in sequence, the switch tube can be automatically controlled to be turned on when the ultrasonic wave is continuously input, and the switch tube can be controlled to be turned off immediately when the ultrasonic wave stops. The control of the external ultrasonic signal source realizes the precise control of the load on and off, and can accurately control the electronic components implanted in the human body.

2. The present invention proposes a novel active rectifier. By changing the positive and negative power supply voltages of the comparator, the functions of reducing the propagation delay of the comparator and the power consumption of the active diode are realized, and the propagation delay can be reduced.

3. The present invention proposes a burst detection circuit, which enables other circuits to enter a low power consumption working mode when no signal is input or the frequency of the input signal is lower than a certain threshold, thereby reducing circuit energy consumption.

4. The present invention proposes a new type of double-pass voltage regulator, which utilizes the discharge current of the parasitic capacitance and the average current drawn from the power supply by the comparator to adjust the output current to achieve the effect of low power consumption.

Description of drawings

1 is a schematic diagram of the circuit principle of the present invention;

Fig. 2 is the circuit schematic diagram of the burst detection module in the present invention;

FIG. 3 is a timing diagram when the burst detection module in the present invention detects an input signal.

4 is a schematic diagram of an active diode module circuit in the present invention;

5 is a schematic diagram of a dual-pass voltage regulator module in the present invention;

FIG. 6 is a schematic diagram of a reference voltage and a start-up circuit module in the present invention.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings.

As shown in Figure 1, a low-power ultrasonic energy harvesting circuit includes a rectifier module 1, a burst detection module 3, a double-pass voltage regulator module 4, a reference voltage and a start-up circuit module 5, a switch tube 6, and an ultrasonic collector. Y1 and storage capacitor C_stor. The ultrasonic collector Y1 can convert ultrasonic energy into alternating voltage and output it, and the energy storage capacitor C_stor plays the role of energy storage in the circuit. The rectifier module 1 adopts an active rectifier. The two input ends of the rectifier module 1 are respectively connected to both ends of the ultrasonic collector Y1; the output interface of the rectifier module 1 is connected to both ends of the energy storage capacitor C_stor, and provides the power supply voltage V_Rec. The switch tube 6 and the load are connected in series between the power supply voltage V_Rec and the ground wire. The input end of the burst detection module 3 is connected to the IN1 end of the ultrasonic collector Y1, and the output end provides the state working signal Pas/Act for the rectifier module 1 and the switch tube 6, so that the enable of the switch tube 6 is controlled by the burst detection module 3 . The dual-pass voltage regulator module 4 performs voltage regulation through the series voltage regulator module and the parallel voltage regulator module. The start-up circuit module 5 provides the rectifier module 1 with a start-up work signal SU. When the control pin EN of the switch tube 6 inputs a high level, the switch tube 6 is turned on; when the control pin EN of the switch tube 6 inputs a low level, the switch tube 6 is turned off.

When the ultrasonic collector Y1 collects ultrasonic signals, the two ends (IN1, IN2) of the ultrasonic collector Y1 output an AC voltage, which is rectified by the rectifier module 1 and converted into a DC power supply voltage V_Rec. The burst detection module 3 detects whether an ultrasonic signal is input. If there is no ultrasonic signal, the burst detection module 3 makes other circuit modules enter the low-power working mode, and the switch tube 6 will limit the current flowing through the load, so that the load is powered off. In this embodiment, the load is the light-emitting diode LED1, that is, the light-emitting diode LED1 is turned off at this time. In this way, the real-time power-off of the load can be realized when the external ultrasonic output is removed, so as to precisely control the power-on and power-off of the load through the external ultrasonic signal source. Also, the electrical energy stored on the storage capacitor C_stor can power other circuits for a longer time. The switch tube 6 module can be implemented using an active circuit, such as a current mirror/digital-to-analog converter, and its active module can be powered by the V_LDO voltage. In order to reduce the interference of the AC signal, a capacitor C_LDO is connected in series at the output end of the dual-pass regulator 4, and the capacitance value is 77pF.

As shown in FIGS. 2 and 3 , the burst detection module 3 includes a waveform converter 3-1, an edge extraction module 3-2 and a watchdog circuit 3-3 which are connected in series in sequence. The waveform converter 3-1 is obtained by connecting an even number of digital inverters in series, and can convert the analog signal output from the IN1 terminal of the ultrasonic collector Y1 into a square wave signal. The edge extraction module 3-2 includes a delay unit and an exclusive OR gate. The delay unit includes an even number of inverters connected in series. The output node X of the waveform converter 3-1 is divided into two paths, one is connected to the first input terminal of the XOR gate, and the other is connected to the second input terminal of the XOR gate after passing through the delay unit, so that the XOR gate is connected to the second input terminal of the XOR gate. The signals at the two input terminals of the gate have a certain phase difference. The output node Z of the edge extraction module 3-2 is connected to the input terminal of the watchdog circuit 3-3. The watchdog circuit 3-3 includes a current source IS2, a MOS transistor M22, a capacitor C_WD and an inverter U3. The input end of the current source IS2 is connected to the power supply signal V_Rec, and the output end is connected to the source of the MOS transistor M22, one end of the capacitor C_WD and the input end of the inverter U1. The drain of the MOS transistor M22 and the other end of the capacitor C_WD are both grounded. The gate of the MOS transistor M22 is used as the input terminal of the watchdog circuit 3-3, and is connected to the output node Z of the edge extraction module 3-2. The output end of the inverter U1 is the output end of the burst detection module 3 , which is used to output the state working signal Pas/Act.

As shown in Figure 3, the edge extractor module generates short reset pulses at its output node Z for each falling or rising edge of the signal at node X and feeds them to the watchdog circuit 3-3. In the watchdog circuit 3-3, the capacitor C_WD is continuously charged by the current source IS2. The reset pulse at node Z triggers FET M22 on watchdog circuit 3-3 to reset the voltage on capacitor C_WD. Therefore, in the presence of ultrasonic waves, the voltage at the node U is lower than the trigger point of the output inverter, which causes the state operating signal Pas/Act output by the burst detection module 3 to maintain a high logic level. At this time, the switch tube 6 does not Limit the current on the load. Otherwise, if node IN1 does not oscillate for a certain period of time, M22 will not reset the DC voltage. Therefore, the DC voltage will be charged to a certain level higher than the trigger point of the output inverter, and cause the state operating signal Pas/Act output by the burst detection module 3 to become a low logic level. The circuit consumes little power in the absence of ultrasound or the ultrasound signal below a certain threshold.

As shown in FIG. 4 , the rectifier module 1 includes a field effect transistor MS3 , a field effect transistor MS4 and two active diode modules 2 . The grid of the FET MS3 and the drain of the FET MS4 are both connected to the IN1 terminal of the ultrasonic collector Y1; the drain of the FET MS3 and the grid of the FET MS4 are both connected to the IN2 terminal of the ultrasonic collector Y1; The source electrodes of the field effect transistor MS3 and the field effect transistor MS4 are connected together to provide a ground wire.

The active diode module 2 includes an active comparator module Comp1 and a dynamic bias module. The active comparator module Comp1 includes field effect transistors M1 to M7 and a buffer BUF; the gate of the field effect transistor M1 is connected to the reference voltage V_BP1 input from the outside; the reference voltage V_BP1 provides a startup voltage for the active comparator module Comp1; the field effect transistor M1 The drain of the FET M2 is connected to the source of the FET M2, and the drain of the FET M2 is connected to the drain of the FET M3; the gates of the FET M3, the FET M4 and the FET M5 are connected together; The source of the effect transistor M3 , the field effect transistor M4 , the field effect transistor M5 and the negative power supply terminal of the buffer BUF are all connected to the input voltage V_LDO provided by the double-pass voltage regulator module 4 . The drain of the field effect transistor M6 is connected to the drain of the field effect transistor M4, and the gate is connected to the gate of the field effect transistor M7.

The drain of the field effect transistor M7 is connected to the drain of the field effect transistor M5 and the signal input terminal of the buffer BUF. The first input signal terminal of the NOR gate NOR and the gate of the field effect transistor M2 are connected to the state operating signal Pas/Act provided by the burst detection module 3 . The second input signal terminal of the NOR gate NOR is connected to the start working signal SU. The output signal of the NOR gate NOR is connected to the gate of the field effect transistor M8; the output signal of the buffer BUF is connected to the drain of the field effect transistor M8 and the gate of the field effect transistor MS1. The sources of field effect transistors M1, M6 and M8, the drain of field effect transistor MS1, the substrates of field effect transistors M1 and M2 and the positive power supply terminal of the buffer BUF are connected together to output the power supply voltage V_Rec provided by the rectifier module 1 . The source of the field effect transistor M7 is connected to the source of the field effect transistor MS1 as a signal input terminal of the active diode module 2 . The signal input ends of the two active diode modules 2 are respectively connected to the IN1 end and the IN2 end of the ultrasonic collector Y1.

In principle, the active diode module 2 consists of a comparator module and a dynamic bias module. There is a buffer BUF composed of a series of inverters in the comparator module. The buffer BUF is powered by the power supply voltage V_Rec and the voltage V_LDO to drive the switch tube MS1. The state work signal Pas/Act is the output signal of the burst detection module 3 , and the start work signal SU is the output signal of the reference voltage and the start circuit module 5 . The state work signal Pas/Act and the start work signal SU signal control the turn-on and turn-off of the field effect transistor M8 through the NOR gate output signal. The reference voltage V_BP1 is used to bias the switch M1. When there is no external signal input, the Pas/Act signal is low, so that the switch tube M2 is turned off, and the current in the circuit is cut off to reduce power consumption. When there is no external signal input or during the startup of the circuit, the field effect transistor M8 is turned on. At this time, the field effect transistor MS1 can be regarded as a diode.

The resolution V _in,min of the comparator in the active diode can be defined as the minimum differential input voltage between its high and low level switching that the comparator can detect, which can be expressed by the following formula:

where _VR2RS is the rail-to-rail supply voltage of the comparator and A _DC is the DC gain of the comparator. When the input differential voltage of the comparator increases above the resolution value, the comparator will enter large-signal mode and its propagation delay (t _P ) is mainly determined by _VR2RS and slew rate (SR), as shown in the following equation:

However, the slew rate (SR) depends on the current drive capability of the comparator output branch and the parasitic capacitance of the comparator output node. Therefore, improving SR usually requires higher power consumption. Therefore, reducing _VR2RS can increase the _tP of the comparator without incurring additional power dissipation.

As shown in FIG. 5 , the dual-pass voltage regulator module 4 includes a series voltage regulator module and a parallel voltage regulator module. The first reference input terminal, the second reference input terminal, and the third reference input terminal of the dual-pass voltage regulator module 4 are respectively connected to the IN1 terminal of the ultrasonic collector Y1, the power supply voltage V_Rec, and the reference voltage V_Ref. The series regulator module includes a comparator OPAMP1 and a field effect transistor M9. The parallel regulator module includes a comparator OPAMP2, a resistor R1, a current source IS1 and a field effect transistor M10. The inverting input terminal of the comparator OPAMP1 is connected to the reference voltage V_Ref; the non-inverting input terminal of the comparator OPAMP1 is connected to the drain of the field effect transistor M9, one end of the resistor R1, the positive power supply terminal of the comparator OPAMP2, and the source of the field effect transistor M10 , one end of capacitor C_LDO and one end of resistor R_LDO. The positive power supply terminal of the comparator OPAMP1 is connected to the power supply voltage V_Rec, and the negative power supply terminal is grounded. The other end of the resistor R1 is connected to the negative electrode of the current source and the inverting input end of the comparator OPAMP2. The positive pole of the current source IS1, the negative power supply terminal of the comparator OPAMP2, the drain of the field effect transistor M10, the other terminal of the capacitor C_LDO and the other terminal of the resistor R_LDO are all grounded. The non-inverting input terminal of the comparator OPAMP2 is connected to the reference voltage V_Ref.

In principle, I_RU1 and I_RU2 in the rectifier module 1 represent the average discharge current of the parasitic capacitance C_GS1 and the average current drawn by the comparator from V_Rec, respectively. Similarly, C_GS1, I_RU3 and I_RU4 can be defined in active diode 2. In the figure,

I_RU=I_RU1+I_RU2+I_RU3+I_RU4

1) When I_LDO<I_RU, the voltage on C_LDO starts to rise. At this time, the average current conducted by the series regulator is I _Shunt =I_RU-I_LDO, and the switch tube M10 connects the excess current to the ground.

2) When I_LDO>I_RU, the voltage on C_LDO starts to decrease. At this time, the average current delivered by the series regulator is I _Series =I_LDO-I_RU to compensate the load current I_LDO.

In traditional linear regulators, a resistive divider is used to adjust V_LDO to the desired reference voltage. In order to reduce the power consumption of the voltage divider circuit, a larger resistance is usually selected, in this circuit, this step is omitted by making the input reference voltage V_Ref equal to the desired voltage V_LDO. In order to reduce the output oscillation of the regulator, the reference voltage V_Ref is compared with the comparator and then output. In the present invention, the reverse input terminal in the comparator OPAMP2 realizes the function of reverse voltage input by being connected with a current source.

As shown in FIG. 6 , the startup circuit module 5 includes an inverter U1 , an inverter U2 and field effect transistors M11 to M21 . One end of the resistor R2 and the sources of the field effect transistors M17 and M18 are all connected to the power supply voltage V_Rec. The gate of the field effect transistor M18, the gate and drain of the field effect transistor M17, the drain of the field effect transistor M21 and the source of the field effect transistor M15 are all connected to the reference voltage V_BP1; the other end of the resistor R2 is connected to the field effect transistor M21 The gate of the inverter U1 is connected to the drain of the field effect transistor M20. The drain of the field effect transistor M18 is connected to the source of the field effect transistor M16; the gate of the field effect transistor M16, the gate and the drain of the field effect transistor M15 and the drain of the field effect transistor M13 are all connected to the reference voltage V_BP2; The gate of the transistor M13, the gate and drain of the field effect transistor M14, the source of the field effect transistor M21, the gate of the field effect transistor M20 and the drain of the field effect transistor M16 are all connected to the reference voltage V_Ref; the field effect transistor M20 The source of the FET M19 is connected to the drain of the FET M19; the source of the FET M13 is connected to the drain of the FET M11. The gate of the field effect transistor M11, the gate and drain of the field effect transistor M12, the source of the field effect transistor M14 and the gate of the field effect transistor M19 are all connected to the reference voltage V_BN1; the source of the field effect transistor M11 is connected to the resistor R3 One end of the FET; the sources of the field effect transistors M12 and M19 and the other end of the resistor R3 are all grounded. The output end of the inverter U1 is connected to the input end of the inverter U2 ; the output end of the inverter U2 is used for outputting the starting working signal SU provided to the rectifier module 1 .

In principle, the reference voltage and start-up circuit module 5 is used to provide the reference voltage V_Ref and the start-up signal SU to other circuits. When the reference voltage and the start-up circuit module work, the field effect transistor M21 is turned on. Two inverters are connected in series with the gate of the field effect transistor M21, and the output start-up operation signal SU is used as the start-up signal of the rectifier module 1 in the present invention.

The specific use method of the low-power ultrasonic energy harvesting circuit is as follows:

Step 1: The startup circuit module 5 provides the reference voltage V_Ref, the reference voltage V_BP1 and the startup working signal SU to the rectifier module 1 , and provides the reference voltage V_Ref to the dual-pass voltage regulator module 4 and the switch tube 6 . V_BP1 is used to bias the FET M1 in the rectifier module 1 .

Step 2: The external ultrasonic generator UT1 sends out ultrasonic waves, and the ultrasonic collector Y1 receives ultrasonic signals and generates alternating voltages. When the frequency of the alternating voltage reaches a certain threshold, the state operating signal Pas/Act sent by the burst detection module 3 to the rectifier module 1 and the switch tube 6 module maintains a high level, so that the rectifier module 1 works, and the switch tube 6 is connected to the load. The output terminal keeps the low level, the energy storage capacitor C_stor is in the charging state, and the light-emitting diode LED1 as the load is turned on to emit light.

Step 3. When there is no external ultrasonic signal or the frequency of the external ultrasonic signal is lower than a certain threshold, the state operating signal Pas/Act output by the burst detection module 3 becomes a low level, so that the active diode module in the rectifier module 1 2 is turned off, and the switch tube 6 is turned off.

The output terminal connected to the load becomes a high level, the light-emitting diode LED1 as the load goes out, and the power consumption of the circuit is reduced. At the same time, the reference voltage is provided by the storage capacitor C_stor.

Claims (6)

1. A low power consumption ultrasonic energy collection circuit, characterized in that: it comprises a rectifier module (1), a burst detection module (3), a switch tube (6), an ultrasonic collector Y1 and an energy storage capacitor C_stor; the rectifier module ( The input interface of 1) is connected to the output interface of the ultrasonic collector Y1; the output interface of the rectifier module (1) is connected to the energy storage capacitor C_stor; the switch tube (6) and the load are connected in series by the rectifier module (1) and the energy storage capacitor C_stor. between the provided power supply voltage V_Rec and the ground wire; the burst detection module (3) provides the switch tube (6) with a state work signal Pas/Act; the switch tube (6) controls the load according to the state work signal Pas/Act. Power on and off; the burst detection module (3) includes a waveform converter (3-1), an edge extraction module (3-2) and a watchdog circuit (3-3) connected in series in sequence; the waveform converter (3-1) ) is connected to the input terminal of the ultrasonic collector Y1, and the output terminal signal of the ultrasonic collector Y1 is converted into a square wave signal; when the frequency of the alternating signal input to the waveform converter (3-1) is less than the threshold value, the switching tube (6 ) to keep the load energized; when the frequency of the alternating signal input to the waveform converter (3-1) is greater than the threshold, the switch tube (6) controls the load to be powered off; The waveform converter (3-1) is obtained by connecting an even number of digital inverters in series; the edge extraction module (3-2) includes a delay unit and an exclusive OR gate; The output signal is divided into two channels, one is connected to the first input end of the XOR gate, and the other is connected to the second input end of the XOR gate after passing through the delay unit; the delay unit includes an even number of serially connected inverter; The watchdog circuit (3-3) includes a current source IS2, a MOS tube M22, a capacitor _{C_WD} and an inverter U3; the input terminal of the current source IS2 is connected to the power supply voltage _{V_Rec} , and the output terminal is connected to the source of the MOS tube M22 pole, one end of the capacitor C_WD and the input end of the inverter U1; the drain of the MOS tube M22 and the other end of the capacitor C_WD are grounded; the gate of the MOS tube M22 is used as the input end of the watchdog circuit (3-3); The output terminal of the inverter U1 outputs the state working signal Pas/Act. 2. A low-power consumption ultrasonic energy harvesting circuit according to claim 1, characterized in that: it further comprises a double-pass voltage stabilizer module (4), a start-up circuit module (5); the rectifier module (1) adopts an active a rectifier; the double-pass voltage regulator module (4) performs voltage regulation through the series voltage regulator module and the parallel voltage regulator module; the starting circuit module (5) provides the rectifier module (1) with a start working signal SU. 3. A low power consumption ultrasonic energy collection circuit according to claim 2, characterized in that: the rectifier module (1) comprises a field effect transistor MS3, a field effect transistor MS4 and two active diode modules (2 ); the gate of FET MS3 and the drain of FET MS4 are both connected to the IN1 terminal of the ultrasonic collector Y1; the drain of the FET MS3 and the gate of the FET MS4 are both connected to the IN2 of the ultrasonic collector Y1 terminal; the source electrodes of the FET MS3 and the FET MS4 are connected together to provide a ground wire; the active diode module (2) includes the active comparator module Comp1 and the dynamic bias module; the active comparator module Comp1 includes the field effect tube MS1, field effect transistors M1~M8 and buffer BUF; the gate of the field effect transistor M1 is connected to the externally input reference voltage V_BP1; the drain of the field effect transistor M1 is connected to the source of the field effect transistor M2, and the The drain is connected to the drain of the field effect transistor M3; the gates of the field effect transistor M3, the field effect transistor M4 and the field effect transistor M5 are connected together; the source electrodes of the field effect transistor M3, the field effect transistor M4, and the field effect transistor M5 and The negative power supply terminal of the buffer BUF is connected to the input voltage V_LDO provided by the double-pass voltage regulator module (4); the drain of the field effect transistor M6 is connected to the drain of the field effect transistor M4, and the gate is connected to the gate of the field effect transistor M7 ; The drain of the field effect transistor M7 is connected to the drain of the field effect transistor M5 and the signal input terminal of the buffer BUF; the first input signal terminal of the NOR gate NOR and the gate of the field effect transistor M2 are connected to the burst detection module (3 ) provides the state working signal Pas/Act; the second input signal end of the NOR gate NOR is connected to the start working signal SU; the output signal of the NOR gate NOR is connected to the gate of the field effect transistor M8; the output signal of the buffer BUF Terminate the drain of the field effect transistor M8 and the gate of the field effect transistor MS1; the sources of the field effect transistors M1, M6, M8, the drain of the field effect transistor MS1, the substrate and the buffer of the field effect transistors M1, M2 The positive power terminals of the BUF are connected together to provide the power supply voltage V_Rec; the source of the field effect transistor M7 is connected with the source of the field effect transistor MS1 as the signal input terminal of the active diode module (2); two active The signal input end of the diode module (2) is respectively connected to the IN1 end and the IN2 end of the ultrasonic collector Y1. 4. A low power consumption ultrasonic energy harvesting circuit according to claim 2, characterized in that: the two-pass voltage stabilizer module (4) comprises a series voltage stabilizer module and a shunt voltage stabilizer module; The voltage regulator module includes a comparator OPAMP1 and a field effect transistor M9; the shunt voltage regulator module includes a comparator OPAMP2, a resistor R1, a current source I _S1 and a field effect transistor M10; the inverse input end of the comparator OPAMP1 is connected to the reference voltage V_Ref; The non-inverting input terminal of the comparator OPAMP1, the drain of the field effect transistor M9, one end of the resistor R1, the positive power supply terminal of the comparator OPAMP2, the source electrode of the field effect transistor M10, one end of the capacitor C_LDO and one end of the resistor R_LDO are connected together, It is the input voltage V_LDO of the rectifier module (1); the positive power supply terminal of the comparator OPAMP1 is connected to the power supply voltage V_Rec, and the negative power supply terminal is grounded; the other end of the resistor R1 is connected to the negative electrode of the current source and the inverting input terminal of the comparator OPAMP2; the current source I The positive pole of _S1 , the negative power supply terminal of the comparator OPAMP2, the drain of the FET M10, the other terminal of the capacitor C_LDO and the other terminal of the resistor R_LDO are all grounded; the non-inverting input terminal of the comparator OPAMP2 is connected to the reference voltage V_Ref. 5. A low-power-consumption ultrasonic energy harvesting circuit according to claim 2, characterized in that: the startup circuit module (5) comprises an inverter U1, an inverter U2 and field effect transistors M11-M21; One end of the resistor R2 and the sources of the field effect transistors M17 and M18 are all connected to the power supply voltage V_Rec; the gate of the field effect transistor M18, the gate and the drain of the field effect transistor M17, the drain of the field effect transistor M21 and the field effect transistor The source of M15 is connected to the reference voltage V_BP1; the other end of the resistor R2 is connected to the gate of the field effect transistor M21, the input end of the inverter U1 and the drain of the field effect transistor M20; the drain of the field effect transistor M18 is connected to the field The source of the effect transistor M16; the gate of the field effect transistor M16, the gate and the drain of the field effect transistor M15 and the drain of the field effect transistor M13 are all connected to the reference voltage V_BP2; the gate of the field effect transistor M13, the field effect transistor The gate and drain of M14, the source of field effect transistor M21, the gate of field effect transistor M20 and the drain of field effect transistor M16 are all connected to the reference voltage V_Ref; the source of field effect transistor M20 is connected to the Drain; the source of the FET M13 is connected to the drain of the FET M11; the gate of the FET M11, the gate and the drain of the FET M12, the source of the FET M14 and the FET M19 The gates of the MOSFETs are connected to the reference voltage V_BN1; the source of the field effect transistor M11 is connected to one end of the resistor R3; the sources of the field effect transistors M12 and M19 and the other end of the resistor R3 are all grounded; the output of the inverter U1 is connected to the reverse phase The input end of the inverter U2; the output end of the inverter U2 is used for outputting the start working signal SU provided to the rectifier module (1). 6. the using method of a kind of low power consumption ultrasonic energy collection circuit as claimed in claim 1, it is characterized in that: use external ultrasonic generator to send out ultrasonic wave, ultrasonic wave collector Y1 receives ultrasonic signal and produces alternating voltage; Rectifier module (1) Rectify the alternating voltage to provide power supply voltage for the switch tube and load; in the burst detection module (3), the waveform converter (3-1) converts the input alternating voltage into a square wave signal; edge extraction The module (3-2) extracts the rising and falling edges of the square wave signal to form a pulse signal; each pulse in the pulse signal resets the continuously charged capacitor in the watchdog circuit (3-3), thereby allowing the watchdog The input of the inverter in the dog circuit (3-3) keeps a low level, and the output keeps a high level; the high level output by the watchdog circuit (3-3) keeps the switch tube (6) in a conducting state all the time ; When it is necessary to control the load to be powered off, control the ultrasonic generator to turn off or make the output frequency of the ultrasonic generator greater than the preset value, so that the edge extraction module (3-2) cannot continuously provide pulses for the watchdog circuit (3-3), The capacitor in the watchdog circuit (3-3) is charged to output a high level to the inverter; the output of the inverter to the switch tube (6) keeps a low level; the switch tube (6) is turned off, so that the load is powered off .

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