CN112688338A - UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering - Google Patents

Abstract

The invention provides a UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering, which is used for carrying out steady-state linear Kalman filter control on a three-phase UPQC system under a nonlinear load so as to realize power quality compensation. Firstly, designing a structural topology of a UPQC system, and designing parameters according to the designed structural topology; then, filtering the voltage based on a steady-state linear Kalman filter of the frequency locking loop FLL to calculate a voltage fundamental wave positive sequence component; and finally, generating a UPQC reference signal to control the UPQC according to the generated voltage positive sequence fundamental wave component. The method adopts SSLKF-FLL control, can obviously improve direct current offset filtering, has the characteristics of less calculation amount and high dynamic response speed, can better improve the capacity of UPQC for controlling the electric energy quality of the system, can improve the electric energy quality of the power grid under nonlinear load, improves the stability and robustness of the power grid, and enhances the control effect and the dynamic response performance of the UPQC system.

Description

A UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filter

technical field

The invention relates to the field of power electronic control, in particular to a UPQC power quality compensation control method based on a frequency-locked loop steady-state linear Kalman filter.

Background technique

The rapid development of nonlinear loads in power systems leads to the deterioration of power quality (PQ) at the point of common coupling. Non-linear loads are mostly based on power electronics. The flexible AC transmission system (FACTS) device based on power electronic technology is the most effective means to improve the reliability and control ability of reactive power in the transmission system. FACTS guarantees system flexibility and fast response to failures. The unified power flow controller (UPFC) can be used to regulate and control the bus voltage and power flow in the DC transmission system. In order to improve the power quality of the distribution network, FACTS devices such as parallel connection, series connection and hybrid connection are also configured. Among these devices, a unified power quality controller (UPQC) is a hybrid device similar to a UPFC that combines the functions of parallel and series active power compensators (APFs). The parallel type APF is used to compensate the power quality problem of current, while the series type APF is used to compensate the power quality problem of voltage. At the same time, UPQC can also improve the power factor of the system. Therefore, UPQC is considered to be the most effective device to solve the power quality problem.

Commonly used control techniques for UPQC include Instantaneous Reactive Power Theory (IRPT), Synchronous Reference Frame Theory (SRF), Unit Vector Template Method, and Instantaneous Symmetric Component Theory (ISCT). Among these theories, the SRF algorithm has the simplest structure and the lowest computational cost, and is the simplest control method. Among them, the extraction of the fundamental component of the grid voltage is an important requirement for injecting balanced positive sequence current under the condition of asymmetric voltage or harmonic distortion. However, the SRF algorithm needs to use a low-pass filter (LPF), which will cause signal delay and affect the fundamental voltage of the grid. The extraction of components has adverse effects, affects the control effect of UPQC, and is not conducive to the compensation of power quality. The traditional second-order generalized integrator frequency-locked loop (SOGI-FLL) filter extracts the fundamental component, which has high accuracy in the case of grid voltage smoothing. However, due to the limited attenuation capability of the second-order generalized integrator (SOGI) filter, the synchronization error is large under the condition of distorted grid, and it is extremely susceptible to the influence of low-order harmonics and DC offset in the system.

SUMMARY OF THE INVENTION

The purpose of the present invention is to propose a UPQC power quality compensation control method based on a frequency-locked loop steady-state linear Kalman filter, which can better improve the UPQC's ability to control the power quality of the system.

The technical solution of the present invention is: a UPQC power quality compensation control method based on a frequency-locked loop steady-state linear Kalman filter, comprising the following steps:

Step 1: Design the structural topology of the UPQC system, and design parameters for the structural topology;

Step 2: Use the steady-state linear Kalman filter SSLKF based on the frequency-locked loop FLL to filter the α component v _a and the β component v _b of the voltage to obtain the positive sequence component of the voltage fundamental wave.

Step 3: According to the voltage fundamental wave component generated in Step 2, generate the UPQC reference signal to control the UPQC, and trigger the compensator to generate the compensation current and the compensation voltage.

A UPQC power quality compensation control system based on frequency-locked loop steady-state linear Kalman filter, including the following modules:

Structural and parameter design module: used to design the structural topology of the UPQC system, and design parameters for the structural topology;

Filtering module: used to filter the α component v _a and the β component v _b of the voltage to obtain the positive sequence component of the voltage fundamental wave;

Compensator trigger module: It is used to use the voltage fundamental wave component generated by the filter module to generate the UPQC reference signal according to the proposed control strategy to control the UPQC, and trigger the compensator to generate compensation current and compensation voltage.

Compared with the prior art, the beneficial effects of the present invention are: 1) the steady-state linear Kalman filter (SSLKF) control is performed on the three-phase UPQC system under the nonlinear load, so as to improve the power quality of the power grid under the nonlinear load, Improve the stability and robustness of the power grid, and enhance the control effect and dynamic response performance of the UPQC system; 2) SSLKF-FLL significantly improves the DC offset filtering, has the characteristics of less calculation and fast dynamic response, and can better Improve UPQC's ability to control system power quality.

The present invention will be further described in detail below in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 is the topological structure diagram of UPQC of the present invention.

FIG. 2 is a structural diagram of a frequency-locked loop based on a steady-state linear Kalman filter of the present invention.

FIG. 3 is a Bode plot of the SSLKF-FLL of the in-phase component (V _fα ) of the present invention with respect to the input signal (V _in )

FIG. 4 is a diagram of generating a reference signal of an UPQC compensator by adopting the SSLKF-FLL method in an embodiment of the present invention.

FIG. 5 is a dynamic characteristic diagram of an UPQC control algorithm and a parallel converter in an embodiment of the present invention.

FIG. 6 is a graph of steady-state and dynamic responses of UPQC using SSLKF-FLL in an embodiment of the present invention.

Detailed ways

A UPQC power quality compensation control method based on a frequency-locked loop steady-state linear Kalman filter, characterized in that it includes the following steps:

Step 1: Combined with Figure 1, design the structural topology of the UPQC system, and design parameters for the structural topology, including the following steps:

Step 1-1: The UPQC system includes a parallel compensator, a series compensator, an additional DC capacitor, a series-parallel interface inductor, and a ripple filter. The DC bus voltage is controlled by SSLKF-FLL algorithm, proportional and integral PI control and sinusoidal Pulse width modulation SPWM switching technology, each compensator is composed of six insulated gate bipolar transistor IGBT switches, and the series and parallel compensators are respectively connected to the grid through series-parallel interface inductors;

Step 1-2: The parameters of the UPQC system are designed as follows: Calculate the DC voltage V _DC :

Among them, m is the modulation index, and _VL is the grid voltage;

Calculate the shunt compensator phase current I _sh :

Among them, f _sw is the switching frequency, I _{cr, pp} is the current ripple, and a is the overload coefficient;

Calculate the DC capacitance C _DC :

Among them, k is the energy dynamic change coefficient, V _ph is the phase voltage, t is the time to restore the DC line voltage, and V _DC1 is the minimum DC voltage value;

Calculate the series interface inductor L _se :

Among them: I _{cr, swell} is the ripple current, N is the turns ratio.

Step 2: Filter the α component v _a and the β component v _b of the voltage with a steady-state linear Kalman filter (SSLKF) based on a frequency-locked loop (FLL) to obtain the positive sequence component of the voltage fundamental wave, specifically:

The alpha component v _a and beta component v _b of the voltage are filtered with a frequency-locked loop (FLL) based steady-state linear Kalman filter (SSLKF) to calculate the voltage fundamental components v _fa and v _fb :

Among them, ω is a constant, v _in is the power supply voltage v _sabc , and k ₁ and k ₂ are Kalman parameters.

Step 3: According to the voltage fundamental wave component generated in step 2, generate the UPQC reference signal to control the UPQC, and trigger the compensator to generate the compensation current and compensation voltage, specifically:

Step 3-1: Calculate using the fundamental voltage components v _fa and v _fb and the quadrature components qv _fa and qv _fb obtained by quadrature transformation:

和

进行逆变换得到

Step 3-2: Use the inverse of the Clark transformation matrix to calculate the fundamental positive sequence voltage

and

Inverse transform to get

和实际测得的直流电压V_DC的差值得到v_de，其差值经过PI控制器得到功率损耗分量P_loss，计算公式为：Step 3-3: Calculate the reference DC link voltage

The difference between the actual measured DC voltage V _DC is v _de , and the difference is obtained through the PI controller to obtain the power loss component P _loss , and the calculation formula is:

P _loss (t)=P _loss (t-1)+k _p {v _de (t)-v _de (t-1)}

和实际测得的直流电压V_DC的差值；Among them, the power P _loss (t) is the active power of the supply current at time t, P _loss not only includes all switching losses, but also the loss of the UPQC device, kp is the droop control coefficient, and v _de (t) is the reference at time t. DC link voltage

The difference between the actual measured DC voltage V _DC ;

Do the dot product processing of the load voltage V _labc and the load current i _labc to obtain the average load power P _lavg , then the reference power P _ref is expressed as:

P _ref =P _lavg +P _loss

Step 3-4: Generate compensation current, specifically:

Step 3-4-1: Calculate the reference current

为实际测得的平衡正序参考电网输入电压；in,

is the actual measured balanced positive sequence reference grid input voltage;

与侧到的实际电流i_sabc做差运算后，将其差值信号送入到SPWM脉冲触发器中，在脉冲触发器中生成补偿电流控制信号控制并联补偿器中VSC换流器开关的关断；从而完成补偿；Step 3-4-2: Insert the reference current

After doing the difference operation with the actual current i _sabc from the side, the difference signal is sent to the SPWM pulse trigger, and the compensation current control signal is generated in the pulse trigger to control the turn-off of the VSC converter switch in the parallel compensator. ; to complete the compensation;

Step 3-5: Generate compensation voltage, specifically:

Step 3-5-1: Calculate the reference load voltage

为设定的峰值参考电压，

为单元模板；in,

is the set peak reference voltage,

is the unit template;

与侧到的实际负载电压v_labc做差运算后，将其差值信号送入到SPWM脉冲触发器中，在脉冲触发器中生成补偿电压控制信号控制串联补偿器中VSC换流器开关的关断，从而生成完成补偿。Step 3-5-2: Set the reference load voltage

After doing the difference operation with the actual load voltage v _labc on the side, the difference signal is sent to the SPWM pulse trigger, and the compensation voltage control signal is generated in the pulse trigger to control the closing of the VSC converter switch in the series compensator. is interrupted, thereby generating a complete compensation.

A UPQC power quality compensation control system based on frequency-locked loop steady-state linear Kalman filter, including the following modules:

Structural and parameter design module: used to design the structural topology of the UPQC system, and design parameters for the structural topology;

Filtering module: used to filter the α component v _a and the β component v _b of the voltage to obtain the positive sequence component of the voltage fundamental wave;

Compensator trigger module: It is used to generate the UPQC reference signal to control the UPQC by using the voltage fundamental wave component generated by the filter module, and trigger the compensator to generate compensation current and compensation voltage.

A computer device, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, wherein the processor implements the following steps when executing the computer program:

Step 1: Design the structural topology of the UPQC system, and design parameters for the structural topology, including the following steps:

Step 1-1: The UPQC system includes a parallel compensator, a series compensator, an additional DC capacitor, a series-parallel interface inductor, and a ripple filter. The DC bus voltage is controlled by SSLKF-FLL algorithm, proportional and integral PI control and sinusoidal Pulse width modulation SPWM switching technology, each compensator is composed of six insulated gate bipolar transistor IGBT switches, and the series and parallel compensators are respectively connected to the grid through series-parallel interface inductors;

Step 1-2: The UPQC system parameters are as follows: Calculate the DC voltage V _DC :

Among them, m is the modulation index, and _VL is the grid voltage;

Calculate the shunt compensator phase current I _sh :

Among them, f _sw is the switching frequency, I _{cr, pp} is the current ripple, and a is the overload coefficient;

Calculate the DC capacitance C _DC :

Among them, k is the energy dynamic change coefficient, V _ph is the phase voltage, t is the time to restore the DC line voltage, and V _DC1 is the minimum DC voltage value;

Calculate the series interface inductor L _se :

Among them: I _{cr, swell} is the ripple current, N is the turns ratio.

Step 2: According to the structural topology and parameters of the UPQC system designed in step 1, the steady-state linear Kalman filter SSLKF based on a frequency-locked loop (FLL) filters the α component v _a and the β component v _b of the voltage to obtain The positive sequence component of the fundamental voltage of the voltage, specifically:

The alpha component v _a and beta component v _b of the voltage are filtered with a steady-state linear Kalman filter SSLKF based on a frequency-locked loop FLL to calculate the voltage fundamental components v _fa and v _fb :

Among them, ω is a constant, v _in is the power supply voltage v _sabc , and k ₁ and k ₂ are Kalman parameters.

Step 3: According to the voltage fundamental wave component generated in step 2, generate the UPQC reference signal to control the UPQC, and trigger the compensator to generate the compensation current and compensation voltage, specifically:

Step 3-1: Calculate using the fundamental voltage components v _fa and v _fb and the quadrature components qv _fa and qv _fb obtained by quadrature transformation:

和

进行逆变换得到

Step 3-2: Use the inverse of the Clark transformation matrix to calculate the fundamental positive sequence voltage

and

Inverse transform to get

和实际测得的直流电压V_DC的差值得到v_de，其差值经过PI控制器得到功率损耗分量P_loss，计算公式为：Step 3-3: Calculate the reference DC link voltage

The difference between the actual measured DC voltage V _DC is v _de , and the difference is obtained through the PI controller to obtain the power loss component P _loss , and the calculation formula is:

P _loss (t)=P _loss (t-1)+k _p {v _de (t)-v _de (t-1)}

Among them, power P _loss (t) is the active power of the supply current at time t, and kp is the droop control coefficient;

Do the dot product processing of the load voltage V _labc and the load current i _labc to obtain the average load power P _lavg , then the reference power P _ref is expressed as:

P _ref =P _lavg +P _loss

Step 3-4: Generate compensation current, specifically:

Step 3-4-1: Calculate the reference current

为实际测得的平衡正序参考电网输入电压；in,

is the actual measured balanced positive sequence reference grid input voltage;

与侧到的实际电流i_sabc做差运算后，将其差值信号送入到SPWM脉冲触发器中，在脉冲触发器中生成补偿电流控制信号控制并联补偿器中VSC换流器开关的关断；从而完成补偿；Step 3-4-2: Insert the reference current

After doing the difference operation with the actual current i _sabc from the side, the difference signal is sent to the SPWM pulse trigger, and the compensation current control signal is generated in the pulse trigger to control the turn-off of the VSC converter switch in the parallel compensator. ; to complete the compensation;

Step 3-5: Generate compensation voltage, specifically:

Step 3-5-1: Calculate the reference load voltage

为设定的峰值参考电压，

为单元模板；in,

is the set peak reference voltage,

is the unit template;

与侧到的实际负载电压v_labc做差运算后，将其差值信号送入到SPWM脉冲触发器中，在脉冲触发器中生成补偿电压控制信号控制串联补偿器中VSC换流器开关的关断，从而生成完成补偿。Step 3-5-2: Set the reference load voltage

After doing the difference operation with the actual load voltage v _labc on the side, the difference signal is sent to the SPWM pulse trigger, and the compensation voltage control signal is generated in the pulse trigger to control the closing of the VSC converter switch in the series compensator. is interrupted, thereby generating a complete compensation.

A computer-storable medium on which a computer program is stored, characterized in that, when the computer program is executed by a processor, the following steps are implemented:

Step 1: Design the structural topology of the UPQC system, and design parameters for the structural topology, including the following steps:

Step 1-1: The UPQC system includes a parallel compensator, a series compensator, an additional DC capacitor, a series-parallel interface inductor, and a ripple filter. The DC bus voltage is controlled by SSLKF-FLL algorithm, proportional and integral PI control and sinusoidal Pulse width modulation SPWM switching technology, each compensator is composed of six insulated gate bipolar transistor IGBT switches, and the series and parallel compensators are respectively connected to the grid through series-parallel interface inductors;

Step 1-2: The UPQC system parameters are as follows: Calculate the DC voltage V _DC :

Among them, m is the modulation index, and _VL is the grid voltage;

Calculate the shunt compensator phase current I _sh :

Among them, f _sw is the switching frequency, I _{cr, pp} is the current ripple, and a is the overload coefficient;

Calculate the DC capacitance C _DC :

Among them, k is the energy dynamic change coefficient, V _ph is the phase voltage, t is the time to restore the DC line voltage, and V _DC1 is the minimum DC voltage value;

Calculate the series interface inductor L _se :

Among them: I _{cr, swell} is the ripple current, N is the turns ratio.

Step 2: According to the structural topology and parameters of the UPQC system designed in step 1, the steady-state linear Kalman filter SSLKF based on the frequency-locked loop FLL filters the α component v _a and the β component v _b of the voltage to obtain the voltage base. The positive sequence component of the wave, specifically:

The alpha component v _a and beta component v _b of the voltage are filtered with a steady-state linear Kalman filter SSLKF based on a frequency-locked loop FLL to calculate the voltage fundamental components v _fa and v _fb :

Among them, ω is a constant, v _in is the power supply voltage v _sabc , and k ₁ and k ₂ are Kalman parameters.

Step 3: According to the voltage fundamental wave component generated in step 2, generate the UPQC reference signal to control the UPQC, and trigger the compensator to generate the compensation current and compensation voltage, specifically:

Step 3-1: Calculate using the fundamental voltage components v _fa and v _fb and the quadrature components qv _fa and qv _fb obtained by quadrature transformation:

和

进行逆变换得到

Step 3-2: Use the inverse of the Clark transformation matrix to calculate the fundamental positive sequence voltage

and

Inverse transform to get

和实际测得的直流电压V_DC的差值得到v_de，其差值经过PI控制器得到功率损耗分量P_loss，计算公式为：Step 3-3: Calculate the reference DC link voltage

The difference between the actual measured DC voltage V _DC is v _de , and the difference is obtained through the PI controller to obtain the power loss component P _loss , and the calculation formula is:

P _loss (t)=P _loss (t-1)+k _p {v _de (t)-v _de (t-1)}

Among them, power P _loss (t) is the active power of the supply current at time t, and kp is the droop control coefficient;

Do the dot product processing of the load voltage V _labc and the load current i _labc to obtain the average load power P _lavg , then the reference power P _ref is expressed as:

P _ref =P _lavg +P _loss

Step 3-4: Generate compensation current, specifically:

Step 3-4-1: Calculate the reference current

为实际测得的平衡正序参考电网输入电压；in,

is the actual measured balanced positive sequence reference grid input voltage;

与侧到的实际电流i_sabc做差运算后，将其差值信号送入到SPWM脉冲触发器中，在脉冲触发器中生成补偿电流控制信号控制并联补偿器中VSC换流器开关的关断；从而完成补偿；Step 3-4-2: Insert the reference current

After doing the difference operation with the actual current i _sabc from the side, the difference signal is sent to the SPWM pulse trigger, and the compensation current control signal is generated in the pulse trigger to control the turn-off of the VSC converter switch in the parallel compensator. ; to complete the compensation;

Step 3-5: Generate compensation voltage, specifically:

Step 3-5-1: Calculate the reference load voltage

为设定的峰值参考电压，

为单元模板；in,

is the set peak reference voltage,

is the unit template;

与侧到的实际负载电压v_labc做差运算后，将其差值信号送入到SPWM脉冲触发器中，在脉冲触发器中生成补偿电压控制信号控制串联补偿器中VSC换流器开关的关断，从而生成完成补偿。Step 3-5-2: Set the reference load voltage

After doing the difference operation with the actual load voltage v _labc on the side, the difference signal is sent to the SPWM pulse trigger, and the compensation voltage control signal is generated in the pulse trigger to control the closing of the VSC converter switch in the series compensator. is interrupted, thereby generating a complete compensation.

The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

Example

A UPQC power quality compensation control method based on a frequency-locked loop steady-state linear Kalman filter, characterized in that it includes the following steps:

Step 1: Combined with Figure 1, design the structural topology of the UPQC system, and design parameters for the structural topology, including the following steps:

Step 1-1: The UPQC system includes a parallel compensator, a series compensator, an additional DC capacitor, a series-parallel interface inductor, and a ripple filter. The DC bus voltage is controlled by SSLKF-FLL algorithm, proportional and integral PI control and sinusoidal Pulse width modulation SPWM switching technology, each compensator is composed of six insulated gate bipolar transistor IGBT switches, and the series and parallel compensators are respectively connected to the grid through series-parallel interface inductors;

Step 1-2: The parameters of the UPQC system are designed as follows: Calculate the DC voltage V _DC :

Among them, m is the modulation index, and _VL is the grid voltage;

Calculate the shunt compensator phase current I _sh :

Among them, f _sw is the switching frequency, I _{cr, pp} is the current ripple, and a is the overload coefficient;

Calculate the DC capacitance C _DC :

Among them, k is the energy dynamic change coefficient, V _ph is the phase voltage, t is the time to restore the DC line voltage, and V _DC1 is the minimum DC voltage value;

Calculate the series interface inductor L _se :

Among them: I _{cr, swell} is the ripple current, N is the turns ratio.

Step 2: Use the steady-state linear Kalman filter SSLKF based on the frequency-locked loop FLL to filter the α component v _a and the β component v _b of the voltage to obtain the positive sequence component of the voltage fundamental wave, specifically:

The alpha component v _a and beta component v _b of the voltage are filtered with a steady-state linear Kalman filter SSLKF based on a frequency-locked loop FLL to calculate the voltage fundamental components v _fa and v _fb :

Among them, ω is a constant, v _in is the power supply voltage v _sabc , k ₁ and k ₂ are Kalman parameters, and FIG. 2 is a block diagram of the SSLKF-based FLL filter.

For different combinations of damping factors and Kalman parameters (k ₁ , k ₂ ), the Bode plots of the in-phase signal V _fa of the SSLKF versus the supply voltage V _in are shown in Figure 3 .

From Figure 3 it can be concluded that SSLKF-FLL produces relatively small DC offset and better harmonic rejection. These properties can be attributed to the second control gain (beta axis gain) of the SSLKF-FLL. Therefore, it has greater dynamic response and damping than SOGI-FLL.

Step 3: Combined with Figure 4, according to the voltage fundamental wave component generated in Step 2, generate the UPQC reference signal to control the UPQC, and trigger the compensator to generate the compensation current and compensation voltage, specifically:

Step 3-1: Calculate using the fundamental voltage components v _fa and v _fb and the quadrature components qv _fa and qv _fb obtained by quadrature transformation:

和

进行逆变换得到

Step 3-2: Use the inverse of the Clark transformation matrix to calculate the fundamental positive sequence voltage

and

Inverse transform to get

和实际测得的直流电压V_DC的差值得到v_de，其差值经过PI控制器得到功率损耗分量P_loss，计算公式为：Step 3-3: Calculate the reference DC link voltage

The difference between the actual measured DC voltage V _DC is v _de , and the difference is obtained through the PI controller to obtain the power loss component P _loss , and the calculation formula is:

P _loss (t)=P _loss (t-1)+k _p {v _de (t)-v _de (t-1)}

和实际测得的直流电压V_DC的差值；Among them, the power P _loss (t) is the active power of the supply current at time t, P _loss not only includes all switching losses, but also the loss of the UPQC device, kp is the droop control coefficient, and vd _e (t) is the reference at time t. DC link voltage

The difference between the actual measured DC voltage V _DC ;

Do the dot product processing of the load voltage V _labc and the load current i _labc to obtain the average load power P _lavg , then the reference power P _ref is expressed as:

P _ref =P _lavg +P _loss

Step 3-4: Generate compensation current, specifically:

Step 3-4-1: Calculate the reference current

为实际测得的平衡正序参考电网输入电压；in,

is the actual measured balanced positive sequence reference grid input voltage;

与侧到的实际电流i_sabc做差运算后，将其差值信号送入到SPWM脉冲触发器中，在脉冲触发器中生成补偿电流控制信号控制并联补偿器中VSC换流器开关的关断；从而完成补偿；Step 3-4-2: Insert the reference current

After doing the difference operation with the actual current i _sabc from the side, the difference signal is sent to the SPWM pulse trigger, and the compensation current control signal is generated in the pulse trigger to control the turn-off of the VSC converter switch in the parallel compensator. ; to complete the compensation;

Step 3-5: Generate compensation voltage, specifically:

Step 3-5-1: Calculate the reference load voltage

为设定的峰值参考电压，

为单元模板；in,

is the set peak reference voltage,

is the unit template;

与侧到的实际负载电压v_labc做差运算后，将其差值信号送入到SPWM脉冲触发器中，在脉冲触发器中生成补偿电压控制信号控制串联补偿器中VSC换流器开关的关断，从而生成完成补偿。Step 3-5-2: Set the reference load voltage

After doing the difference operation with the actual load voltage v _labc on the side, the difference signal is sent to the SPWM pulse trigger, and the compensation voltage control signal is generated in the pulse trigger to control the closing of the VSC converter switch in the series compensator. is interrupted, thereby generating a complete compensation.

The proposed FLL control algorithm based on SSLKF is simulated and verified on the UPQC system, and the model is analyzed by using the Matlab/Simulink software platform. The sampling time is 10μs, and the discrete domain is obtained by 5 ode solvers. The following table is the system parameters and three-phase UPQC detailed design value parameters:

(1) Application of SSLKF-FLL control and parallel converter in UPQC based on dynamic characteristics

The dynamic behavior of UPQC under unbalanced load and current distortion is shown in Figure 5, and the compensation currents i _coma , i _comb , and i _comc of the parallel compensator are shown in Figure 5, indicating that the reactive power compensation for the power supply current is orderly Yes, the DC bus voltage is within the allowable range of 3% tolerance, the DC voltage adapts to its 700 volt voltage level and is not affected by 16 volt voltage fluctuations.

Due to the use of low-order filters in the DC link voltage and active average power calculations, there is an imperceptible shift of one cycle in the waveform. _The load voltage v1 curve remains at its desired level regardless of the load imbalance.

一致；同样，电源电压v_s、负载电压v₁和电源电流i_s彼此同相。由此可知，UPQC的并联补偿器在负载动态过程中起到功率因数校正的作用。The waveforms show that the three-phase supply current i _s is almost the same as the reference supply current due to the presence of the current injected by the shunt-type compensator

Consistent; likewise, the supply voltage v _s , the load voltage v ₁ and the supply current _is are in phase with each other. It can be seen that the parallel compensator of UPQC plays the role of power factor correction in the dynamic process of the load.

The results show that the "c-phase" load is connected from 0.5 seconds, and the changes of each phase compensation current i _coma , i _comb , i _comc are shown. At this point, it can be seen that the shunt type compensator provides the necessary compensation current in all three phases with the required magnitude to maintain the sinusoidal supply current before and after the unbalanced load condition.

(2) Steady-state and dynamic responses of UPQC using SSLKF-FLL method

The steady-state and dynamic responses of UPQC controlled by _SSLKF -FLL are shown in Figure 6. The waveforms in the figure are the three-phase supply voltage vs, supply current is, load voltage v _l , load current _{i l} , DC voltage V _DC , series connection Compensator compensation voltages v _inja , v _injb , v _injc , parallel compensator compensation currents i _coma , i _comb , i _comc .

Between 0.5-0.56s, a voltage sag of the order of 0.70pu can be seen; at 0.6-0.66s, the voltage expands to a magnitude of 1.30pu; at 0.5-0.56s, the supply voltage applied to the supply voltage v _s changes from -11th harmonic to +13th harmonic with amplitudes 1/15 and 1/20 of the fundamental voltage;

At 0.5-0.6 seconds, when "c-phase" is disconnected from the supply line, the load is adjusted from three-phase to two-phase, which results in an unbalanced load condition in the network. From the results, the unbalanced load is compensated by the parallel compensator part of the _UPQC , it balances the sinusoidal supply current is and makes it in phase with the supply voltage _vs ;

The UPQC series compensator acts as compensation for voltage sag/swell and distortion, and produces a distortion-free load voltage v _l , as shown in Figure 6. It also compensates for load voltage _vl issues from all PQ disturbances and remains equal to the desired magnitude. Therefore, it maintains a constant voltage at the point of common coupling on the load side. At the same time, the parallel compensator maintains a balanced supply current and uniformly adjusts the power factor. The SSLKF-FLL control algorithm keeps the DC link voltage close to the reference level under the above-mentioned PQ disturbance. The harmonic spectrum of supply voltage v _s , supply current is , load voltage v _l and load current _{i l} is shown in the table below:

The total harmonic distortion (THD) of the harmonic load is 63.83% of the total harmonic load. Likewise, the THD of the load voltage is 3.16%, also filtered from the THD of the supply voltage of 16.85%. Harmonic levels can be limited to less than 5% according to the IEEE standard for SSLKF-FLL control of the UPQC system.

It can be seen from the above that the present invention can improve the power quality of the power grid under nonlinear load, improve the stability and robustness of the power grid, and enhance the control effect and dynamic response performance of the UPQC system.

Claims (7)

1. a UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering, is characterized in that, comprises the steps: Step 1: construct the structural topology of the UPQC system, and determine the parameters for the structural topology; Step 2: Use the steady-state linear Kalman filter SSLKF based on the frequency-locked loop FLL to filter the α component v _a and the β component v _b of the voltage to obtain the positive sequence component of the voltage fundamental wave; Step 3: According to the voltage fundamental wave component generated in step 2, generate the UPQC reference signal to control the UPQC, trigger the compensator to generate the compensation current and the compensation voltage, and complete the compensation of the power quality. 2. the UPQC power quality compensation control method based on the frequency-locked loop steady-state linear Kalman filter according to claim 1, is characterized in that, in described step 1, construct the structure of UPQC system, and according to determining the parameter specific for structure topology Contains the following steps: Step 1-1: Construct the structural topology of the UPQC system; the UPQC system includes a parallel compensator, a series compensator, an additional DC capacitor, a series-parallel interface inductor and a ripple filter, and the DC bus voltage control adopts the SSLKF-FLL algorithm, Using proportional integral PI control and sinusoidal pulse width modulation SPWM switching technology, each compensator is composed of six insulated gate bipolar transistor IGBT switches, and the series and parallel compensators are respectively connected to the grid through series-parallel interface inductors; Step 1-2: Determine parameters; UPQC system parameters are as follows: DC voltage V _DC :

Among them, m is the modulation index, and _VL is the grid voltage; Parallel compensator phase current I _sh :

Among them, f _sw is the switching frequency, I _{cr, pp} is the current ripple, and a is the overload coefficient; DC capacitance C _DC :

Among them, k is the energy dynamic change coefficient, V _ph is the phase voltage, t is the time to restore the DC line voltage, and V _DC1 is the minimum DC voltage value; Series interface inductor L _se :

Among them: I _{cr, swell} is the ripple current, N is the turns ratio. 3. the UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering according to claim 1, is characterized in that, in described step 2, according to design structure topology and parameter, calculate voltage fundamental wave component is specifically: : The alpha component v _a and beta component v _b of the voltage are filtered with a steady-state linear Kalman filter SSLKF based on a frequency-locked loop FLL to calculate the voltage fundamental components v _fa and v _fb :

Among them, ω is a constant, v _in is the power supply voltage v _sabc , and k ₁ and k ₂ are Kalman parameters. 4. the UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering according to claim 1, is characterized in that, in described step 3, according to the voltage fundamental wave component generated in step 2, generate UPQC reference The signal to control UPQC is as follows: Step 3-1: Calculate using the fundamental voltage components v _fa and v _fb and the quadrature components qv _fa and qv _fb obtained by quadrature transformation:

Step 3-2: Use the inverse of the Clark transformation matrix to calculate the fundamental positive sequence voltage

and

Inverse transform to get

Step 3-3: Calculate the reference power _Pref ; first calculate the reference DC link voltage

The difference between the actual measured DC voltage V _DC is v _de , and the difference is obtained through the PI controller to obtain the power loss component P _loss , and the calculation formula is: P _loss (t)=P _loss (t-1)+k _p {v _de (t)-v _de (t-1)} Among them, power P _loss (t) is the active power of the supply current at time t, and kp is the droop control coefficient; Do the dot product processing of the load voltage V _labc and the load current i _labc to obtain the average load power P _lavg , then the reference power P _ref is expressed as: P _ref =P _lavg +P _loss Step 3-4: Generate compensation current, specifically: Step 3-4-1: Calculate the reference current

in,

is the actual measured balanced positive sequence reference grid input voltage; Step 3-4-2: Insert the reference current

After doing the difference operation with the actual current i _sabc from the side, the difference signal is sent to the SPWM pulse trigger, and the compensation current control signal is generated in the pulse trigger to control the turn-off of the VSC converter switch in the parallel compensator. ; to complete the compensation; Step 3-5: Generate compensation voltage, specifically: Step 3-5-1: Calculate the reference load voltage

in,

is the set peak reference voltage,

is the unit template; Step 3-5-2: Set the reference load voltage

After doing the difference operation with the actual load voltage v _labc on the side, the difference signal is sent to the SPWM pulse trigger, and the compensation voltage control signal is generated in the pulse trigger to control the closing of the VSC converter switch in the series compensator. is interrupted, thereby generating a complete compensation. 5. a UPQC power quality compensation control system based on frequency-locked loop steady-state linear Kalman filtering, is characterized in that, comprises following module: Structural and parameter design module: used to design the structural topology of the UPQC system, and design parameters for the structural topology; Filtering module: used to filter the α component v _a and the β component v _b of the voltage to obtain the positive sequence component of the voltage fundamental wave; Compensator trigger module: It is used to generate the UPQC reference signal to control the UPQC by using the voltage fundamental wave component generated by the filter module, and trigger the compensator to generate compensation current and compensation voltage. 6. A computer device comprising a memory, a processor and a computer program stored on the memory and running on the processor, wherein the processor implements any of claims 1-4 when the processor executes the computer program. A step of the method. 7. A computer-storable medium on which a computer program is stored, wherein the computer program implements the steps of the method according to any one of claims 1-4 when the computer program is executed by a processor.

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