CN112685754B - Unlocking circuit and unlocking method of debugging interface - Google Patents
Unlocking circuit and unlocking method of debugging interface Download PDFInfo
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Abstract
The embodiment of the invention provides an unlocking circuit and an unlocking method for a debugging interface, which can solve the problem that the unlocking method for the debugging interface is easy to crack by voltage attack in the prior art, thereby improving the reliability of the debugging interface. The circuit comprises: the first verification module is used for executing at least two verification steps corresponding to an unlocking program of the debugging interface, and writing a first secret key into a preset storage space when each verification step is successful in verification; the second verification module is used for reading at least two first keys from the preset storage space and matching the at least two first keys with at least two second keys stored in the second verification module in advance one by one; and if the matching results are the same, controlling the debugging interface to be unlocked.
Description
Technical Field
The invention relates to the technical field of chip security, in particular to an unlocking circuit and an unlocking method of a debugging interface.
Background
Since various kinds of confidential data are usually stored in a chip, in order to protect the confidential data stored in the chip, an encryption algorithm is often provided to protect the confidential data from being stolen by a hacker. However, in order to facilitate debugging of the chip system by a developer, a debugging interface is usually provided in the chip, and most of confidential data in the chip can be acquired through the debugging interface. Thus, protection against debug interfaces is an important component of chip security protection.
In the prior art, when the debug interface needs to be unlocked, a plurality of verification steps corresponding to the unlocking program can be executed. When all the verification steps pass verification, the step is skipped to an unlocking step, so that the debugging interface is controlled to unlock. However, the verification mode is broken by voltage attack, that is, by rapidly changing the input voltage on the chip, voltage burrs are generated, so that the transistor inside the chip enters an error state, and then part of verification steps corresponding to the unlocking program may be skipped and directly enter the final unlocking step, thereby completing the unlocking of the debugging interface.
Therefore, the unlocking method of the debugging interface in the prior art has the risk of being cracked by voltage attack.
Disclosure of Invention
The embodiment of the invention provides an unlocking circuit and an unlocking method for a debugging interface, which can solve the problem that the unlocking method for the debugging interface is easy to crack by voltage attack in the prior art, thereby improving the reliability of the debugging interface.
In a first aspect, an embodiment of the present invention provides an unlock circuit of a debug interface, where the unlock circuit is applied to a chip, and the circuit includes:
The first verification module is used for executing at least two verification steps corresponding to an unlocking program of the debugging interface, and writing a first secret key into a preset storage space when each verification step is successful in verification;
The second verification module is used for reading at least two first keys from the preset storage space and matching the at least two first keys with at least two second keys stored in the second verification module in advance one by one; and if the matching results are the same, controlling the debugging interface to be unlocked.
In the embodiment of the present invention, the verification steps corresponding to the unlocking program for the debug interface executed in the first verification module may be considered to include at least two verification steps, and then the first key may be written into the preset storage space when each verification step is successful. The first key may be considered as a pre-agreed fixed value. The second verification module can acquire at least two first keys from a preset storage space, and match the at least two first keys with at least two second keys stored in the second verification module. The second key may be considered a fixed value agreed in advance and identical to the first key. If the matching results are the same, the chip can be considered not to be attacked by voltage in the unlocking process of the debugging interface, namely, any verification step is not skipped due to the voltage attack, and the second verification module can control the debugging interface to unlock. The circuit matches the first key written in each verification step with the corresponding second key when the verification is successful, and the debugging interface is unlocked only when all verification steps are successful, so that the problem of misunderstanding of the locking of the debugging interface caused by voltage attack is avoided, and the reliability of the debugging interface is improved.
Optionally, the second verification module is further configured to: when any first key is not matched with the corresponding second key, the debugging interface is controlled to not respond to any unlocking operation.
In the embodiment of the invention, if any first key is not matched with the corresponding second key, part of verification steps can be considered to be skipped in the unlocking process of the debug interface, namely the debug interface is attacked by voltage, and the second verification module can control the debug interface not to respond to any unlocking operation, so that the data security in the chip is ensured.
Optionally, the second verification module includes:
each matching component of the at least two matching components is used for acquiring a first key written in the corresponding verification step, matching the first key with a second key stored in the matching component, and outputting a level signal corresponding to a matching result;
and the AND gate is respectively connected with the at least two matching components, and is used for receiving the level signal output by each matching component and performing AND operation on the received at least two level signals; and when the result of the AND operation is high level, determining that the matching result of the first key written in each verification step and the corresponding second key is the same.
In the embodiment of the invention, the number of the matching components can be set according to the number of the verification steps, namely the number of the matching components is equal to the number of the verification steps, so that the matching result of the first key written in each verification step and the corresponding second key can be converted into the level signal through the matching components, and then the level signals output by the matching components are subjected to AND operation through the AND gate. As long as the result of the and operation is high, it may be indicated that the matching result of the first key written by each verification step and the corresponding second key is the same. The chip can be judged not to be attacked by voltage in the process of unlocking the test interface through a simple circuit structure.
Optionally, the and gate is further configured to: when the result of the AND operation is low level, the matching result of the first key written in any verification step and the corresponding second key is determined to be different.
In the embodiment of the present invention, as long as the result of the and operation is a low level, it may indicate that there is a matching result between the first key written in the verification step and the corresponding second key. That is, part of the verification step is skipped due to voltage attack. That is, the chip can be judged to have been attacked by the voltage in the process of unlocking the test interface by a simple circuit structure.
Optionally, each matching component includes:
A nonvolatile memory for storing the second key;
the comparator is used for respectively acquiring the first key and the second key and comparing the first key with the second key, wherein when the first key and the second key are the same, the comparator outputs a high-level signal; the comparator outputs a low level signal when the first key is different from the second key.
In the embodiment of the invention, the nonvolatile memory can realize long-term storage of the second secret key, namely, the second secret key still exists under the condition of power failure of the chip. The comparator can acquire the first key written in each verification step and the second key stored in advance, compare the first key with the second key, and convert the comparison result of the first key and the second key into corresponding level signals, so that whether the debugging interface is unlocked or not can be controlled according to the comparison result of the first key and the second key.
In a second aspect, an embodiment of the present invention provides a chip, including: the embodiment of the first aspect of the invention provides a circuit.
In a third aspect, an embodiment of the present invention provides an unlocking method for a debug interface, which is applied to a chip including the debug interface, where the method includes:
Executing at least two verification steps corresponding to an unlocking program of the debugging interface, and writing a first secret key into a preset storage space when each verification step is successful in verification;
Reading at least two first keys from the preset storage space, and matching the at least two first keys with at least two second keys stored in advance one by one;
and if the matching results are the same, controlling the debugging interface to be unlocked.
Optionally, the method further comprises:
And if any first key is not matched with the corresponding second key, controlling the debugging interface not to respond any unlocking operation.
Optionally, reading at least two first keys from the preset storage space, and performing one-to-one matching between the at least two first keys and at least two second keys stored in advance includes:
acquiring a first key written in each verification step, matching the first key with a stored second key, and outputting a level signal corresponding to a matching result;
performing AND operation on at least two level signals;
when the result of the AND operation is high, the matching result of the first key written in each verification step and the corresponding second key is the same.
Optionally, the method further comprises:
If the result of the AND operation is low level, the matching result of the first key written in any verification step and the corresponding second key is determined to be different.
Optionally, obtaining the first key written in each verification step, matching with the stored second key, and outputting a level signal corresponding to the matching result includes:
Outputting a high-level signal if the first key is the same as the second key; or alternatively
And outputting a low-level signal if the first key is different from the second key.
Drawings
Fig. 1 is a schematic structural diagram of an unlocking circuit of a debug interface according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a second verification module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a matching component according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a debugging interface unlocking process according to an embodiment of the present invention;
Fig. 5 is a flowchart of an unlocking method of a debug interface according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent.
In the prior art, the test interface is unlocked by executing a series of verification steps corresponding to the unlocking program, but the verification mode is easy to be attacked by voltage. That is, under multiple voltage attacks, some of the above series of verification steps may be skipped, so that the step of unlocking the debug interface is directly skipped. That is, the unlocking method of the debug interface in the prior art has the risk of being cracked by voltage attack.
In view of this, in the embodiment of the present invention, an unlocking circuit for a debug interface is provided, where the first key written in each verification step is matched with the corresponding second key when verification is successful, and when all verification steps are successful, the debug interface is unlocked, so that the problem of misunderstanding of the lock of the debug interface caused by voltage attack is avoided, and the reliability of the debug interface is improved.
The following describes in detail an unlocking circuit of a debug interface provided by an embodiment of the present invention with reference to the accompanying drawings. Referring to fig. 1, an unlocking circuit of a debug interface provided in an embodiment of the present invention includes:
The first verification module 10 is configured to execute at least two verification steps corresponding to an unlocking program for the debug interface, and write a first key into a preset storage space when each verification step is successful;
The second verification module 20 is configured to read at least two first keys from the preset storage space, and match the at least two first keys with at least two second keys stored in advance by the second verification module; and if the matching results are the same, controlling the debugging interface to be unlocked.
In the embodiment of the present invention, the first verification module 10 may be considered to store an unlocking program for unlocking the debug interface, and in order to improve the reliability of the debug interface, the unlocking program in the prior art generally corresponds to at least two verification steps, for example, a first verification step and a second verification step.
When a developer needs to debug a program for implementing related functions in a chip based on a debug interface or needs to read confidential data stored in the chip, then the debug interface needs to be unlocked. At this time, the first authentication module 10 may perform at least two authentication steps as described above, and write the first key into the preset storage space after each authentication step is successfully authenticated. I.e. writing at least two first keys to a preset memory space. Otherwise, if a certain verification step is not verified successfully or skipped due to voltage attack, the verification step will not write the first key into the preset memory space. That is, in the preset storage space, the first key corresponding to the verification step is null. It should be understood that the first key written to the preset storage space after each verification step is successfully verified may be considered as a predetermined fixed value, and the first keys written by different verification steps may be the same or different, which is not particularly limited herein.
The second verification module 20 may consider that at least two second keys corresponding to at least two first keys one to one are stored therein, and each second key has the same value as the corresponding first key. Then, in the process of unlocking the debug interface, as long as the second verification module 20 determines that the first key written in each verification step is the same as the corresponding second key, it indicates that at least two verification steps corresponding to the unlocking program are verified and both verification steps are successful, and at this time, the second verification module 20 can control the debug interface to unlock. Otherwise, if the second verification module 20 determines that any first key is not matched with the corresponding second key, it may be considered that part of the verification steps are skipped in the process of unlocking the debug interface, that is, the debug interface is attacked by voltage, and at this time, the second verification module 20 may control the debug interface not to respond to any unlocking operation, so as to ensure the data security inside the chip. That is, the unlocking circuit of the debug interface provided by the embodiment of the invention can effectively distinguish whether the current unlocking process for the debug interface is legal or not, for example, the unlocking process which sequentially verifies at least two verification steps corresponding to the unlocking program is considered legal, and the unlocking process which is skipped in part of at least two verification steps corresponding to the unlocking program is considered illegal through voltage attack, so that the reliability of the debug interface is improved.
The specific implementation structure of the functional module related in the unlocking circuit is described in detail below with reference to the accompanying drawings.
Based on the above description of the functional implementation of the second verification module 20, the second verification module 20 provided in the embodiment of the present invention may be specifically implemented by the following subdivision devices, please refer to fig. 2, which may specifically include: at least two matching components 201 and an and gate 202.
The matching result of the first key written in any verification step and the corresponding second key may be the same or different. For example, if the first verification step is successful, the first key written in the first verification step must be identical to the second key; if the first verification step is skipped due to voltage attack, the first key written by the first verification step is null and must not be identical to the corresponding second key. However, whether the matching result of the first key and the corresponding second key is the same or not, the matching result is not an electrical signal, and thus the method cannot be directly used for controlling whether the debug interface is unlocked or not. Therefore, in the embodiment of the invention, the matching result of the first key written in each verification step and the corresponding second key can be converted into the level signal, so that whether the test interface is unlocked or not is determined together based on a plurality of level signals.
As a possible implementation manner, the number of matching components may be set according to the number of verification steps corresponding to the unlocking procedure, that is, the number of matching components is equal, and then each matching component 201 may acquire the first key written in the corresponding verification step, and match the acquired first key with the second key stored in itself, so as to output a level signal corresponding to the matching result. The level signals output by the at least two matching components 201 are then anded by the and gate 202, i.e., anded for the at least two level signals, to determine whether to unlock the debug interface according to the result of the anded operation.
Specifically, when the result of the and operation is at the high level, it may be indicated that the matching result of the first key written in each verification step and the corresponding second key is the same. That is, it may be determined that the chip is not attacked by the voltage during the process of unlocking the debug interface, and the high level control debug interface output by the and gate 202 may be directly used for unlocking.
Otherwise, when the result of the AND operation is low, it may indicate that there is a different matching result between the first key written in any verification step and the corresponding second key. That is, it may be determined that a portion of the verification step is skipped due to the voltage attack, at which time the debug interface may be directly controlled by the low level output from the and gate 202 without responding to any unlock operation.
Based on the above description of the functional implementation of the matching component 201, the matching component 201 provided in the embodiment of the present invention may be implemented by the following subdivision devices, please refer to fig. 3, which may specifically include: a nonvolatile memory 2011 and a comparator 2012.
It is contemplated that for any one verification step, the first key written is not the same when the verification step is successful or the verification step is skipped. For example, when the verification step is successful, the written first key may be regarded as a fixed value agreed in advance; and when this verification step is skipped, the first key written may be considered a null value, i.e. the first key is changed in different situations. In order to match the first key with the corresponding second key, it is necessary to ensure that the second key must be kept unchanged, that is, it is necessary to determine the result of the matching of the first key with the second key based on the second key while ensuring that the second key does not change.
As a possible implementation, the second key may be stored in the non-volatile memory 2011, i.e. in case of a power failure of the chip, the second key stored in the non-volatile memory 2011 is still present. When it is required to determine whether the first key and the second key are the same, the comparator 2012 may obtain the first key written in each verification step and the second key stored in advance, compare the first key with the second key, and convert the comparison result of the first key and the second key into corresponding level signals, so as to control whether the test interface is unlocked according to the comparison result of the first key and the second key.
For example, when the first key is the same as the second key, the comparator 2012 outputs a high level signal; when the first key is different from the second key, the comparator 2012 outputs a low level signal.
Referring to fig. 4, the following describes the unlocking process of the debug interface in detail.
The unlocking program of the debug interface can be considered to correspond to three verification steps, namely a verification step 1, a verification step 2 and a verification step 3. When the debugging interface of the chip is required to be unlocked, the three verification steps are sequentially executed. The verification process is as follows: if the verification in the verification step 1 fails, directly exiting the current unlocking program; if the verification in the verification step 1 is successful, writing the first key into the preset storage space, and continuing to execute the verification step 2. If the verification in the verification step 2 fails, directly exiting the current unlocking program; if the verification in the verification step 2 is successful, the first key is written into the preset storage space, and the verification step 3 is continuously executed. If the verification in the verification step 3 fails, directly exiting the current unlocking program; if the verification step 3 is successful, writing a first key into the preset storage space, and entering an unlocking step (in the prior art, after the verification step 1, the verification step 2 and the verification step 3 are successful and enter the unlocking step, a high-level signal is output, and the enabling end of the debug interface is set to be 1, namely the debug interface is controlled to be unlocked). Meanwhile, three matching components 201 are further provided, and each matching component 201 is configured to obtain a first key from a preset storage space, match the obtained first key with a second key stored in the matching component, and convert a matching result into a corresponding level signal. For example, if the first key is the same as the second key, a high level signal is output; if the first key is different from the second key, a low level signal is output. The input of the and gate 202 is used for receiving the level signal output by each matching component 201 and the level signal output in the unlocking step.
When the verification step 1, the verification step 2 and the verification step 3 pass through, each matching component 201 outputs a high-level signal, and the unlocking step also outputs a high-level signal, and after the and operation, the output of the and gate 202 is a high-level signal, so that the high-level signal output by the and gate 202 can control the enabling end of the debug interface, and the debug interface is unlocked.
If any one of the verification steps 1,2 and 3 is skipped due to voltage attack, for example, the skipped verification step is directly skipped to step 2 or directly skipped to the unlock step, the skipped verification step may be considered to be successful, but the skipped verification step will not write the first key into the preset memory space, that is, the first key corresponding to the skipped verification step is null, then the first key obtained by the matching component 201 corresponding to the skipped verification step from the preset memory space is null, and the second key stored in the matching component 201 is not null, so that the first key is different from the second key, then the matching component 201 outputs a low level signal, thereby causing the and gate 202 to output a low level signal, so that the low level signal output by the and gate 202 can control the enabling end of the debug interface, and the debug interface will not respond to any unlock operation.
Based on the same inventive concept, the embodiment of the invention provides a chip, which comprises the unlocking circuit of the debugging interface provided by any embodiment of the invention. The chip can be applied to various terminals: smart phones (e.g., android phones, IOS phones), tablet computers, notebook computers, palm computers, wearable smart devices, and other electronic devices. The specific type of terminal is not particularly limited here.
Based on the same inventive concept, please refer to fig. 5, an embodiment of the present invention provides an unlocking method of a debug interface, which is applied to a chip including the debug interface, and the flow of the method is described as follows:
Step 301: executing at least two verification steps corresponding to an unlocking program of the debugging interface, and writing a first secret key into a preset storage space when each verification step is successful in verification;
step 302: reading at least two first keys from a preset storage space, and matching the at least two first keys with at least two second keys stored in advance one by one;
step 303: and if the matching results are the same, controlling the debugging interface to unlock.
Optionally, the method further comprises:
and if any first key is not matched with the corresponding second key, controlling the debugging interface not to respond any unlocking operation.
Optionally, reading at least two first keys from a preset storage space, and matching the at least two first keys with at least two second keys stored in advance one by one includes:
acquiring a first key written in each verification step, matching the first key with a stored second key, and outputting a level signal corresponding to a matching result;
performing AND operation on at least two level signals;
when the result of the AND operation is high, the matching result of the first key written in each verification step and the corresponding second key is the same.
Optionally, the method further comprises:
If the result of the AND operation is low level, the matching result of the first key written in any verification step and the corresponding second key is determined to be different.
Optionally, obtaining the first key written in each verification step, matching with the stored second key, and outputting a level signal corresponding to the matching result includes:
if the first key is the same as the second key, outputting a high-level signal; or alternatively
If the first key is different from the second key, a low level signal is output.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (6)
1. An unlock circuit for a debug interface, the unlock circuit being applied to a chip, the circuit comprising:
The first verification module is used for executing at least two verification steps corresponding to an unlocking program of the debugging interface, and writing a first secret key into a preset storage space when each verification step is successful in verification;
The second verification module is used for reading at least two first keys from the preset storage space and matching the at least two first keys with at least two second keys stored in the second verification module in advance one by one; if the matching results are the same, controlling the debugging interface to unlock;
The second verification module is further configured to: when any first key is not matched with the corresponding second key, controlling the debugging interface not to respond any unlocking operation;
The second verification module includes:
each matching component of the at least two matching components is used for acquiring a first key written in the corresponding verification step, matching the first key with a second key stored in the matching component, and outputting a level signal corresponding to a matching result;
and the AND gate is respectively connected with the at least two matching components, and is used for receiving the level signal output by each matching component and performing AND operation on the received at least two level signals; and when the result of the AND operation is high level, determining that the matching result of the first key written in each verification step and the corresponding second key is the same.
2. The circuit of claim 1, wherein the and gate is further to: when the result of the AND operation is low level, the matching result of the first key written in any verification step and the corresponding second key is determined to be different.
3. The circuit of claim 1, wherein each matching component comprises:
A nonvolatile memory for storing the second key;
the comparator is used for respectively acquiring the first key and the second key and comparing the first key with the second key, wherein when the first key and the second key are the same, the comparator outputs a high-level signal; the comparator outputs a low level signal when the first key is different from the second key.
4. A chip comprising the circuit of any one of claims 1-3.
5. An unlocking method of a debug interface, which is applied to a chip comprising the debug interface, the method comprising:
Executing at least two verification steps corresponding to an unlocking program of the debugging interface, and writing a first secret key into a preset storage space when each verification step is successful in verification;
Reading at least two first keys from the preset storage space, and matching the at least two first keys with at least two second keys stored in advance one by one;
if the matching results are the same, controlling the debugging interface to unlock;
the method further comprises the steps of:
If any first key is determined to be unmatched with the corresponding second key, controlling the debugging interface not to respond any unlocking operation;
Reading at least two first keys from the preset storage space, and matching the at least two first keys with at least two second keys stored in advance one by one comprises:
acquiring a first key written in each verification step, matching the first key with a stored second key, and outputting a level signal corresponding to a matching result;
performing AND operation on at least two level signals;
when the result of the AND operation is high, the matching result of the first key written in each verification step and the corresponding second key is the same.
6. The method as recited in claim 5, further comprising:
If the result of the AND operation is low level, the matching result of the first key written in any verification step and the corresponding second key is determined to be different.
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