CN112653434A - Sequential control low-power consumption common-mode feedback pre-amplifying circuit and comparator - Google Patents
Sequential control low-power consumption common-mode feedback pre-amplifying circuit and comparator Download PDFInfo
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- CN112653434A CN112653434A CN202011525328.7A CN202011525328A CN112653434A CN 112653434 A CN112653434 A CN 112653434A CN 202011525328 A CN202011525328 A CN 202011525328A CN 112653434 A CN112653434 A CN 112653434A
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Abstract
The application discloses sequential control's low-power consumption common mode feedback preamplifier circuit and comparator belongs to integrated circuit technical field. The method mainly comprises the following steps: the common-mode feedback unit comprises a first transistor, a second transistor and a capacitor, the clock control unit comprises a first clock control switch, a second clock control switch, a third clock control switch, a fourth clock control switch, a fifth clock control switch, a sixth clock control switch, a seventh clock control switch, an eighth clock control switch and a ninth clock control switch.
Description
Technical Field
The present disclosure relates to integrated circuits, and particularly to a timing controlled low power consumption common mode feedback pre-amplifying circuit and a comparator.
Background
In integrated circuits, a combined structure of a pre-amplification circuit and a latch is often used in an ADC (digital-to-analog conversion) comparator structure.
In the prior art, the preamplifier circuit of the integrated circuit is a pseudo-differential amplifier formed by two CMOS inverters. In the pseudo differential amplifier, when the common mode voltage input by the inverting input end and the non-inverting input end of the pseudo differential amplifier is close to the jump voltage, the NMOS transistor and the PMOS transistor have the same amplification performance at the time. When the inverting input terminal is short-circuited with the non-inverting input terminal, the pseudo-differential amplifier operates at its voltage jump point. However, the pseudo-differential amplifier generates a high common-mode gain, and the high common-mode gain has a certain influence on the value of the signal-to-noise ratio in the comparator.
Disclosure of Invention
The application mainly provides a time sequence controlled low-power consumption common mode feedback pre-amplifying circuit and a comparator, aiming at the problem that a high common mode gain generated by a pre-amplifier in a pre-amplifying circuit with a comparator structure in the prior art can generate certain influence on a signal-to-noise ratio value in the comparator.
In order to achieve the above object, the present application adopts a technical solution that: the utility model provides a timing control's low-power consumption common mode feedback preamplifier circuit is provided, it includes: the preamplifier, the clock control unit and the common-mode feedback unit, the common-mode feedback unit comprises a first transistor, a second transistor and a capacitor, the clock control unit comprises a first clock control switch, a second clock control switch, a third clock control switch, a fourth clock control switch, a fifth clock control switch, a sixth clock control switch, a seventh clock control switch, an eighth clock control switch and a ninth clock control switch, wherein the reverse phase input end of the preamplifier is interconnected with the in-phase output end of the preamplifier through the first clock control switch, the in-phase output end of the preamplifier is interconnected with the common-mode voltage output end of the common-mode feedback unit through the second clock control switch, the common-mode voltage output end of the common-mode feedback unit is interconnected with the reverse phase output end of the preamplifier through the fourth clock control switch, and the common-mode voltage output end of the common-mode feedback unit is interconnected with the capacitor through the third clock control switch, the non-inverting input end of the preamplifier is connected with the inverting output end of the preamplifier through a fifth clock control switch, the common-mode voltage output end of the common-mode feedback unit is connected with the grid electrode of the first transistor through a sixth clock control switch, an external power supply is connected with the grid electrode of the first transistor through a seventh clock control switch, the common-mode voltage output end of the common-mode feedback unit is connected with the grid electrode of the second transistor through an eighth clock control switch, and the grid electrode of the second transistor is grounded through a ninth clock control switch.
Another technical scheme adopted by the application is as follows: the comparator of the low-power consumption common mode feedback pre-amplifying circuit based on the time sequence control is provided, and comprises: the circuit comprises a pre-amplifier, a clock control unit, a common-mode feedback unit, a latch and a low-power consumption common-mode feedback pre-amplification circuit based on time sequence control of the pre-amplifier, the clock control unit and the common-mode feedback unit in the first scheme, wherein the in-phase output end of the pre-amplifier in the time sequence control low-power consumption common-mode feedback pre-amplification circuit is connected with the in-phase input end of the latch, and the reverse-phase output end of the pre-amplifier in the time sequence control low-power consumption common-mode feedback pre-amplification.
The technical scheme of the application can reach the beneficial effects that: the application designs a time sequence controlled low-power consumption common-mode feedback pre-amplifying circuit and a comparator. By providing a simple common mode feedback circuit with time sequence, the common mode gain is effectively reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic diagram of an embodiment of a timing controlled common mode feedback pre-amplifier circuit;
FIG. 2 is a schematic diagram of a pseudo-differential amplifier in one embodiment of the present application timing controlled low power common mode feedback pre-amplifier circuit;
FIG. 3 is a schematic diagram of a preamplifier in one embodiment of the present application timing controlled low power common mode feedback preamplification circuit;
FIG. 4 is a schematic diagram of a preamplifier-based clock control unit in an embodiment of the timing controlled common mode feedback pre-amplifier circuit of the present application;
FIG. 5 is a schematic diagram of a pre-amplifier circuit according to an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating the variation of clock signals in each operation stage of the low power consumption common mode feedback pre-amplifying circuit for timing control according to the present application;
FIG. 7 is a diagram illustrating the components of an embodiment of a timing controlled common mode feedback pre-amplifier circuit with low power consumption according to the present invention;
FIG. 8 is a schematic diagram of a comparator of a low power consumption common mode feedback pre-amplifying circuit based on the timing control of the present application;
the reference numbers in the figures are as follows: m1-a first transistor, M2-a second transistor, M3-a third transistor, M4-a fourth transistor, M5-a fifth transistor, M6-a sixth transistor, C1-a first clocked switch, C2-a second clocked switch, C3-a third clocked switch, C4-a fourth clocked switch, C5-a fifth clocked switch, C6-a sixth clocked switch, C7-a seventh clocked switch, C8-an eighth clocked switch, C9-a ninth clocked switch, Vin, p 1-a non-inverting input of a pseudo-differential amplifier, Vout, n 1-an inverting output of the pseudo-differential amplifier, Vin, n 1-an inverting input of the pseudo-differential amplifier, Vout, p 1-an in-phase output of the pseudo-differential amplifier, Vin, a non-inverting input of the p-preamplifier, vout, n-the inverting output of the preamplifier, Vin, n-the inverting input of the preamplifier, Vout, the non-inverting output of the p-preamplifier, Vout, the common-mode output voltage of the cm-common-mode feedback unit, D1-the first clock signal controlling the first clock-controlled switch, D2-the second clock signal controlling the second clock-controlled switch, D3-the third clock signal controlling the sixth clock-controlled switch, CLK-the clock signal of the input Latch, D4-the short reset signal controlling the reset switch, Latch-Latch.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will provide those skilled in the art with a better understanding of the advantages and features of the present application, and will make the scope of the present application more clear and definite.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In integrated circuits, a combined structure of a pre-amplification circuit and a latch is often used in an ADC (digital-to-analog conversion) comparator structure. In the prior art, the preamplifier circuit of the integrated circuit is a pseudo-differential amplifier formed by two CMOS inverters. In the pseudo-differential amplifier, when the common-mode voltage input by the inverting input end and the non-inverting input end of the pseudo-differential amplifier is close to the jump voltage, the crystal and the crystal have the same amplification performance. When the inverting input terminal is short-circuited with the non-inverting input terminal, the pseudo-differential amplifier operates at its voltage jump point. However, the pseudo-differential amplifier generates a high common-mode gain, and the high common-mode gain has a certain influence on the value of the signal-to-noise ratio in the comparator.
The invention conception of the application is as follows: a simple common mode feedback circuit with a time sequence is provided, and common mode gain is effectively reduced.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram illustrating an embodiment of a low power consumption common mode feedback pre-amplifying circuit for timing control according to the present application.
In one embodiment of the present application, the present application relates to a time sequence controlled common mode feedback pre-amplifier circuit with low power consumption, a clock control unit and a common mode feedback unit, wherein the common mode feedback unit comprises a first resistor and a second resistor, the pre-amplifier comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein the inverting input terminal of the pre-amplifier is connected to the gate of the third transistor and the gate of the fifth transistor respectively, the non-inverting output terminal of the pre-amplifier is connected to the drain of the third transistor and the drain of the fifth transistor respectively, the drain of the third transistor and the drain of the fifth transistor are connected to the common mode voltage output terminal of the common mode feedback unit through the first resistor respectively, the drain of the fourth transistor and the drain of the sixth transistor are connected to the common mode voltage output terminal of the common mode feedback unit through the second resistor respectively, the inverting output end of the preamplifier is respectively connected with the drain electrode of the fourth transistor and the drain electrode of the sixth transistor, the non-inverting input end of the preamplifier is respectively connected with the grid electrode of the fourth transistor and the grid electrode of the sixth transistor, the source electrode of the first transistor is connected with an external power supply, the drain electrode of the first transistor is respectively connected with the source electrode of the third transistor and the source electrode of the fourth transistor, the source electrode of the second transistor is grounded, the drain electrode of the second transistor is respectively connected with the source electrode of the fifth transistor and the source electrode of the sixth transistor, the common-mode voltage output end of the common-mode feedback unit is connected with the input end of the capacitor, and the output.
In one embodiment of the present application, it is preferable to use a PMOS transistor for the first transistor and an NMOS transistor of a complementary type to the first transistor for the second transistor. The pseudo differential amplifier formed by two inverters has a specific structure as shown in fig. 2, wherein Vin, p1 are non-inverting input terminals of the pseudo differential amplifier, Vout, n1 are inverting output terminals of the pseudo differential amplifier, Vin, n1 are inverting input terminals of the pseudo differential amplifier, Vout, p1 are non-inverting output terminals, M3 is a third transistor, M4 is a fourth transistor, M5 is a fifth transistor, and M6 is a sixth transistor. The low-power consumption common-mode feedback pre-amplification circuit for time sequence control is added with related circuit components based on a pseudo-differential amplifier structure, so that the preamplifier can be realized.
Adding a common-mode feedback unit based on the pseudo-differential amplifier structure to form a preamplifier, comprising: the circuit comprises a first transistor, a second transistor, a first resistor, a second resistor and a capacitor. The added two resistors can detect a common-mode voltage, the common-mode voltage is used as bias voltage of the first transistor and the second transistor and is input from the grid electrodes of the first transistor and the second transistor respectively, the common-mode voltage controls the magnitude of current generated by the first transistor and the second transistor, and the generated current controls the amplification factor of the inverter. The first transistor and the second transistor are sized to operate in a linear region so that the driving voltage in the input tube is minimized and the amount of common mode voltage rejection is moderate.
A specific structural diagram of a preamplifier in the time-sequence-controlled low-power-consumption common-mode feedback pre-amplifying circuit of the present application is shown in fig. 3, where Vin, p is a non-inverting input terminal of the preamplifier, Vout, n is an inverting output terminal of the preamplifier, Vin, n is an inverting input terminal of the preamplifier, Vout, p is a non-inverting output terminal of the preamplifier, Vout, cm is a common-mode output voltage of the common-mode feedback unit, M1 is a first transistor, M2 is a second transistor, M3 is a third transistor, M4 is a fourth transistor, M5 is a fifth transistor, M6 is a sixth transistor, PMOS transistors are used for the first transistor, the third transistor, and the fifth transistor, and NMOS transistors of a type complementary to the first transistor are used for the second transistor, the fourth transistor, and the sixth transistor. Since the complexity and power consumption of the circuit are increased if the common mode feedback circuit is directly used, the common mode feedback unit is added to the preamplifier to achieve the effect of common mode feedback. When the common-mode output voltage in the current amplifier is increased, the amplification capability of the PMOS tube is weakened, and the common-mode voltage is reduced; therefore, a common-mode feedback unit is added on the basis of the pseudo-differential amplifier to form a pre-amplification unit in the low-power consumption common-mode feedback pre-amplification circuit controlled by the time sequence, so that proper voltage gain reduction is realized.
In one embodiment of the present application, in the time-sequence controlled common-mode feedback pre-amplifying circuit with low power consumption of the present application, the common-mode feedback unit further includes a first transistor, a second transistor and a capacitor, the clock control unit includes a first clock control switch, a second clock control switch, a third clock control switch, a fourth clock control switch, a fifth clock control switch, a sixth clock control switch, a seventh clock control switch, an eighth clock control switch and a ninth clock control switch, wherein an inverting input terminal of the preamplifier is interconnected with an non-inverting output terminal of the preamplifier through the first clock control switch, a non-inverting output terminal of the preamplifier is interconnected with a common-mode voltage output terminal of the common-mode feedback unit through the second clock control switch, a common-mode voltage output terminal of the common-mode feedback unit is interconnected with an inverting output terminal of the preamplifier through the fourth clock control switch, the common-mode voltage output end of the common-mode feedback unit is connected with the capacitor through a third clock control switch, the in-phase input end of the preamplifier is connected with the inverted output end of the preamplifier through a fifth clock control switch, the common-mode voltage output end of the common-mode feedback unit is connected with the grid electrode of the first transistor through a sixth clock control switch, the external power supply is connected with the grid electrode of the first transistor through a seventh clock control switch, the common-mode voltage output end of the common-mode feedback unit is connected with the grid electrode of the second transistor through an eighth clock control switch, and the grid electrode of the second transistor is grounded through a ninth clock control switch.
In an embodiment of the present invention, preferably, based on the aforementioned preamplifier, the timing-controlled low-power-consumption common-mode feedback pre-amplifying circuit of the present application adds a related clock control switch to the preamplifier, and the specific addition positions are as shown in fig. 4, where M1 is a first transistor, M2 is a second transistor, M3 is a third transistor, M4 is a fourth transistor, M5 is a fifth transistor, M6 is a sixth transistor, PMOS transistors are used for the first transistor, the third transistor, and the fifth transistor, and NMOS transistors of a type complementary to the first transistor are used for the second transistor, the fourth transistor, and the sixth transistor; c1 is the first clock control switch, C2 is the second clock control switch, C3 is the third clock control switch, C4 is the fourth clock control switch, C5 is the fifth clock control switch, C6 is the sixth clock control switch, C7 is the seventh clock control switch, C8 is the eighth clock control switch, C9 is the ninth clock control switch, Vin, p is the non-inverting input of the preamplifier, Vout, n is the inverting output of the preamplifier, Vin, n is the inverting input of the preamplifier, Vout, p is the non-inverting output of the preamplifier. The related clock control switch added in the preamplifier of the time sequence controlled low-power consumption common mode feedback preamplification circuit effectively reduces the common mode gain of the preamplification circuit.
In an embodiment of the present application, the timing-controlled common-mode feedback pre-amplifying circuit with low power consumption further includes: the first clock signal controls the opening and closing of the first clock control switch, the third clock control switch and the fifth clock control switch; the second clock signal controls the opening and closing of the second clock control switch and the fourth clock control switch; the third clock signal controls the opening and closing of a sixth clock control switch and an eighth clock control switch; the fourth clock signal controls the opening and closing of the seventh clock control switch and the ninth clock control switch.
In an embodiment of the present application, the timing-controlled common-mode feedback pre-amplifying circuit with low power consumption further includes: the fourth clock signal is an inverted clock signal of the third clock signal.
In this embodiment, in the timing-controlled low-power-consumption common-mode feedback pre-amplification circuit of the present application, the clock control switches added in the pre-amplification unit are respectively controlled by different clock signals. The switching of the first clock control switch, the switching of the third clock control switch and the switching of the fifth clock control switch are controlled by a first clock signal, the switching of the second clock control switch and the switching of the fourth clock control switch are controlled by a second clock signal, the switching of the sixth clock control switch and the switching of the eighth clock control switch are controlled by a third clock signal, and the switching of the seventh clock control switch and the switching of the ninth clock control switch are controlled by a fourth clock signal; and the fourth clock signal is an inverted clock signal of the third clock signal. Aiming at each clock control switch, the low-power consumption common-mode feedback pre-amplification circuit is respectively started at different stages according to the operation stage of the low-power consumption common-mode feedback pre-amplification circuit controlled by the time sequence, and is used for reducing the power consumption of the pre-amplification circuit and/or reducing the common-mode gain of the pre-amplification circuit.
In an embodiment of the present application, the timing-controlled common-mode feedback pre-amplifying circuit with low power consumption further includes: if the seventh clock control switch and the ninth clock control switch controlled by the fourth clock signal are both closed, the working states of the first transistor and the second transistor are switched off.
In one embodiment of the present invention, preferably, when the fourth clock signal is turned on at a high level, the seventh clock control switch and the ninth clock control switch controlled by the fourth clock signal are closed, the gate of the first transistor is connected to the external power supply, i.e., the gate of the first transistor is connected to a high potential, and the gate of the second transistor is connected to ground; at this time, the working states of the first transistor and the second transistor are switched to be off, namely, the pre-amplifying circuit does not work, and the power consumption of the pre-amplifying circuit is reduced.
In an embodiment of the present application, the timing-controlled common-mode feedback pre-amplifying circuit with low power consumption further includes: the in-phase output end of the preamplifier is connected with the anti-phase output end of the preamplifier through a reset switch, wherein the on-off of the reset switch is controlled through a short reset pulse signal.
In one embodiment of the present invention, preferably, the non-inverting output terminal of the preamplifier of the time-sequence controlled low-power consumption common-mode feedback pre-amplifying circuit of the present application is connected to the inverting output terminal of the preamplifier through a reset switch. The connection of the preamplifier and the latch is shown in fig. 5, where M1 is a first transistor, M2 is a second transistor, M3 is a third transistor, M4 is a fourth transistor, M5 is a fifth transistor, M6 is a sixth transistor, PMOS transistors are used for the first transistor, the third transistor and the fifth transistor, and NMOS transistors of a complementary type to the first transistor are used for the second transistor, the fourth transistor and the sixth transistor; c1 is a first clock control switch, C2 is a second clock control switch, C3 is a third clock control switch, C4 is a fourth clock control switch, C5 is a fifth clock control switch, C6 is a sixth clock control switch, C7 is a seventh clock control switch, C8 is an eighth clock control switch, C9 is a ninth clock control switch, C10 is a reset switch, Vin, p is the non-inverting input terminal of the preamplifier, Vout, n is the inverting output terminal of the preamplifier, Vin, n is the inverting input terminal of the preamplifier, Vout, p is the non-inverting output terminal of the preamplifier.
In an embodiment of the present application, the timing-controlled common-mode feedback pre-amplifying circuit with low power consumption further includes: and if the reset switch controlled by the short reset pulse signal is closed, setting and resetting the signal of the in-phase output end of the preamplifier and the signal of the anti-phase output end of the preamplifier.
In an embodiment of the present invention, it is preferable that the timing-controlled low-power-consumption common-mode feedback pre-amplifying circuit of the present application has three operation stages, i.e., a pre-amplifying stage, a low-noise comparison stage and a set clear stage, and fig. 6 shows changes of clock signals in the operation stages of the timing-controlled low-power-consumption common-mode feedback pre-amplifying circuit of the present application, where D1 is a first clock signal for controlling a first clock control switch, D2 is a second clock signal for controlling a second clock control switch, D3 is a third clock signal for controlling a sixth clock control switch, D4 is a short reset signal for controlling a reset switch, and CLK is a clock signal for inputting to a latch. As shown in fig. 6, after each pre-amplification stage, a short reset pulse signal is subsequently generated to reset the signal at the non-inverting output of the preamplifier, which allows the differential signal to start from near 0 and speeds up the settling of 0.
In an embodiment of the present application, the timing-controlled common-mode feedback pre-amplifying circuit with low power consumption further includes: and if the working state of the time sequence controlled low-power consumption common mode feedback pre-amplification circuit is a reset state, closing a first clock control switch, a third clock control switch, a fifth clock control switch, a second clock control switch and a fourth clock control switch which are controlled by the first clock signal.
In a specific example of the present invention, preferably, in the setting and clearing phase shown in fig. 6, the first clock signal and the second clock signal are both high-potential turned on, and the first clock control switch, the third clock control switch, the fifth clock control switch, the second clock control switch, and the fourth clock control switch controlled by the first clock signal are all closed; at the moment, the inverting input end of the preamplifier is in short circuit with the in-phase output end of the preamplifier, the inverting output end of the preamplifier is in short circuit with the in-phase input end of the preamplifier, and the inverting output end of the preamplifier is in short circuit with the in-phase output end of the preamplifier, so that the bias voltage is at a trip point, and the low-power consumption common-mode feedback pre-amplification circuit controlled by the time sequence obtains the maximum common-mode gain. The trip point voltage is similar to a capacitor and can be used as a common-mode input voltage in the next comparison stage, so that the common-mode point of the timing control low-power consumption common-mode feedback pre-amplification circuit is clamped to the trip point.
Fig. 7 is a schematic diagram illustrating an embodiment of a comparator of the timing controlled low power consumption common mode feedback pre-amplifying circuit of the present application.
In an embodiment of the present invention, it is preferable that the comparator structure having the timing-controlled low-power-consumption common-mode feedback pre-amplifying circuit is implemented by connecting the timing-controlled low-power-consumption common-mode feedback pre-amplifying circuit based on the aforementioned timing control of the present application to a latch. The connection mode of the time sequence controlled low-power consumption common mode feedback pre-amplifying circuit and the latch is shown in fig. 8, the non-inverting output end of the preamplifier in the time sequence controlled low-power consumption common mode feedback pre-amplifying circuit is connected with the non-inverting input end of the latch, and the inverting output end of the preamplifier is connected with the inverting input end of the latch. In the pre-amplifying circuit of the comparator shown in fig. 8, M1 is a first transistor, M2 is a second transistor, M3 is a third transistor, M4 is a fourth transistor, M5 is a fifth transistor, M6 is a sixth transistor, PMOS transistors are used for the first transistor, the third transistor, and the fifth transistor, and NMOS transistors of a type complementary to the first transistor are used for the second transistor, the fourth transistor, and the sixth transistor; c1 is a first clock control switch, C2 is a second clock control switch, C3 is a third clock control switch, C4 is a fourth clock control switch, C5 is a fifth clock control switch, C6 is a sixth clock control switch, C7 is a seventh clock control switch, C8 is an eighth clock control switch, C9 is a ninth clock control switch, C10 is a reset switch, Vin, p is the non-inverting input terminal of the preamplifier, Vout, n is the inverting output terminal of the preamplifier, Vin, n is the inverting input terminal of the preamplifier, Vout, p is the non-inverting output terminal of the preamplifier. In the latch of the comparator shown in fig. 8, CLK is a clock signal input to the latch, and its operation state in each operation stage of the timing-controlled low-power consumption common mode feedback preamplification circuit is as shown in fig. 6, which is turned on at a high potential in a low-noise comparison stage.
The application designs a time sequence controlled low-power consumption common-mode feedback pre-amplifying circuit and a comparator. By providing a simple common mode feedback circuit with time sequence, the common mode gain is effectively reduced, and the power consumption is reduced.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings, which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.
Claims (10)
1. A time sequence controlled low-power consumption common mode feedback pre-amplifying circuit is characterized by comprising: the common-mode feedback unit comprises a first transistor, a second transistor and a capacitor, the clock control unit comprises a first clock control switch, a second clock control switch, a third clock control switch, a fourth clock control switch, a fifth clock control switch, a sixth clock control switch, a seventh clock control switch, an eighth clock control switch and a ninth clock control switch, wherein,
the inverting input terminal of the preamplifier is interconnected with the non-inverting output terminal of the preamplifier through the first clock control switch, the non-inverting output terminal of the preamplifier is interconnected with the common mode voltage output terminal of the common mode feedback unit through the second clock control switch, the common mode voltage output terminal of the common mode feedback unit is interconnected with the inverting output terminal of the preamplifier through the fourth clock control switch, the common mode voltage output terminal of the common mode feedback unit is interconnected with the capacitor through the third clock control switch, the non-inverting input terminal of the preamplifier is interconnected with the inverting output terminal of the preamplifier through the fifth clock control switch, the common mode voltage output terminal of the common mode feedback unit is interconnected with the gate of the first transistor through the sixth clock control switch, and the external power supply is interconnected with the gate of the first transistor through the seventh clock control switch, and a common-mode voltage output end of the common-mode feedback unit is interconnected with a grid electrode of the second transistor through the eighth clock control switch, and the grid electrode of the second transistor is grounded through the ninth clock control switch.
2. The timing controlled low power consumption common mode feedback preamplification circuit of claim 1, wherein a first clock signal controls the opening and closing of the first, third and fifth clock controlled switches;
the second clock signal controls the opening and closing of the second clock control switch and the fourth clock control switch;
the third clock signal controls the opening and closing of the sixth clock control switch and the eighth clock control switch;
and the fourth clock signal controls the opening and closing of the seventh clock control switch and the ninth clock control switch.
3. The timing controlled low power consumption common mode feedback pre-amplification circuit of claim 2, wherein the fourth clock signal is an inverted clock signal of the third clock signal.
4. The timing controlled low power consumption common mode feedback pre-amplifying circuit according to claim 1, wherein said common mode feedback unit further comprises a first resistor and a second resistor, said pre-amplifier comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, wherein,
the inverting input end of the preamplifier is respectively connected with the grid electrode of the third transistor and the grid electrode of the fifth transistor, the in-phase output end of the preamplifier is respectively connected with the drain electrode of the third transistor and the drain electrode of the fifth transistor, the drain electrode of the third transistor and the drain electrode of the fifth transistor are respectively connected with the common-mode voltage output end of the common-mode feedback unit through a first resistor, the drain electrode of the fourth transistor and the drain electrode of the sixth transistor are respectively connected with the common-mode voltage output end of the common-mode feedback unit through a second resistor, the inverting output end of the preamplifier is respectively connected with the drain electrode of the fourth transistor and the drain electrode of the sixth transistor, and the in-phase input end of the preamplifier is respectively connected with the grid electrode of the fourth transistor and the grid electrode of the sixth transistor, the source of the first transistor is connected with an external power supply, the drain of the first transistor is respectively connected with the source of the third transistor and the source of the fourth transistor, the source of the second transistor is grounded, the drain of the second transistor is respectively connected with the source of the fifth transistor and the source of the sixth transistor, the common-mode voltage output end of the common-mode feedback unit is connected with the input end of the capacitor, and the output end of the capacitor is grounded.
5. The timing controlled low power consumption common mode feedback pre-amplifier circuit as claimed in claim 4, wherein said first transistor, said third transistor and said fifth transistor are the same type of transistor, said second transistor, said fourth transistor and said sixth transistor are the same type of transistor, wherein said first transistor and said second transistor are complementary type of transistor.
6. The timing-controlled low-power-consumption common-mode feedback pre-amplification circuit according to claim 1 or 2, wherein if the seventh and ninth clock-controlled switches controlled by the fourth clock signal are both closed, the operating states of the first and second transistors are switched off.
7. The timing controlled low power consumption common mode feedback pre-amplifier circuit according to claim 1, wherein the non-inverting output terminal of said preamplifier is connected to the inverting output terminal of said preamplifier through a reset switch, wherein the opening and closing of said reset switch is controlled by a short reset pulse signal.
8. The timing controlled low power consumption common mode feedback pre-amplifying circuit according to claim 7, wherein if the reset switch controlled by the short reset pulse signal is closed, the signal at the in-phase output terminal of the pre-amplifier and the signal at the inverted output terminal of the pre-amplifier are set and cleared.
9. The timing-controlled low-power-consumption common-mode feedback pre-amplifying circuit as claimed in claim 1, wherein if the operating state of the timing-controlled low-power-consumption common-mode feedback pre-amplifying circuit is a reset state, the first clock control switch, the third clock control switch, the fifth clock control switch and the second clock control switch and the fourth clock control switch controlled by the first clock signal are all turned off.
10. A comparator comprising the timing controlled low power consumption common mode feedback preamplification circuit and latch of claim 1, wherein
The non-inverting output end of the preamplifier is connected with the non-inverting input end of the latch, and the inverting input end of the preamplifier is connected with the inverting input end of the latch.
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| WO2024077818A1 (en) * | 2022-10-09 | 2024-04-18 | 深圳英集芯科技股份有限公司 | Voltage-controlled frequency circuit and related products |
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| CN112653434B (en) | 2024-05-24 |
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