CN112635553A - Manufacturing method of thin film transistor and display device - Google Patents
Manufacturing method of thin film transistor and display device Download PDFInfo
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- CN112635553A CN112635553A CN202011566630.7A CN202011566630A CN112635553A CN 112635553 A CN112635553 A CN 112635553A CN 202011566630 A CN202011566630 A CN 202011566630A CN 112635553 A CN112635553 A CN 112635553A
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- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 42
- 238000005468 ion implantation Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 19
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- 239000000463 material Substances 0.000 claims description 10
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 3
- 230000005684 electric field Effects 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 2
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- 238000002347 injection Methods 0.000 claims 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
- H10D30/6739—Conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
- H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
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- Thin Film Transistor (AREA)
Abstract
本申请提供了一种薄膜晶体管的制作方法和显示装置，涉及半导体领域。本申请提供的制作方法，通过在金属层上形成图形化的光刻胶。然后对去除了光刻胶的非遮挡区的金属层进行离子注入，增加非遮挡区中与遮挡区相邻的位置处的金属层的耐腐蚀性。这样使得后续进行腐蚀后，最终剩余的金属层所形成栅极的边缘具有平缓的斜坡，与基板的接触角比较小。在后续铺设栅极绝缘层之后，栅极绝缘层在铺设时厚度比较均匀，栅极的边缘与源极或者漏极之间不容易形成薄弱区域，从而降低了被击穿的风险，因此提高了薄膜晶体管的稳定性和寿命。显示装置包括了上述制作方法制得的薄膜晶体管，因此也具有性能稳定、寿命长的特点。
The present application provides a method for manufacturing a thin film transistor and a display device, and relates to the field of semiconductors. The fabrication method provided by the present application forms a patterned photoresist on the metal layer. Then, ion implantation is performed on the metal layer of the non-blocking region from which the photoresist has been removed, so as to increase the corrosion resistance of the metal layer in the non-blocking region adjacent to the blocking region. In this way, after subsequent etching, the edge of the gate formed by the remaining metal layer has a gentle slope, and the contact angle with the substrate is relatively small. After the subsequent laying of the gate insulating layer, the thickness of the gate insulating layer is relatively uniform during laying, and it is not easy to form a weak area between the edge of the gate and the source or drain, thereby reducing the risk of breakdown, thus improving the Stability and lifetime of thin film transistors. The display device includes the thin film transistor prepared by the above manufacturing method, so it also has the characteristics of stable performance and long life.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a manufacturing method of a thin film transistor and a display device.
Background
The TFT (thin Film transistor) technology is a large-scale semiconductor fully integrated circuit manufacturing technology adopting new materials and new processes, and is the basis of liquid crystal, inorganic and organic Film electroluminescent flat panel displays. Among them, a thin film transistor device (TFT) is an important device for driving a pixel to realize a display function. However, the existing manufacturing process of the thin film transistor easily causes weak points on the manufactured thin film transistor, and under the condition of applying voltage, the device is easily broken down, so that the stability and the service life of the device are affected.
Disclosure of Invention
The purpose of the present application includes providing a method for manufacturing a thin film transistor, which can manufacture a thin film transistor with stable performance and long service life. The embodiment of the application also provides a display device which comprises the thin film transistor.
The embodiment of the application can be realized as follows:
in a first aspect, the present application provides a method for manufacturing a thin film transistor, including:
forming a metal layer on a substrate;
forming photoresist covering the metal layer, removing part of the photoresist in a photoetching mode, and forming a shielding area covered by the residual photoresist and a non-shielding area exposing the metal layer;
performing ion implantation in the non-shielding region to enhance the corrosion resistance of the metal layer at a position adjacent to the shielding region in the non-shielding region;
corroding the metal layer in the non-shielding area to form a grid electrode on the residual metal layer;
and manufacturing a gate insulating layer, a source electrode and a drain electrode to obtain the thin film transistor.
In an alternative embodiment, the ions used for ion implantation include at least one of Ti, N, or C ions.
In an alternative embodiment, ion implantation includes deflecting the ion beam with an electric or magnetic field to cause bombardment of the metal layer surface by the ion beam. Optionally, the bombardment direction and the surface of the metal layer form a preset inclination angle, and the ion beam obliquely faces to the remaining photoresist and the sidewall adjacent to the non-shielding region.
In an alternative embodiment, the ion implantation is performed at an implant dose of (1-6) × 1018cm-2。
In an alternative embodiment, the ion energy of the ion implantation is 10KeV to 50 KeV.
In an optional embodiment, two sides of the gate in the width direction form a slope respectively, and an included angle between the slope and the upper surface of the gate is greater than 120 °.
In an alternative embodiment, the ion implantation makes the surface of the metal layer form an ion implantation layer, the thickness of the ion implantation layer is in positive correlation with the ion energy, and the thickness of the ion implantation layer gradually decreases from the edge of the non-shielding region to the middle.
In an alternative embodiment, the material of the metal layer comprises at least one of Au, Mo, Al, Cu.
In an alternative embodiment, the material of the metal layer includes Al and Mo, and the etchant used for etching the metal layer in the non-shielding region includes hydrochloric acid and hydrofluoric acid.
In a second aspect, the present application provides a display device including a thin film transistor manufactured by the manufacturing method of any one of the foregoing embodiments.
The beneficial effects of the embodiment of the application include:
according to the manufacturing method provided by the embodiment of the application, the patterned photoresist is formed on the metal layer. And then, carrying out ion implantation on the metal layer of the non-shielding area from which the photoresist is removed, so as to increase the corrosion resistance of the metal layer at the position adjacent to the shielding area in the non-shielding area. Therefore, when subsequent etching is carried out, the metal layer close to the shielding area is more difficult to etch, the residual metal layer forms a grid electrode, a relatively gentle slope is formed at the edge of the grid electrode, and the contact angle between the grid electrode and the substrate is relatively small. Because the edge of the grid forms a relatively gentle slope, the thickness of the grid insulating layer is relatively uniform when the grid insulating layer is laid after the grid insulating layer is laid subsequently, and the thickness of the edge of the grid is not too small compared with the thickness of other positions. After the source electrode and the drain electrode are manufactured subsequently, a weak area is not easily formed between the edge of the grid electrode and the source electrode or the drain electrode, so that the risk of breakdown is reduced, and the stability and the service life of the thin film transistor are improved.
The display device provided by the embodiment of the application comprises the thin film transistor manufactured by the manufacturing method of the embodiment of the application, so that the display device has the characteristics of stable performance and long service life.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIGS. 1 to 5 are diagrams illustrating a conventional etching process for fabricating a thin film transistor;
FIGS. 6 to 10 are diagrams illustrating a conventional metal lift-off process for fabricating a Thin Film Transistor (TFT) structure;
FIG. 11 is a flow chart illustrating a method of fabricating a thin film transistor according to an embodiment of the present disclosure;
fig. 12 to 17 are process diagrams of manufacturing a thin film transistor according to an embodiment of the present application.
Icon: 1' -a substrate; a 2' -metal layer; 3' -a photoresist; a 4' -gate electrode; 5' -a gate insulating layer; 6' -a semiconductor layer; a 7' -source electrode; an 8' -drain electrode; 100-a substrate; 200-a metal layer; 210-an ion-implanted layer; 300-photoresist; 400-a gate; 500-a gate insulating layer; 600-a semiconductor layer; 700-source electrode; 800-drain electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the present invention product is usually put into use, it is only for convenience of describing the present application and simplifying the description, but it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and thus, should not be construed as limiting the present application.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
A Thin Film Transistor (TFT) is mainly composed of a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode, and a Thin Film formation process adopts a Chemical Vapor Deposition (CVD), a photolithography, an etching (Etch), a Physical Vapor Deposition (PVD), and other process techniques similar to a semiconductor manufacturing process. The thin film transistor works on the principle that the channel resistance is adjusted through the gate voltage, so that the drain current is effectively controlled. The size and stability of the gate resistance is therefore critical to device lifetime. Fig. 1 to 5 are diagrams illustrating a conventional etching process for fabricating a thin film transistor. Referring to fig. 1 to 5, in a conventional etching process for manufacturing a thin film transistor, a metal layer 2 ' is formed on a substrate 1 ', and then a patterned photoresist 3 ' is formed, as shown in fig. 1. Wherein the part of the metal layer 2 'shielded by the photoresist 3' is used to form the gate 4 ', the part not shielded is removed by etching to obtain the structure shown in fig. 2, and the photoresist 3' is stripped to form the structure shown in fig. 3. Since the etching solution will etch into the shielding region, the top surface and the side surface of the finally formed gate 4 ' still form a relatively sharp corner, and the shape of the two sides of the gate 4 ' will cause the subsequently laid gate insulating layer 5 ' to be thinner (thinner than other positions), as shown in fig. 4. On this basis, the source electrode 7 ', the drain electrode 8 ', and the semiconductor layer 6 ' are successively formed, and then a thin film transistor is obtained. However, the gate insulating layer 5 'is uneven in thickness and thinner at the positions on both sides of the gate 4', a weak region is formed at the weak region, and under the condition of voltage application, side leakage current exists in addition to vertical current, a weak region breaks down, and therefore the device is unstable and the service life is shortened.
The gate 4' manufactured by the metal lift-off process is also easy to have a weak area when a thin film transistor is subsequently manufactured. Fig. 6 to 10 are diagrams illustrating a conventional metal lift-off process for fabricating a thin film transistor. As shown in fig. 6 to 10, the process first forms a patterned photoresist 3 'and then lays a metal layer 2' as shown in fig. 6 and 7. The metal layer 2 ' on the photoresist 3 ' is removed with the photoresist 3 ', as shown in fig. 8. It can be seen that due to process problems, sharp protrusions are likely to occur at the corner positions on both sides of the gate electrode 4 ', resulting in a thin weak region after the gate insulating layer 5' is laid thereon, as shown in fig. 9 and 10. Therefore, the problems of poor stability and short service life of the manufactured thin film transistor still exist by adopting the conventional process.
It can be seen that one of the reasons for the weak region is because the angle between the upper surface and the side surface of the gate 4' is relatively sharp (and may protrude even in the metal stripping process). In the prior art shown in fig. 1 to 5, the reason why the problem occurs is that the etching solution still maintains strong corrosivity at the position (shielding region) covered by the photoresist 3 ', and rapidly etches downwards (even into the shielding region) along the edge of the shielding region, so that the two sides of the gate 4 ' are not smooth enough, and the included angle between the side surface of the gate 4 ' and the upper surface is sharp, thereby causing the occurrence of a subsequent weak region. The breakdown field is improved mainly by improving the film quality of the gate insulating layer 5' in the industry at present, and the breakdown of the weak point of the device is less concerned.
In order to solve the problems in the prior art, the embodiment of the application provides a manufacturing method of a thin film transistor, and before metal etching, an ion implantation means is added to improve the local corrosion resistance of a metal layer, so that two sides of a manufactured gate are relatively gentle, a laid gate insulating layer can be more uniform, and a weak section is not easy to exist.
FIG. 11 is a flow chart illustrating a method of fabricating a thin film transistor according to an embodiment of the present disclosure; fig. 12 to 17 are process diagrams of manufacturing a thin film transistor according to an embodiment of the present application. Referring to fig. 11 to 17, a method for manufacturing a thin film transistor according to an embodiment of the present disclosure includes:
step S100 is to form a metal layer on a substrate.
As shown in fig. 12, in the present embodiment, a Si substrate 100, a glass substrate 100, a substrate 100 such as flexible PI/PET, or the like may be used as the substrate 100, and in the present embodiment, the Si substrate 100 is used. Optionally, the material of the metal layer 200 includes at least one of Au, Mo, Al, and Cu, for example, in the present embodiment, a double-layer structure (shown as one layer) of Al and Mo is adopted, and Al is located at an upper layer. The material of the metal layer 200 deposited at this step should be selected according to the desired gate 400. In this step, the metal layer 200 may be deposited on the substrate 100 by magnetron sputtering, electron beam evaporation, or other processes. In the present embodiment, a Mo-Al laminated metal layer 200 with a thickness of 30-150 nm is deposited by electron beam evaporation.
Step S200, forming photoresist covering the metal layer, removing part of the photoresist in a photoetching mode, and forming a shielding area covered by the residual photoresist and a non-shielding area exposing the metal layer.
In this step, a layer of photoresist 300 is first uniformly laid on the metal layer 200. Then, a partial exposure is performed on the photoresist 300, and depending on the property of the photoresist 300 (positive photoresist or negative photoresist), the exposed or unexposed photoresist 300 can be washed away by the developing solution, and the remaining photoresist 300 is the patterned photoresist 300, wherein the shielded part is a shielded region and the unshielded part is an unshielded region, as shown in fig. 13. The metal layer 200 of the blocking region is used to form a body portion of the gate 400 in a subsequent step.
Specifically, in the embodiment, a positive photoresist 300 is dripped on the metal layer 200 formed in the step S100, a low-speed spin coating is performed at a speed of 500rpm5S, a film is formed at a high speed of 2000-4000 rpm for 30S, the thickness of the film is about 2-5 μm, a sample after film formation is baked on a hot plate at 100 ℃ for 60S, a mask is used for ultraviolet exposure for 8S in a photoetching machine, the exposed film is developed in a developing solution for 2-3 min, the photoresist 300 is patterned, and the photoresist is baked on the hot plate at 100 ℃ for 5-10 min to solidify. The photoresist 300 blocks a region where the gate electrode 400 is to be formed, and the non-blocking region is a region where ions are implanted and etched in a subsequent step.
Step S300, ion implantation is carried out in the non-shielding area so as to enhance the corrosion resistance of the metal layer at the position adjacent to the shielding area in the non-shielding area.
The step is to perform ion implantation on the product obtained in step S200, wherein the ion selected for the ion implantation may be at least one of Ti ion, N ion or C ion, and the specific selection should be determined according to the materials of the substrate 100 and the metal layer 200. In this embodiment, Ti ions are selected to implant into the aluminum surface at an implant dose of (1-6) × 1018cm-2Formation of Ti3Al、Al2O3The alloy layer and the damaged layer have an ion energy of 10KeV to 50 KeV. As shown in fig. 14, the ion implantation makes the surface of the metal layer 200 form an ion implantation layer 210 (i.e. including the formed alloy layer and damaged layer), and the thickness of the ion implantation layer 210 has a positive correlation with the ion energy. The ion-implanted layer 210 is more resistant to corrosion than other locations of the metal layer 200, and the thicker the ion-implanted layer 210, the more resistant it is to corrosion.
In an alternative embodiment, the ion implantation includes deflecting the ion beam with an electric or magnetic field such that the ion beam bombards the surface of the metal layer 200. Optionally, the bombardment direction is a predetermined inclination angle with respect to the surface of the metal layer 200, and the ion beam is inclined toward the sidewall of the remaining photoresist 300 adjacent to the non-shielding region. This makes the thickness of the ion implantation layer 210 gradually decrease from the edge of the non-blocking region to the center in the present embodiment. Specifically, in the present embodiment, the thickness and the angular distribution of the ion implantation layer 210 can be controlled by controlling the acceleration energy of the electric field, and the thickness distribution of the film layer is a concave shape distribution in the non-blocking region, and the positions with large acceleration energy of the electric field are precisely set to be close to the two sides of the photoresist 300 by focusing the ion beam into a nano-scale beamlet ion optical system, and the position with small acceleration energy is the middle part of the non-blocking region. The ion implantation results in a graded ion implantation layer 210 as shown in fig. 14, which enhances the corrosion resistance of the metal layer 200 near the shadow region.
Step S400, the metal layer of the non-shielding area is corroded, and the rest metal layer forms a grid electrode.
The product obtained in step S300 is put into an etching solution to etch the metal layer 200 in the non-shielding region. Specifically, in this embodiment, hydrochloric acid is used to etch for 1-5 min, the Al film layer in the non-ion-implanted region is etched, and Ti is slowly etched3Al、Al2O3And (4) rinsing twice with water, and then putting the sample into a hydrofluoric acid solution to continuously corrode the Mo layer. After the etching is completed, the etched sample is immersed and cleaned in a photoresist removing solution such as acetone, and the photoresist 300 is removed, thereby finally forming the structure shown in fig. 15. Since the metal layer 200 close to the shielding region has improved corrosion resistance by using the ion implantation method in the previous step, the corrosion depth is shallow, while the metal layer 200 far from the shielding region has relatively low corrosion resistance and deeper corrosion depth. Therefore, as shown in the figure, the two sides of the obtained gate 400 in the width direction respectively form a slope, and an included angle between the slope and the upper surface of the gate 400 is greater than 120 °. Specifically, in this embodiment, an included angle between the slope and the upper surface of the gate 400 may be controlled to be greater than 135 °, so that a contact angle between the slope and the substrate 100 is smaller than 45 °, which can better prevent the gate insulating layer 500 laid subsequently from being too thin at two sides of the gate 400 to cause easy breakdown.
Step S500, a gate insulating layer, a source electrode, and a drain electrode are fabricated to obtain a thin film transistor.
After the gate 400 is fabricated, the gate insulating layer 500 is further formed, the semiconductor layer 600 is fabricated, and the source electrode 700 and the drain electrode 800 are fabricated.
Specifically, in the embodiment, 50 to 100nm HfO may be deposited on the basis of the sample obtained in step S4002Or ZrO2A gate insulating layer 500 is formed. The gate insulating layer 500 is spread out with a uniform thickness according to the pattern of the gate electrode 400, as shown in fig. 16. Depositing Indium Gallium Zinc Oxide (IGZO) with a thickness of 40-60 nm on the gate insulating layer 500 to form a semiconductor layer 600 thin film, then obtaining the patterned semiconductor layer 600 by using photolithography and etching techniques, and finally removing the photoresist. Then, depositing a 50-200 nm source on the semiconductor layer 600 by lift-off processThe gate 700 and the drain 800 form a thin film transistor structure as shown in fig. 17. The source electrode 700 and the drain electrode 800 may use Mo as a deposition material. According to the thin film transistor provided by the embodiment of the application, when the gate 400 is formed by etching, the ion implantation mode is used, the ion implantation layer 210 with uneven thickness is generated, the thickness of the ion implantation layer 210 becomes thinner gradually in the direction away from the shielding region (the main body part of the gate 400), so that the corrosion resistance becomes worse gradually, so that the two sides of the gate 400 obtained after etching form gentle slopes, and therefore, the thickness of the gate insulating layer 500 is not easy to become too thin on the two sides of the gate 400. In this way, the gate insulating layer 500 is uniform in thickness and is not prone to weak regions and breakdown, so that the thin film transistor manufactured by the manufacturing method provided by the embodiment of the application has the characteristics of good stability and long service life.
In the aspect of manufacturing process, a system with good controllability and accurate ion implantation control is introduced to realize the distribution of different implantation concentrations and film thicknesses, the process is simple and flexible, and multiple materials can be selected as masks without affecting the device area. The ion implantation has small lateral extension, which is beneficial to improving the accuracy of the device.
In addition, the embodiment of the application also provides a practical device, and the display device comprises the thin film transistor manufactured by the embodiment of the application, so that the display device has the characteristics of stable performance and long service life.
In summary, in the manufacturing method provided by the embodiment of the present application, a patterned photoresist is formed on a metal layer. And then, carrying out ion implantation on the metal layer of the non-shielding area from which the photoresist is removed, so as to increase the corrosion resistance of the metal layer at the position adjacent to the shielding area in the non-shielding area. Therefore, when subsequent etching is carried out, the metal layer close to the shielding area is more difficult to etch, the residual metal layer forms a grid electrode, a relatively gentle slope is formed at the edge of the grid electrode, and the contact angle between the grid electrode and the substrate is relatively small. Because the edge of the grid forms a relatively gentle slope, the thickness of the grid insulating layer is relatively uniform when the grid insulating layer is laid after the grid insulating layer is laid subsequently, and the thickness of the edge of the grid is not too small compared with the thickness of other positions. After the source electrode and the drain electrode are manufactured subsequently, a weak area is not easily formed between the edge of the grid electrode and the source electrode or the drain electrode, so that the risk of breakdown is reduced, and the stability and the service life of the thin film transistor are improved.
The display device provided by the embodiment of the application comprises the thin film transistor manufactured by the manufacturing method of the embodiment of the application, so that the display device has the characteristics of stable performance and long service life.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
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