CN112635492A

CN112635492A - Strain GeSiOI substrate and manufacturing method thereof

Info

Publication number: CN112635492A
Application number: CN202011393106.4A
Authority: CN
Inventors: 亨利·H·阿达姆松; 王桂磊; 罗雪; 孔真真
Original assignee: Guangdong Greater Bay Area Institute of Integrated Circuit and System
Current assignee: Guangdong Greater Bay Area Institute of Integrated Circuit and System
Priority date: 2020-12-02
Filing date: 2020-12-02
Publication date: 2021-04-09
Anticipated expiration: 2040-12-02
Also published as: CN112635492B

Abstract

The invention relates to a strained GeSiOI substrate and a manufacturing method thereof. A strained _GeSiOI substrate comprises: a silicon substrate, a first silicon oxide layer, a plurality of silicon nitride spacers; a second silicon _dioxide layer; Manufacturing method: manufacturing a supporting substrate: depositing a first silicon oxide layer and a silicon nitride layer on a first silicon substrate in sequence; patterning the silicon nitride layer to form a plurality of discrete silicon nitride spacers, which are separated adjacently Form trenches between the strips; form a second silicon dioxide layer to fill the trenches and cover the upper surfaces of the spacers; make a donor substrate: epitaxial Ge _1-x Si _x layer on the second silicon substrate; The substrate and the donor substrate are bonded and thinned to obtain a strained GeSiOI substrate. The present invention is introduced in the supporting substrate instead of the donor substrate, the GeSiOI substrate formed by this process has a larger strain force, and the fabricated device has better electrical properties.

Description

Strain GeSiOI substrate and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductor materials and production processes, in particular to a strain GeSiOI substrate and a manufacturing method thereof.

Background

The feature size of integrated circuit devices reaches 3-5nm, and is limited by physical effects, so that further miniaturization is realized, and new materials and material engineering are indispensable. Silicon Germanium on insulator GeSiOI (Germanium)&silicon-On-Insulator) combines the advantages of Ge and SOI structures, which has become an ideal material for fabricating p-channel MOSFETs and MSM (Metal-Semiconductor-Metal) photodetectors. GeSiOI has a structure similar to SOI, with Ge in the top layer_1-xSi_xAnd a buried oxide layer is introduced between the substrate and the backing substrate. Ge (germanium) oxide_1-xSi_xThe (x is more than 0 and less than 1) base device has the following characteristics: 1) has Ge_1-zSi_zThe high mobility of the material is beneficial to improving the on-state current of the device and improving the performance of the device; 2) the advantages of low subthreshold swing, low parasitic capacitance, low power consumption and high driving current of the device on the insulator are combined, and the device is expected to be widely applied in the future. On the basis that GeSiOI has the advantages, strain engineering is adopted, so that the channel mobility and the on-state current of the device can be further improved, and the performance of the device can be improved.

The current method for manufacturing the strain GeSiOI substrate is as follows: firstly growing a strain buffer layer on a silicon substrate, and then extending Ge on the buffer layer_1-zSi_zThe layer introduces stress that cannot be well preserved after subsequent layer transfer and thinning.

The invention is therefore proposed.

Disclosure of Invention

The main object of the present invention is to provide a strained GeSiOI substrate with a silicon nitride spacer structure added to Ge_1-xSi_xThe semiconductor layer introduces uniform stress, and the performance of the device is improved.

A second object of the present invention is to provide a method for fabricating the strained GeSiOI substrate, which introduces stress to the semiconductor layer by forming a silicon nitride spacer structure on the support substrate and bonding the donor substrate, thereby avoiding stress weakening problems due to layer transfer and thinning when the donor substrate introduces stress.

In order to achieve the above object, the present invention provides the following technical solutions.

A strained GeSiOI substrate comprises, stacked in sequence from bottom to top:

a silicon substrate, a silicon substrate and a silicon substrate,

a first silicon oxide layer formed on the first silicon oxide layer,

the silicon nitride separation strips are distributed on the surface of the first silicon oxide layer at intervals;

the second silicon dioxide layer fills gaps among the separation strips and covers the separation strips;

Ge_1-xSi_xa layer;

wherein x is more than 0 and less than 1.

In addition, in the second silicon dioxide layer and the Ge_1-xSi_xA high-k dielectric layer may also be added between the layers.

A method for fabricating a strained GeSiOI substrate includes:

manufacturing a support substrate:

providing a first silicon substrate, and depositing a first silicon oxide layer and a silicon nitride layer on the first silicon substrate in sequence; patterning the silicon nitride layer to form a plurality of discrete silicon nitride separation strips, wherein a groove is formed between every two adjacent silicon nitride separation strips and penetrates through the silicon nitride layer; then forming a second silicon dioxide layer, wherein the second silicon dioxide layer fills the groove and covers the upper surface of the silicon nitride separation strip;

making a donor substrate:

providing a second silicon substrate and epitaxially growing Ge on said second silicon substrate_1-xSi_xLayer, x is more than 0 and less than 1;

bonding:

with said second silicon oxide layer and said Ge_1-xSi_xThe layer being a bonding face, bonding the support substrate and the donor substrate, and then removing the second silicon substrate, optionally for Ge_1-xSi_xAnd thinning the layer to obtain the strain GeSiOI substrate.

Compared with the prior art, the invention achieves the following technical effects:

(1) in one aspect, the invention adds a silicon nitride spacer structure between two layers of silicon oxide, which acts as a spacerMay be Ge-doped for buffer layer_1-xSi_xThe semiconductor layer introduces uniform stress, the performance of the device is improved, and the substrate can be used for devices which need thin semiconductor layers such as Fully-depleted (FD) devices and the like;

(2) on the other hand, the silicon nitride division bar structure is introduced into the supporting substrate, and the second substrate is etched after bonding, so that the silicon nitride division bar in the supporting substrate is not influenced, the strain introduced by the silicon nitride division bar is not weakened, and the stress can be maintained to a greater extent compared with the traditional process;

(3) the addition of the high-k dielectric layer can reduce interface defects, enhance adhesion and improve device characteristics.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.

FIGS. 1 to 7 are schematic structural views obtained in the steps of manufacturing a strained GeSiOI substrate according to the present invention.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

The difference between the method for introducing stress when manufacturing the strain GeSiOI substrate and the traditional process is as follows: the invention is introduced into a supporting substrate instead of a donor substrate, the GeSiOI substrate formed by the process has larger strain force, and the manufactured device has more excellent electrical characteristics, and the basic structure of the substrate comprises the following components which are stacked from bottom to top in sequence:

a silicon substrate, a silicon substrate and a silicon substrate,

a first silicon oxide layer formed on the first silicon oxide layer,

Ge_1-xSi_xa layer;

wherein x is more than 0 and less than 1.

In the strained substrate, the crystal orientation of the silicon substrate is arbitrary, and examples thereof include a silicon (100) substrate, a silicon (110) substrate, and the like.

The thicknesses of the first silicon oxide layer and the second silicon oxide layer are arbitrarily adjusted as required.

The size (height, width, etc.) and the interval of the silicon nitride dividing strips are adjusted arbitrarily according to needs.

May also be on the second silicon dioxide layer and the Ge_1-xSi_xA high-k dielectric layer is added between the layers, so that interface defects can be reduced and adhesion can be enhanced. Especially when the content of Ge in Ge is higher, x is more than 0 and less than or equal to 0.3, the high-k dielectric layer is more suitable to be increased. When x is more than or equal to 0.3, a high-k dielectric layer can be grown or not grown. High-k dielectrics generally refer to dielectric materials having a k greater than the dielectric constant of silicon oxide, such as metal oxides or nitrides (Si)₃N₄SiON, etc.), preferably aluminum oxide Al₂O₃。

The basic process for manufacturing the strain GeSiOI substrate comprises the following steps: making a support substrate → making a donor substrate → bonding → removing the sacrificial layer, as detailed below.

When there is no high-k dielectric layer, it includes:

manufacturing a support substrate:

making a donor substrate:

epitaxial Ge on second silicon substrate_1-xSi_xLayer, x is more than 0 and less than 1;

with said second silicon oxide layer and said Ge_1-xSi_xThe layer being a bonding face, bonding the support substrate and the donor substrate, and then removing the second silicon substrate, optionally with Ge_1-xSi_xAnd thinning the layer to obtain the strain GeSiOI substrate.

When containing the high-k dielectric layer, the high-k dielectric layer comprises:

manufacturing a support substrate:

making a donor substrate:

epitaxial Ge on second silicon substrate_1-xSi_xLayer, x is more than 0 and less than 1; then depositing a high-k dielectric layer;

bonding the support substrate and the donor substrate by using the second silicon dioxide layer and the high-K dielectric layer as bonding surfaces,followed by removal of the second silicon substrate, optionally for Ge_1-xSi_xAnd thinning the layer to obtain the strain GeSiOI substrate.

In the above two methods, the deposition and etching means is arbitrary, for example, polishing (Grading) back thinning, Chemical Mechanical Polishing (CMP), wet etching, dry etching, Atomic Layer Etching (ALE) (dry or wet), gas oxidation + wet etching, etc. are performed by using typical APCVD, UHVCVD, LPCVD, RTCVD, PECVD, or oxide growth, etc. When the silicon nitride is etched to form a groove, patterning means such as a photoresist mask and the like are required to be introduced.

In addition, after the silicon nitride layer is etched, annealing treatment (RTN) can be carried out on the silicon nitride to eliminate defects generated by etching.

One of the preferred embodiments of the present invention is as follows.

Example fabrication of strained GeSiOI substrate

Forming a support substrate

A first step of providing a first Si (100) substrate 101; depositing a first silicon oxide layer 102 on a first Si (100) substrate 101 resulting in the structure shown in fig. 1;

secondly, depositing a silicon nitride layer 103 on the first silicon oxide layer 102 to obtain the structure shown in fig. 2; means of deposition include, but are not limited to, APCVD, UHVCVD, LPCVD, RTCVD, PECVD, or oxide growth, among others;

thirdly, etching the silicon nitride layer 103 to form a structure as shown in fig. 3, forming a plurality of grooves 103b, penetrating the silicon nitride, dividing the silicon nitride into a plurality of separating strips 103a, and then annealing to eliminate defects and the like generated by etching;

and fourthly, depositing a second silicon oxide layer again, filling the groove and covering the silicon nitride, wherein the shape of the donor substrate structure is as shown in the figure 4, the deposition method is not limited in the present, and the deposition method can be selectively growing a silicon oxide layer, or can be depositing silicon oxide and then performing surface smoothing (such as CMP and the like).

Forming a donor substrate

A first step, as shown in fig. 5, of providing a second Si (100) substrate 201; epitaxial silicon germanium (Ge) on a second Si (100) substrate 201_1-xSi_x(0 < x < 1)) layer 202;

second, Al is grown on the epitaxial SiGe layer 202₂O₃Layer 203 (or other high-k dielectric with a dielectric constant higher than that of silicon oxide, which may primarily reduce interfacial defects and enhance adhesion) forms a donor substrate as shown in fig. 5.

Bonding and thinning

With the second silicon oxide layer 104 and Al₂O₃Layer 203 is a bonding surface, and the support substrate and the donor substrate are bonded to obtain the structure shown in fig. 6; then removing the silicon substrate of the donor substrate, and removing the Ge_1-xSi_xThinning the layer to obtain a strained GeSiOI substrate, such as the structure shown in FIG. 7; the thinning of the Si substrate layer is not limited, and the combination of Grading (grinding and polishing), a dry method, a wet method and CMP is preferred; ge thinning is not limited, and dry or wet Atomic Layer Etching (ALE), dry and wet methods and the like can be adopted.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. a strained GeSiOI substrate, is characterized in that, comprises sequentially stacked from bottom to top:

silicon substrate,

first silicon oxide layer,

a plurality of silicon nitride spacers, the spacers are distributed on the surface of the first silicon oxide layer;

A second silicon dioxide layer, the second silicon dioxide layer fills the gaps between the spacers and covers the spacers;

Ge _1-x _Six layer;

where 0<x<1.

2 . The strained GeSiOI substrate according to claim 1 , further comprising a high-k dielectric layer between the second silicon dioxide layer and the Ge _1-x Si _x layer. 3 .

3. The strained GeSiOI substrate according to claim 2, wherein the high-k dielectric layer is aluminum oxide.

4 . The strained GeSiOI substrate according to claim 1 , wherein 0<x≦0.3. 5 .

5 . The strained GeSiOI substrate of claim 1 , wherein the spacers are distributed in parallel. 6 .

6. The strained GeSiOI substrate according to any one of claims 1-5, wherein the silicon substrate is a silicon (100) substrate.

7. a preparation method of strained GeSiOI substrate, is characterized in that, comprising:

To make the support substrate:

A first silicon substrate is provided, a first silicon oxide layer and a silicon nitride layer are sequentially deposited on the first silicon substrate; the silicon nitride layer is patterned to form a plurality of discrete silicon nitride spacers, adjacent to each other A trench is formed between the silicon nitride spacers, the trench penetrates the silicon nitride layer; and a second silicon dioxide layer is formed, and the second silicon dioxide layer fills the trench and covers the silicon nitride the upper surface of the divider;

To make the donor substrate:

providing a second silicon substrate, and epitaxial Ge _1-x Si _x layer on the second silicon substrate, 0<x<1;

Bond:

Using the second silicon dioxide layer and the Ge _1-x Si _x layer as bonding surfaces, the support substrate and the donor substrate are bonded, and then the second silicon substrate is removed, optionally The Ge _1-x Si _x layer is thinned to obtain a strained GeSiOI substrate.

8 . The manufacturing method according to claim 7 , wherein, in the process of manufacturing the donor substrate, after the epitaxial Ge _1-x Si _x layer, the method further comprises: depositing a high-k dielectric layer; 9 .

In addition, during the bonding, the second silicon dioxide layer and the high-k dielectric layer are used as bonding surfaces.

9 . The manufacturing method according to claim 7 , wherein, in the process of manufacturing the supporting substrate, after etching the silicon nitride layer and before forming the second silicon dioxide layer, the method further comprises: annealing. 10 . Handle silicon nitride.