CN112614842A

CN112614842A - Memory device and method of manufacturing the same

Info

Publication number: CN112614842A
Application number: CN202011055446.6A
Authority: CN
Inventors: 李南宰
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2019-10-04
Filing date: 2020-09-29
Publication date: 2021-04-06

Abstract

Embodiments of the present disclosure relate to a memory device and a method of manufacturing the same. A memory device and a method of manufacturing a memory device, the memory device comprising: a stack structure having a cell region and a reduced region in the stack structure and formed by alternately stacking insulating layers and conductive layers; a vertical channel structure formed through the stacked structure in the cell region; support structures formed to pass through the stacked structures in the reduced region and having different heights depending on the stacked heights of the reduced region, each of the support structures having a vertical channel structure; an etch-resistant layer formed over the stacked structure and including carbon; and a contact plug formed through the etch-prevention layer and coupled to the conductive layer.

Description

Memory device and method of manufacturing the same

Cross Reference to Related Applications

This application is a continuation of the section of U.S. patent application No.16/880678 filed on 21/5/2020, which claims priority from korean patent application 10-2019-. The disclosures of the above applications are incorporated herein by reference in their entirety.

Technical Field

Various embodiments of the present disclosure relate generally to a memory device and a method of manufacturing the same, and more particularly, to a memory device including memory cells stacked in a direction perpendicular to a substrate and a method of manufacturing the same.

Background

The memory device may include volatile memory that stores data that is lost when power is interrupted. The memory device may also include a non-volatile memory, the data stored by which is retained even if power is interrupted.

With the increasing popularity of portable electronic devices, such as cellular phones and notebook computers, there is a need for non-volatile memory devices with increased capacity and integration.

There is limited potential to further increase the integration of two-dimensional non-volatile memory devices that include memory cells formed on a substrate in a single layer. Accordingly, a three-dimensional (3D) nonvolatile memory device including memory cells stacked in a vertical direction on a substrate has been proposed.

Disclosure of Invention

According to an embodiment of the present disclosure, a memory device is provided. The memory device includes a stacked structure having a cell region and a reduced region in the stacked structure and formed by alternately stacking insulating layers and conductive layers, support structures formed through the stacked structure in the reduced region, and the support structures having different heights depending on the stacked height of the reduced region, each of the support structures having a vertical channel structure, an etch-resistant layer formed over the stacked structure and including carbon, and a contact plug formed through the etch-resistant layer and coupled to the conductive layer.

According to an embodiment of the present disclosure, a method of manufacturing a memory device is provided. The method comprises the following steps: alternately stacking insulating layers and conductive layers in the cell region and the reduced region; and forming a stacked structure having a stepped structure in the reduced region; forming an etch-resistant layer including carbon along an upper surface of the stack structure; forming an interlayer insulating layer over the etch-resistant layer; performing a first etching process of forming a contact hole for exposing a portion of the etch-prevention layer in the cell region and the reduced region of the interlayer insulating layer; performing a second etching process of removing the etch-resistant layer exposed through the contact hole; and forming a contact plug in the contact hole.

According to an embodiment of the present disclosure, a method of manufacturing a memory device is provided. The memory device includes: forming a stacked structure formed by alternately stacking first material layers and second material layers; sequentially forming an etching prevention layer and an interlayer insulating layer on the stacked structure; forming a slit region vertically penetrating the interlayer insulating layer, the etch resist layer, and the stack structure; performing an etching process to remove the second material layer exposed through the slit region; forming a third material layer in the region where the second material layer is removed; and forming a fourth material layer in the slit region. The etch-prevention layer may be formed of a material having an etch selectivity different from that of the second material layer.

Drawings

Fig. 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

Fig. 2 is a diagram for describing an arrangement between a memory cell array and peripheral circuits according to an embodiment.

Fig. 3 is a diagram illustrating a memory cell array including memory blocks each having a three-dimensional structure according to an embodiment.

Fig. 4 is a diagram for describing a configuration of a memory block and a connection relationship between the memory block and a peripheral circuit according to an embodiment.

Fig. 5 is a diagram illustrating a layout of a cell region and a reduced region according to an embodiment.

Fig. 6 to 25 are diagrams for describing a method of manufacturing a memory device according to a first embodiment of the present disclosure.

Fig. 26 is a diagram illustrating the structure of a complete memory device according to the first embodiment of the present disclosure.

Fig. 27 to 30 are diagrams illustrating a method for describing a method of manufacturing a memory device according to a second embodiment of the present disclosure.

Fig. 31 to 38 are diagrams for describing a method of manufacturing a memory device according to a third embodiment of the present disclosure and a structure of a completed memory device.

Fig. 39 is a block diagram illustrating an example of a memory system including a memory device according to an embodiment of the present disclosure.

Fig. 40 is a block diagram illustrating an example of a memory system including a memory device according to an embodiment of the present disclosure.

Detailed Description

Fig. 1 is a diagram illustrating a memory device 1100 according to an embodiment of the disclosure.

Referring to fig. 1, a memory device 1100 may include a memory cell array 100 configured to store data; and a peripheral circuit 110 configured to perform a program operation, a read operation, or an erase operation of the memory cell array 100.

The memory cell array 100 may include a plurality of memory blocks, each of which includes nonvolatile memory cells. The local line LL may be coupled to each of the memory blocks. The bit lines BL may be commonly coupled to each of the memory blocks.

Peripheral circuits 110 may include control logic 111, voltage generator 112, row decoder 113, page buffer bank 114, column decoder 115, and input/output circuits 116.

The control logic 111 may control the voltage generator 112, the row decoder 113, the page buffer group 114, the column decoder 115, and the input/output circuit 116 in response to a command CMD and an address ADD. For example, the control logic 111 may output an operation signal OPS and a page buffer control signal PBSIG in response to a command CMD, and output a row address RADD and a column address CADD in response to an address ADD. The control logic 111 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 111 may be control logic circuitry that operates in accordance with an algorithm and/or a processor that executes control logic code.

The voltage generator 112 may generate an operation voltage Vop required for a program operation, a read operation, or an erase operation in response to the operation signal OPS. For example, the voltage generator 112 may generate and output an operation voltage Vop, such as a program voltage, a read voltage, an erase voltage, and a pass voltage.

The row decoder 113 may transmit the operation voltage Vop to the selected memory block through the local line LL in response to the row address RADD.

The page buffer group 114 may include a plurality of page buffers coupled to the bit lines BL. The page buffer group 114 may temporarily store data in response to a page buffer control signal PBSIG during a program operation or a read operation.

The column decoder 115 may transfer data between the page buffer group 114 and the input/output circuit 116 in response to a column address CADD.

Input/output circuit 116 may receive commands CMD and addresses ADDR from external devices and transmit the commands CMD and addresses ADDR to control logic 111. The input-output circuit 116 may transmit DATA received from an external device to the column decoder 115 during a program operation and output DATA received from the column decoder 115 to the external device during a read operation.

Fig. 2 is a diagram for describing an arrangement between the memory cell array 100 and the peripheral circuit 110 according to the embodiment.

Referring to fig. 2, the memory cell array 100 and the peripheral circuit 110 described with reference to fig. 1 may be arranged in various structures. For example, in the case where the substrate is disposed in parallel with the X-Y direction, the memory cell array 100 and the peripheral circuit 110 may be disposed in parallel with each other along the X-Y direction (as indicated by reference numeral 210). Alternatively, the memory cell array 100 may be disposed over the peripheral circuit 110 in a direction perpendicular to the substrate (Z direction) (as indicated by reference numeral 220). In other words, the peripheral circuit 110 may be disposed between the substrate and the memory cell array 100.

Referring to fig. 3, in the case where the memory cell array 100 includes memory blocks BLK1 through BLKn each having a three-dimensional structure, the memory blocks BLK1 through BLKn may be arranged in the Y direction. The Y direction may be a direction in which the bit line BL of fig. 1 extends.

Although fig. 3 illustrates that the memory cell array 100 includes a single plane, the memory cell array 100 may include a plurality of planes. The plurality of planes may be arranged in the X direction. The memory blocks included in each plane may be arranged in the corresponding plane in the Y direction.

Fig. 4 is a diagram for describing the configuration of the memory block BLKn and the connection relationship between the memory block BLKn and the peripheral circuit 110 according to the embodiment.

The plurality of memory blocks BLK1 through BLKn described with reference to fig. 3 may have the same configuration. Fig. 4 illustrates any one memory block BLKn as a representative example of the plurality of memory blocks BLK1 through BLKn.

Referring to fig. 4, a memory block BLKn having a three-dimensional structure may include a cell region CR including memory cells; and a reduced region SR provided to electrically couple the peripheral circuit 110 with the cell region CR. For example, the cell region CR may include a plurality of vertical strings obtained by stacking memory cells and selection transistors. The reduced area SR may include ends of a plurality of gate lines coupled to the memory cells and the selection transistors. For example, in the reduced area SR, the gate lines may be stacked in a staircase structure in which the extension length of the gate lines disposed at relatively lower positions is longer than the extension length of the gate lines disposed at relatively higher positions. The exposed portion of the gate line having the stepped structure may be coupled to the peripheral circuit 110 through a contact plug.

In the case where the peripheral circuit 110 and the memory block BLKn are arranged in the horizontal direction (X direction) as indicated by reference numeral 210, a plurality of lines ML for electrically coupling the reduced region SR with the peripheral circuit 110 may be formed. For example, in the structure denoted by reference numeral 210, the plurality of lines ML may extend in the X direction, and may be disposed at positions spaced apart from each other in the Y direction.

In the case where the peripheral circuit 110 is disposed below (in the Y direction) the memory block BLKn as indicated by reference numeral 220, a plurality of lines ML for electrically coupling the reduced region SR with the peripheral circuit 110 may extend in the Z direction and may be disposed at positions spaced apart from each other in the Y direction.

Fig. 5 is a diagram illustrating a layout of the cell region CR and the reduced region SR according to an embodiment.

Referring to fig. 5, a plurality of vertical channel structures VCH may be formed in the cell region CR. A plurality of support structures SP may be formed in the reduced area SR. The vertical channel structure VCH may vertically pass through the structure stacked in the Z direction in the cell region CR, and include a plurality of memory cells. The support structure SP may support a stack structure formed in the memory block.

The support structure SP may vertically pass through the structures stacked in the Z direction in the reduced region SR, and have the same structure as that of the vertical channel structure VCH.

In the embodiment of the present disclosure, since the support structure SP is formed simultaneously with the vertical channel structure VCH, a separate manufacturing step for forming the support structure SP is not required. Accordingly, in the memory device according to the embodiment of the present disclosure, the support structure SP may reduce or prevent the memory block from being tilted. Since the support structure SP is formed simultaneously with the vertical channel structure VCH, the manufacturing process can be facilitated.

The number of the vertical channel structures VCH and the support structures SP is not limited to the number shown in fig. 5, and may vary according to the size of the memory block or the number of stacked layers included in the stacked structure.

In the following embodiments, the method of manufacturing the structure of the vertical channel structure VCH and the cell region CR is described with reference to a cross section taken along the line a-B; and the method of manufacturing the structure of the support structure SP and the reduced area SP is described with reference to a cross-section taken along line C-D.

Fig. 6 to 25 are diagrams for describing a manufacturing method of a memory device according to a first embodiment of the present disclosure.

Referring to fig. 6, in the first embodiment, a single stack structure is illustrated, in which one stack structure STR is formed on a substrate 61.

The stacked structure STR may be formed on a substrate 61. The base 61 may be a semiconductor substrate and include lower structures such as a peripheral circuit and a source structure.

The stacked structure STR may include first material layers 62 and second material layers 63 that are alternately stacked. A first material layer 62 may be provided to insulate the stacked gate electrodes from each other. A second material layer 63 may be provided to form gate electrodes such as memory cells and select transistors. The second material layer 63 may be made of a material having a high etching selectivity with respect to the first material layer 62. For example, the second material layer 63 may be a sacrificial layer including nitride or the like, and the first material layer 62 may be an insulating layer including oxide or the like. A second material layer 63 may be formed at the uppermost end of the stacked structure STR.

Referring to fig. 7, vertical vias VHc and VHs may be formed vertically through the stacked structure STR. For example, in the cell region CR and the reduced region SR, a mask pattern (not shown) having a plurality of openings may be formed on the second material layer 63 formed on the uppermost end of the stacked structure STR. Portions of the stacked structure STR exposed through the openings may be etched. An etching process may be performed until the substrate 61 is exposed.

Through subsequent processes, a vertical channel structure (VCH of fig. 5) may be formed in the vertical hole VHc formed in the cell region CR, and a support structure (SP of fig. 5) may be formed in the vertical hole VH formed in the reduced region SR. Accordingly, as shown in fig. 5, the vertical holes VHc formed in the cell region CR may be arranged in a zigzag pattern, and the vertical holes VHs formed in the reduced region SR may be arranged in a matrix pattern along the X-direction and the Y-direction. However, the vertical holes VHc and VHs may be arranged in various patterns as well as the pattern shown in fig. 5, and the arrangement pattern and the pattern of the vertical holes VHc and VHs according to one embodiment are not limited to the pattern shown in fig. 5.

Referring to fig. 8, a vertical channel structure VCH may be formed in the vertical hole VHc of the cell region CR. The support structures SP1 through SP5 may be formed in the vertical holes VHs of the reduced region SR. The support structures SP1 through SP5 may have the same structure as that of the vertical channel structure VCH, and may be formed simultaneously with the vertical channel structure VCH.

The vertical channel structure VCH and the support structures SPl to SP5 formed in the cell region CR may each include a memory layer 64, a channel layer 65, a vertical insulating layer 66, and a cap layer 67, which are formed in order of proximity to the inner surfaces of the vertical holes VHc, VHs. The memory layer 64 may be formed in a hollow pillar shape along the inner surfaces of the vertical holes VHc, VHs. The channel layer 65 may be formed in a hollow cylindrical shape along an inner surface of the memory layer 64. The vertical insulating layer 66 may be provided in a pillar form, and the space defined by the channel layer 65 is filled with the vertical insulating layer 66. Although not illustrated, in various embodiments, the channel layer 65 may be provided in a pillar form. In this case, the vertical insulating layer 66 is not formed. A cap layer 67 may be formed on the channel layer 65 and the vertical insulating layer 66, and surrounded by the memory layer 64.

In cell region CR, portions of each vertical channel structure VCH adjacent to second material layer 63 may function as memory cells. The support structures SP1 to SP5 formed in the reduced region SR may be used to support the stacked structure STR.

The structure of the vertical channel structure VCH and the support structures SP1 to SP5 are described in more detail with reference to the schematic view 80. The memory layer 64 may include a barrier layer 64-1, a trapping layer 64-2, and a tunnel insulating layer 64-3, which are formed in order of proximity to the vertical holes VHc, VHs.

The barrier layer 64-1 may be formed of an insulating layer including oxide or the like. The trapping layer 64-2 may be made of a material capable of trapping charges, such as polysilicon, nitride, variable resistance material, or phase change material. The tunnel insulating layer 64-3 may be formed of an insulating layer including oxide or the like. The channel layer 65 may be formed of polysilicon. The vertical insulating layer 66 may be formed of an insulating layer including oxide or the like. Data may be stored in the vertical channel structure VCH formed in the cell region CR. Specifically, data may be stored in the trapping layer 64-2 of the vertical channel structure VCH.

Referring to fig. 9, a reduction process of exposing each of the second material layers 63 in the reduced region SR may be performed. Specifically, the reduction process may include a plurality of mask pattern forming steps and etching steps to form a stair step structure having a plurality of steps each having a pair of the first material layer 62 and the second material layer 63 in the reduced region SR. Fig. 9 illustrates a method of forming the first mask pattern 1MP for forming the first stepped structure.

In the mask pattern forming step, the first mask pattern 1MP may be formed on the entire cell region CR and a portion of the reduced region SR. The first mask pattern 1MP may include a first opening 1OP through which the target material to be etched is exposed in the reduced region SR. For example, the first mask pattern 1MP may be formed to cover the entire cell region CR and a portion of the reduced region SR. In other words, the second to fifth support structures SP2 to SP5 and a portion of the first material layer 62-1 formed at the highest position in the first and second material layers 62 and 63 may be exposed through the first opening 1OP of the first mask pattern 1 MP.

Referring to fig. 10, at the etching step, an etching process may be performed such that the second material 63-1 is exposed by removing the uppermost portion of the first material layer 62-1 exposed through the first opening 10P. The etching process may be performed in an anisotropic etching manner such that the exposed portion is removed only through the first opening 10P. An etching process using the first mask pattern 1MP may be performed until the second material layer 63-1 is exposed in the reduced region SR.

In the etching step, when the exposed portion of the first material layer 62-1 is removed, the upper portions of the second to fifth support structures SP2 to SP5 exposed through the first opening 10P may also be removed. Although fig. 10 illustrates that the upper surfaces of second through fifth support structures SP2 through SP5 and the upper surface of second material layer 63-1 are flush with each other, the upper portions of second through fifth support structures SP2 through SP5 may remain non-flush with the upper surface of second material layer 63-1. For example, the upper surfaces of the second through fifth support structures SP2 through SP5 may remain protruding from the upper surface of the second material layer 63-1. In addition, heights of remaining portions of the respective layers in each of the second to fifth support structures SP2 to SP5 may be different from each other according to etch selectivity of the respective layers. In the embodiment of the present disclosure, the first to fifth support structures SP1 to SP5 formed in the reduced region SR perform only the function of supporting the stacked structure STR without performing an electrical operation. In this case, the shapes of the remaining portions of the first to fifth support structures SP1 to SP5 may be changed.

Referring to fig. 11, if the second material layer 63-1 is exposed in the reduced region SR, the first mask pattern (1 MP of fig. 10) may be removed and a second mask pattern 2MP including a second opening 2OP may be formed. To form the stepped structure, the width of the second opening 2OP of the second mask pattern 2MP may be smaller than the width of the first opening 1 OP. For example, the second mask pattern 2MP may be formed to cover the entire cell region CR and a portion of the reduced region SR. In other words, the third to fifth support structures SP3 to SP5 and a portion of the second material layer 63-1 formed at the highest position in the first and second material layers 62 and 63 may be exposed through the second opening 2OP of the second mask pattern 2 MP.

Referring to fig. 12, an etching process may be performed such that second material layer 63-2 is exposed by removing a portion of uppermost second material layer 63-1 exposed through second opening 2OP and a portion of first material 62 formed under second material 63-1. The etching process may be performed in an anisotropic etching manner such that the exposed portion is removed only through the second opening 2 OP. An etching process using the second mask pattern 2MP may be performed until the second material layer 63-2 is exposed in the reduced region SR.

In the etching step, when the exposed portions of the second material 63-1 and the first material layer 62 are removed, upper portions of the third to fifth support structures SP3 to SP5 exposed through the second opening 2OP may also be removed. Although fig. 12 also illustrates that the upper surfaces of the third through fifth support structures SP3 through SP5 are flush with the upper surface of the second material layer 63-2, as described with reference to fig. 10, in other embodiments of the present disclosure, the shapes of the exposed portions of the third through fifth support structures SP3 through SP5 are not necessarily flush with the upper surface of the second material layer 63-2.

Referring to fig. 13, the second mask pattern 2MP may be removed. According to the mask pattern forming step and the etching step described with reference to fig. 9 to 12, a stepped structure may be formed in the reduced region SR by using a mask pattern having an opening whose width is gradually reduced. For example, a stair step structure may be formed in reduced region SR in which second material layer 63-1, 63-2, 63-3, 63-4, … is exposed on the corresponding step. Since the shrink process is performed only in the shrink region SR, the vertical channel structures VCH formed in the cell region CR may have the same height. Still further, in the reduced region SR, the support structures passing through the same layer may have the same height, but the support structures passing through different layers may have different heights. For example, although the second support structures SP2 may have the same height, the second support structure SP2 may have a different height from the structure of the third support structure SP 3.

Referring to fig. 14, an etch-prevention layer 90 may be formed along upper surfaces of the cell region CR and the reduced region SR. The etch-preventing layer 90 may be formed of a material having a different etch selectivity from the second material layer 63 or the first interlayer insulating layer (91 of fig. 15) to be formed during a subsequent process. In other words, the etching prevention layer 90 may be formed of a material having a different etching rate from the second material layer 63 or the first interlayer insulating layer (91 of fig. 15). To this end, the etch resist layer 90 may be formed of a layer including carbon (e.g., a SiCN layer). If the etch-preventing layer 90 has a different etch selectivity from the second material layer 63, the etch-preventing layer 90 may remain during a subsequent etching process for removing the second material layer 63, so that the thickness of the etch-preventing layer 90 does not need to be increased. If the etch-preventing layer 90 is formed of a material having a different etch selectivity from the first interlayer insulating layer (91 of fig. 15) to be formed during a subsequent process, a phenomenon in which a conductive layer for a word line is exposed through a contact hole may be prevented during an etch process of forming the contact hole. In addition, since it is not necessary to increase the thickness of the etching prevention layer 90, the thickness of the etching prevention layer 90 may be reduced. For example, if it is assumed that the second material layers 63 each have the first thickness 1TC and the etching prevention layer 90 has the second thickness 2TC, the second thickness 2TC may be the same as the first thickness 1 TC. In other words, the etch preventing layer 90 may be formed in the same thickness as the second material layer 63.

Referring to fig. 15, a first interlayer insulating layer 91 may be formed over the etch resist layer 90. The first interlayer insulating layer 91 may be formed of an insulating layer. For example, the first interlayer insulating layer 91 may be formed of oxide.

Referring to fig. 16, a slit region SLR may be formed in the reduced region SR. The slit region SLR may be implemented as a trench extending in the X direction and etched in the Z direction in the reduced region SR. For example, a mask pattern (not shown) from which the slit region SLR is exposed may be formed on the cell region CR and the reduced region SR, and a trench from which the substrate 61 is exposed may be formed by performing an etching process using the mask pattern (not shown). An etching process for removing the second material layer 63 exposed through the inside of the trench may be performed. A wet etching process may be performed to easily remove the second material layer 63 formed between the first material layers 62. The wet etching process may be performed using an etchant having an etch selectivity to the second material layer 63 that is higher than an etch selectivity of the etch-prevention layer 90. For example, a phosphoric acid solution may be used as the etchant. If the wet etching process is performed using an etchant having a difference in etching selectivity between the second material layer 63 and the etching prevention layer 90, the etching prevention layer 90 may be maintained when the second material layer 63 is removed.

Thereafter, the first conductive layer 68 for the word line may be loaded into the region where the second material layer 63 has been removed. The first conductive layer 68 may be formed of polysilicon, tungsten, molybdenum, or a combination thereof. After the first conductive layer 68 is formed, a trench may be formed by etching the slit region SLR, and a slit may be formed by filling the trench with an insulating material.

Referring to fig. 17, a third mask pattern 3MP may be formed on the first interlayer insulating layer 91. The third mask pattern 3MP may be formed of a pattern covering the entire cell region CR, and wherein the opening OP is formed in the reduced region SR. A portion of the first interlayer insulating layer 91 of the reduced region SR may be exposed through the opening OP.

Referring to fig. 18, an etching process of removing portions of the first interlayer insulating layer 91 exposed from the third mask pattern 3MP may be performed. The etching process may be an anisotropic etching process such that only a portion of the first interlayer insulating layer 91 exposed through the opening OP is removed. The first contact hole H1 may be formed in a portion of the first interlayer insulating layer 91 that has been removed through an etching process. The etching process may be performed using an etching gas having a higher etching rate of the first interlayer insulating layer 91 than the etching rate of the etching prevention layer 90. Accordingly, the etching prevention layer 90 may be exposed first through the first contact hole H1 in the uppermost region in the stack structure STR, and the etching prevention layer 90 may be sequentially exposed through the first contact hole H1 in the next uppermost region. In this way, when the etching process for forming the first contact hole H1 is performed, even though the portion 161 of the etch-prevention layer 90 is relatively rapidly exposed through the first contact hole H1, the first conductive layers 68-1, 68-2, … … formed in the uppermost layer of the corresponding step may not be exposed by the etch-prevention layer 90 through the first contact hole H1. In other words, the first conductive layers 68-1, 68-2, … … formed in the uppermost layer of the respective steps in the reduced area may be protected by the etch preventing layer 90 during the etching process of forming the first contact hole H1.

Referring to fig. 19, if all of the first contact holes H1 are formed in the reduced region SR, the etch-preventing layer 90 may be exposed through the bottom of the first contact holes H1.

Referring to fig. 20, an etching process of removing the etch-resistant layer 90 exposed through the first contact hole H1 may be performed. The etching process may be performed using an etching gas having a higher etching selectivity to the etching prevention layer 90 than to the first interlayer insulating layer 91 and the first conductive layer 68. An etching process may be performed until the first conductive layers 68-1, 68-2, … … disposed in the uppermost layer of the respective step are exposed through the first contact hole H1.

Referring to fig. 21, a first reduced contact plug 1SRP may be formed in each first contact hole H1. The first reduced contact plug 1SRP may include a first barrier layer 93 and a second conductive layer 94. For example, after the first barrier layer 93 is formed along the inner surface of each of the first contact holes H1, the inside of each of the first contact holes H1 may be filled with the second conductive layer 94. The first barrier layer 93 may be formed of TiN. The second conductive layer 94 may be formed of a conductive material such as polysilicon, tungsten, or molybdenum. The first reduced contact plug 1SRP may be formed to adjoin the first conductive layers 68-1, 68-2, … … disposed in the uppermost layer of the corresponding step through the first contact hole H1. During a program, read or erase operation, the first reduced contact plug 1SRP may be used to transmit an operating voltage (Vop of fig. 1) generated in a voltage generating circuit (112 of fig. 1) to the first conductive layer 68. After forming the second conductive layer 94, a planarization process may be performed to electrically disconnect the first reduced contact plugs 1 SRPs formed in different regions from each other.

Referring to fig. 22, a second interlayer insulating layer 95 and a fourth mask pattern 4MP may be successively formed on the first reduced contact plug 1SRP and the first interlayer insulating layer 91. For example, after forming the second interlayer insulating layer 95 on the first reduced contact plug 1SRP and the first interlayer insulating layer 91, a fourth mask pattern 4MP may be formed over the second interlayer insulating layer 95. The second interlayer insulating layer 95 may be formed of the same material as the first interlayer insulating layer 91. For example, the second interlayer insulating layer 95 may be formed of oxide. The fourth mask pattern 4MP may have a pattern in which an opening OP is formed in the cell region CR and the reduced region SLR. In the cell region CR, an opening OP may be formed in a region in which the vertical channel structure VCH is formed. In the reduced region SR, an opening OP may be formed in a region in which the first reduced contact plug 1SRP is formed.

Referring to fig. 23, an etching process of removing portions of the second interlayer insulating layer 95 and the first interlayer insulating layer 91 exposed from the fourth mask pattern 4MP may be performed. The etching process may be an anisotropic etching process such that the second interlayer insulating layer 95 exposed through the opening OP and the first interlayer insulating layer 91 exposed by removing the second interlayer insulating layer 95 are removed. During the etching process, the second contact hole H2 is formed in the cell region CR and the reduced region SR. The second contact hole H2 formed in the cell region CR may be formed to expose the etch-preventing layer 90. The second contact hole H2 formed in the reduced region SR may be formed to expose an upper surface of the first reduced contact plug 1 SRP.

Referring to fig. 24, an etching process of removing the etch-resistant layer 90 exposed through the second contact hole H2 may be performed. The etching process may be performed using an etching gas having a higher etching selectivity to the etch preventing layer 90 than to the first and second

interlayer insulating layers

91 and 95 and the first reduced contact plug 1 SRP. An etching process may be performed until the vertical channel structure VCH is exposed through the second contact hole H2.

Referring to fig. 25, a cell contact plug CRP may be formed in each of the second contact holes H2 formed in the second contact holes H2 in the cell region CR, and a second reduced contact plug 2SRP may be formed in each of the second contact holes H2 formed in the second contact holes H2 in the reduced region SR. The cell contact plug CRP and the second reduced contact plug 2SRP may be simultaneously formed. For example, the cell contact plug CRP and the second reduced contact plug 2SRP may include the second barrier layer 97 and the third conductive layer 98. For example, after the second barrier layer 97 is formed along the inner surface of each of the second contact holes H2, the inside of each of the second contact holes H2 may be filled with the third conductive layer 98. The second barrier layer 97 may be formed of TiN. The third conductive layer 98 may be formed of a conductive material such as polysilicon, tungsten, or molybdenum. The cell contact plug CRP may be formed to adjoin on the vertical channel structure VCH. The second reduced contact plug 2SRP may be formed to abut on the first reduced contact plug 1 SRP.

The bit line BL may be formed over the cell contact plug CRP, and the metal line ML may be formed over the second reduced contact plug 2 SRP. The bit lines BL may be coupled to the page buffer group (114 of fig. 1), and the metal lines ML may be coupled to the local lines (LL of fig. 1).

After the third conductive layer 98 is formed, a planarization process may be performed to electrically disconnect the cell contact plug CRP and the second reduced contact plug 2SRP, which are formed in different regions, from each other.

As described with reference to fig. 6 to 25, after the vertical channel structure VCH and the support structures SP1 to SP5 are simultaneously formed in the cell region CR and the reduced region SR, a reduction process of forming a stepped structure in the reduced region SR is performed. Therefore, a separate process of forming the support structures SP1 through SP5 may not be required. Accordingly, the phenomenon of the memory block tilting may be reduced or prevented by using the support structures SP1 through SP5 without performing a separate additional process.

In addition, since the etch-preventing layer 90 is formed in the cell region CR and the reduced region SR before the first contact hole H1 is formed, the first conductive layer 68 for the word line may be protected during the etching process of forming the first contact hole H1.

Referring to fig. 26, each of the support structures SP1 through SP5 formed by the manufacturing method described with reference to fig. 6 through 25 may be formed to pass through the edge region of the corresponding step in the vertical direction (Z direction). When the reducing process of forming the stepped structure in the reduced region SR is completed, the first to fifth support structures SP1 to SP5 formed in the reduced region SR may have different heights according to the shape of the stack structure STR. For example, the first height H1 of the first support structure SP1 may be equal to the height of the vertical channel structure VCH. The second height H2 of the second support structure SP2 may be less than the first height H1. In this way, the first to fifth support structures SP1 to SP5 may have different heights H1 to H5. Herein, the term "height" refers to a length from the bottom of each of the first to fifth support structures SP1 to SP5 to the top thereof.

Further, if the first to fifth support structures SP1 to SP5 are formed to abut on the ends of the respective steps, the distance DS between the first to fifth support structures SP1 to SP5 and the reduced contact plugs SRP formed of the first and second reduced contact plugs 1SRP and 2SRP may be increased. Therefore, the manufacturing process can be facilitated. In addition, when a voltage is applied to the reduced contact plugs SRP during a subsequent operation, an electrical coupling phenomenon that may occur between the reduced contact plugs SRP and the first to fifth support structures SP1 to SP5 may be prevented. For example, in the case where the distance DS between the reduced contact plug SRP and the first to fifth support structures SP1 to SP5 is relatively small, coupling may occur between the reduced contact plug SRP and the first to fifth support structures SP1 to SP 5. Accordingly, reducing the increase in the distance DS between the contact plug SRP and the first to fifth support structures SP1 to SP5 may prevent the reliability of the memory device from being degraded.

Fig. 27 to 30 are diagrams for describing a method of manufacturing a memory device according to a second embodiment of the present disclosure.

In the drawings shown in fig. 27 to 30, the same reference numerals are used to denote the same components as those of the first embodiment, and the reference numerals used in fig. 27 to 30 do not indicate the order of forming the components.

In the second embodiment, the cell contact plug CRP and the reduced contact plug SRP may be simultaneously formed in the cell region CR and the reduced region SR. In the second embodiment, the description of the steps before the steps of forming the cell contact plugs CRP and the reduced contact plugs SRP is the same as the steps of the diagrams shown in fig. 6 to 16 of the first embodiment. Therefore, in the second embodiment, the overlapping description with the first embodiment is omitted. Fig. 27 shows a structure corresponding to a step after the step of forming the structure shown in fig. 16.

Referring to fig. 27, a fifth mask pattern 5MP may be formed on the first interlayer insulating layer 91. The fifth mask pattern 5MP may be formed of a pattern in which the opening OP is formed in the cell region CR and the reduced region SLR. For example, in the cell region CR, an opening OP may be formed in a region in which the vertical channel structure VCH is formed. In the reduced region SR, an opening OP may be formed in a region between the first to fifth support structures SP1 to SP 5.

Referring to fig. 28, an etching process of removing portions of the first interlayer insulating layer 91 exposed from the fifth mask pattern 5MP may be performed. The etching process may be an anisotropic etching process such that the first interlayer insulating layer 91 exposed through the opening OP is removed. During the etching process, the first contact hole H1 may be formed in the cell region CR and the reduced region SR. An etching process may be performed until the etch preventing layer 90 is exposed through the first contact hole H1. Since the etch-preventing layer 90 may be left without being etched during the etching process, the first conductive layer 68-1, 68-2, … … may be protected by the etch-preventing layer 90 until the etch-preventing layer 90 is exposed through the first contact hole H1 having the maximum depth.

Referring to fig. 29, an etching process of removing the etch-resistant layer 90 exposed through the first contact hole H1 may be performed. The etching process may be performed using an etching gas having a higher etching selectivity to the etching prevention layer 90 than to the first interlayer insulating layer 91 and the first conductive layers 68-1, 68-2, … …. An etching process may be performed until the upper surfaces of the vertical channel structures VCH of the cell regions CR and the first conductive layers 68-1, 68-2, … … disposed in the uppermost ends of the respective steps in the reduced region SR are exposed.

Referring to fig. 30, a cell contact plug CRP may be formed in each of the first contact holes H1 formed in the cell region CR, and a reduced contact plug SRP may be formed in each of the first contact holes H1 formed in the reduced region SR. The cell contact plug CRP and the reduced contact plug SRP may be simultaneously formed. For example, the cell contact plug CRP and the reduced contact plug SRP may include a first barrier layer 93 and a second conductive layer 94. For example, after the first barrier layer 93 is formed along the inner surface of each of the first contact holes H1, the inside of each of the first contact holes H1 may be filled with the second conductive layer 94. The first barrier layer 93 may be formed of TiN. The second conductive layer 94 may be formed of a conductive material such as polysilicon, tungsten, or molybdenum. The cell contact plug CRP may be formed to adjoin on the vertical channel structure VCH. Reduced contact plugs SRP may be formed to abut on first conductive layers 68-1, 68-2, … …, respectively.

The cell contact plug CRP may electrically couple the vertical channel structure VCH and a bit line to be formed during a subsequent process. During a program, read or erase operation, the reduced contact plug SRP may be used to transfer an operating voltage (Vop of fig. 1) generated in the voltage generation circuit (112 of fig. 1) to the first conductive layer 68-1, 68-2, … …, which may be used as a word line. After the third conductive layer 98 is formed, a planarization process may be performed to electrically disconnect the cell contact plug CRP and the second reduced contact plug 2SRP, which are formed in different regions, from each other.

Fig. 31 to 38 are diagrams for describing a method of manufacturing a memory device and a structure of a completed memory device according to a third embodiment of the present disclosure.

In the drawings shown in fig. 31 to 38, the same reference numerals are used to denote the same components as those of the first embodiment, and the reference numerals used in fig. 31 to 38 do not indicate the order of forming the components. Referring to fig. 31, a first stacked structure 1STR may be formed on a substrate 61. The first stacked structure 1STR may include first material layers 62 and second material layers 63 alternately stacked. In the first embodiment, the substrate 61, the first material layer 62, and the second material layer 63 have been described; therefore, a duplicate description thereof will be omitted.

First vertical vias 1VHc and 1VHs may be formed, the first vertical vias 1VHc and 1VHs vertically penetrating the first stacked structure 1STR and exposing portions of the substrate 61. The first vertical holes 1VHc and 1VHs may be filled with the sacrificial layer 70. The sacrificial layer 70 may be formed of a material having an etch selectivity higher than that of the materials of the first and second material layers 62 and 63 so that the sacrificial layer 70 may be removed during a subsequent etching process. The first vertical hole 1VHc formed in the cell region CR may be used to form a vertical channel structure. The first vertical hole 1VH formed in the reduced area SR may be used to form a support structure.

Referring to fig. 32, a second stacked structure 2STR may be formed on the first stacked structure 1STR provided with the sacrificial layer 70. The second stacked structure 2STR may include third material layers 72 and fourth material layers 73 alternately stacked. For example, the third material layer 72 may be made of the same material as that of the second material layer 63 of the first stacked structure 1 STR. The fourth material layer 73 may be made of the same material as that of the first material layer 62 of the first stacked structure 1 STR. A fourth material layer 73 may be formed on the uppermost end of the second stacked structure 2 STR.

After the second stack structure 2STR has been formed, second vertical holes 2VHc and 2VHs may be formed vertically through the second stack structure 2STR such that a portion of the sacrificial layer 70 may be exposed through the second vertical holes 2VHc and 2 VHs. For example, second vertical holes 2VHc and 2VHs may be formed over first vertical holes 1VHc and 1VHs, respectively.

Referring to fig. 33, the sacrificial layer (70 of fig. 32) exposed through the second vertical holes 2VHc and 2VHs may be removed so that the first material layer 62, the second material layer 63, the third material layer 72, and the fourth material layer 73 may be exposed through the first vertical holes 1VHc, 1VHs and the second vertical holes 2VHc, 2 VHs.

Referring to fig. 34, a vertical channel structure VCH and a support structure SP, each including a memory layer 74, a channel layer 75, a vertical insulating layer 76, and a cap layer 77, may be formed in the first vertical holes 1VHc, 1VHs and the second vertical holes 2VHc, 2 VHs.

The memory layer 74 may be formed in a hollow pillar shape along an inner surface of each of the first vertical holes 1VHc, 1VHs and the second vertical holes 2VHc and 2 VHs. The channel layer 75 may be formed in a hollow cylindrical shape along an inner surface of the memory layer 74. The vertical insulating layer 76 may be provided in a pillar form, and the space defined by the channel layer 75 is filled with the vertical insulating layer 75. Although not shown, in various embodiments, the channel layer 75 may be provided in a pillar form. In this case, the vertical insulating layer 76 is not formed. A cap layer 77 may be formed on the channel layer 75 and the vertical insulating layer 76, and surrounded by the memory layer 74.

In the cell region CR, portions of each vertical channel structure VCH adjacent to the second material layer 63 and the third material layer 72 may function as memory cells. The support structure SP formed in the reduced region SR may be used to support the first stack structure 1STR and the second stack structure 2 STR.

Referring to fig. 35, a reduction process of reducing the first material layer 62, the second material layer 63, the fourth material layer 72, and the fourth material layer 73 formed in the reduced region SR may be performed to form a stepped structure. During the shrink process, a mask pattern forming step and an etching step may be performed as described with reference to fig. 9 to 13. During the shrinking process, not only the first material layer 62, the second material layer 63, the fourth material layer 72, and the fourth material layer 73 exposed in the reduced region SR may be etched, but also the support structure SP may be etched.

After the step structure is formed in the reduced region SP, an etch-preventing layer 90 is formed along the upper surfaces of the cell region CR and the reduced region SR. The etch-preventing layer 90 may be formed of a material having an etch selectivity different from that of the first interlayer insulating layer (91 of fig. 36) to be formed during a subsequent process. In other words, the etching prevention layer 90 may be formed of a material having an etching rate different from that of the first interlayer insulating layer (91 of fig. 36). The etching prevention layer 90 may be formed of a layer including carbon (e.g., SiCN layer). If the etch-preventing layer 90 is formed of a material having a different etch selectivity from the first interlayer insulating layer (91 of fig. 36) to be formed during a subsequent process, a phenomenon in which a conductive layer for a word line is exposed through a contact hole during an etching process for forming the contact hole may be prevented. In addition, since the thickness of the etching prevention layer 90 does not need to be increased, the thickness of the etching prevention layer 90 may be reduced. For example, the etch preventing layer 90 may be formed in the same thickness as that of the second material layer 63.

Referring to fig. 36, a first interlayer insulating layer 91 may be formed over the etch resist layer 90. The first interlayer insulating layer 91 may be formed of an insulating layer. For example, the first interlayer insulating layer 91 may be formed of oxide. Thereafter, the second material layer 63 and the third material layer 72 are removed, and a fourth conductive layer 78 for a word line is formed. The method of removing second material layer 63 and third material layer 72 and forming fourth conductive layer 78 is similar to the method described with respect to the diagram shown in fig. 16; and thus a description thereof will be omitted. After forming the slits in the reduced region SR (refer to fig. 16), a sixth mask pattern 6MP may be formed over the first interlayer insulating layer 91.

The sixth mask pattern 6MP may have a pattern in which an opening OP is formed in the cell region CR and the reduced region SLR. In the cell region CR, an opening OP may be formed in a region where the vertical channel structure VCH is formed. In the reduced region SR, an opening OP may be formed in a region where the first reduced contact plug 1SRP is formed. The opening OP of the cell region CR may be formed in a region where the vertical channel structure VCH is formed. The opening OP of the reduced region SR may be formed in a region where the support structure SP is formed.

Referring to fig. 37, an etching process for forming the first contact holes H1 in the cell region CR and the reduced region SR using the sixth mask pattern 6MP may be performed. The etching process may be an anisotropic etching process such that a portion of the first interlayer insulating layer 91 exposed through the opening OP may be removed. The etching process of forming the first contact hole H1 may be performed until the etch-preventing layer 90 is exposed through all of the first contact holes H1. The etching process may be performed using an etching gas having a higher etching rate of the first interlayer insulating layer 91 than the etching rate of the etching prevention layer 90. Accordingly, the fourth conductive layer 78 in the reduced region SR may be protected by the etch preventing layer 90 during the etching process of forming the first contact hole H1.

If the etch-preventing layer 90 is exposed through all of the first contact holes H1, an additional etching process of removing the exposed etch-preventing layer 90 may be performed. The additional etching process may be performed using an etching gas having a higher etching selectivity to the etch-resistant layer 90 than to the first interlayer insulating layer 91 and the fourth conductive layer 78. An additional etching process may be performed until the fourth conductive layer 78 disposed in the uppermost layer of the corresponding step is exposed through the first contact hole H1.

Referring to fig. 38, a cell contact plug CRP may be formed in each of the first contact holes H1 formed in the first contact holes H1 in the cell region CR, and a reduced contact plug SRP may be formed in each of the first contact holes H1 formed in the first contact holes H1 in the reduced region SR. The cell contact plug CRP and the reduced contact plug SRP may be simultaneously formed. For example, the cell contact plug CRP and the reduced contact plug SRP may include a first barrier layer 93 and a second conductive layer 94. For example, after the first barrier layer 93 is formed along the inner surface of each of the first contact holes H1, the inside of each of the first contact holes H1 may be filled with the second conductive layer 94. The first barrier layer 93 may be formed of TiN. The second conductive layer 94 may be formed of a conductive material such as polysilicon, tungsten, or molybdenum. The cell contact plug CRP may be formed to adjoin on the vertical channel structure VCH. Reduced contact plugs SRPs may be formed to respectively adjoin the fourth conductive layers 78.

The cell contact plug CRP may electrically couple the vertical channel structure VCH and a bit line to be formed during a subsequent process. During a program, read or erase operation, the reduced contact plug SRP may be used to transfer an operating voltage (Vop of fig. 1) generated in the voltage generation circuit (112 of fig. 1) to the fourth conductive layer 78, which may be used as a word line. After the third conductive layer 98 is formed, a planarization process may be performed to electrically disconnect the cell contact plug CRP and the second reduced contact plug 2SRP, which are formed in different regions, from each other.

As described above, after the vertical channel structure VCH and the support structure SP are simultaneously formed in the cell region CR and the reduced region SR, a reduction process of forming a stepped structure in the reduced region SR is performed. Therefore, a separate process of forming the support structure SP may not be required. Accordingly, the phenomenon of the memory block tilting can be prevented by using the support structure SP without performing a separate additional process.

In addition, the etch prevention layer 90 is formed in the cell region CR and the reduced region SR before the first contact hole H1 is formed. Accordingly, the fourth conductive layer 78 for the word line may be prevented from being exposed during the etching process for forming the first contact hole H1, so that the fourth conductive layer 78 may be protected.

Fig. 39 is a block diagram illustrating an example of a memory system 1000 including a memory device according to an embodiment of the disclosure.

Referring to fig. 39, a memory system 1000 may include a plurality of memory devices 1100 configured to store data; and a controller 1200 configured to communicate between the memory device 1100 and the host 2000.

Each of the memory devices 1100 may be formed as the memory device described in one of the foregoing embodiments.

The memory device 1100 may be coupled to the controller 1200 through a plurality of system channels sCH. For example, multiple memory devices 1100 may be coupled to each system channel sCH. The controller 1200 may be coupled with a plurality of system channels sCH.

The controller 1200 may communicate between the host 2000 and the memory device 1100. The controller 1200 may control the memory device 1100 in response to a request from the host 2000 or may perform a background operation for improving the performance of the memory system 1000 even without a request from the host 2000.

The host 2000 may generate requests for various operations and output the generated requests to the memory system 1000. For example, the request may include a program request for controlling a program operation, a read request for controlling a read operation, and an erase request for controlling an erase operation. The host 2000 may communicate with the memory system 1000 through various interfaces, such as a peripheral component interconnect express (pcie) interface, an Advanced Technology Attachment (ATA) interface, a serial ATA (sata) interface, a parallel ATA (pata) interface, a serial attached scsi (sas) interface, a non-volatile memory express (NVMe) interface, a Universal Serial Bus (USB) interface, a Multi Media Card (MMC) interface, an Enhanced Small Device Interface (ESDI), and an Integrated Drive Electronics (IDE) interface.

Referring to fig. 40, the memory system may be implemented as a memory card 3000. The memory card 3000 may include a memory device 1100, a controller 1200, and a card interface 7100.

The controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. In one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto.

The card interface 7100 may exchange data between the host 2000 and the controller 1200 according to a protocol of the host 2000. In one embodiment, card interface 7100 may support the Universal Serial Bus (USB) protocol and the inter-chip (IC) -USB protocol. Herein, the card interface 7100 may refer to hardware, software installed in hardware, or a signal transmission method capable of supporting a protocol used by the host 2000.

When the memory card 3000 is connected to a host interface of a host 2000, such as a PC, a tablet computer, a digital camera, a digital audio player, a cellular phone, console video game hardware, or a digital set-top box, the host interface may perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of a microprocessor of the host 2000.

In various embodiments of the present disclosure, a support structure may be formed in a reduced area of a memory block so that the memory block may be prevented from being tilted. The support structure may be formed simultaneously with the vertical channel structure, so that a manufacturing process of the memory device may be facilitated.

Examples of various embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, it will be apparent to one of ordinary skill in the art to which the present application pertains that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and/or elements described in connection with other embodiments, unless specifically indicated otherwise. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A memory device comprising:

a stacked structure having cell regions and reduced regions in the stacked structure and formed by alternately stacking insulating layers and conductive layers;

a vertical channel structure formed through the stack structure in the cell region;

support structures formed through the stack structures in the abbreviated regions and having different heights depending on the stack heights of the abbreviated regions, each of the support structures having the vertical channel structure;

an etch resist layer formed over the stacked structure and including carbon; and

A contact plug is formed through the etch-resistant layer and coupled to the conductive layer.

2. The memory device of claim 1, wherein the etch-resistant layer is formed of a SiCN layer.

3. The memory device of claim 1, wherein the contact plug comprises:

a cell contact plug formed in the cell region; and

Reduced contact plugs formed in the reduced regions.

4. The memory device of claim 3, further comprising:

bit lines formed over the cell contact plugs; and

A metal line is formed over the reduced contact plug.

5. A method of manufacturing a memory device, comprising:

alternately stacking insulating layers and conductive layers in the cell area and the reduced area, and forming a stacked structure having a stepped structure in the reduced area;

forming an etch-resistant layer including carbon along the upper surface of the stacked structure;

forming an interlayer insulating layer on the etching resist layer;

performing a first etching process of forming a contact hole for exposing a portion of the etch-resistant layer in the cell region and the reduced region of the interlayer insulating layer;

performing a second etching process of removing the etching resist layer exposed through the contact hole; and

Contact plugs are formed in the contact holes.

6. The method of claim 5, wherein forming the stacked structure comprises:

alternately stacking insulating layers and sacrificial layers on the substrate;

A vertical channel structure vertically passing through the insulating layer and the sacrificial layer stacked in the cell region and a support structure vertically passing through the stacking the insulating layer and the sacrificial layer in the reduced region;

forming a trench for exposing the sacrificial layer by etching the insulating layer and the sacrificial layer between the support structures in a vertical direction;

performing a third etching process of removing the sacrificial layer exposed through the trench;

forming the conductive layer between the insulating layers from which the sacrificial layer was removed; and

The inside of the trench is filled with an insulating layer.

7. The method of claim 6,

wherein each of the insulating layers and the insulating layer are formed of an oxide layer,

wherein each of the sacrificial layers is formed of a nitride layer, and

Wherein the conductive layer is formed of polysilicon, tungsten or molybdenum.

8. The method of claim 6, wherein the third etching process comprises a wet etching process.

9. The method of claim 8, wherein the wet etching process is performed using phosphoric acid as an etchant.

10. The method of claim 5, wherein the etch resist layer is formed of a SiCN layer.

11. The method of claim 5, wherein the interlayer insulating layer is formed of an oxide layer.

12. The method of claim 5, wherein the etch-resistant layer has a thickness of any one of the conductive layers included in the stacked structure.

13. The method of claim 5, wherein each of the first etching process and the second etching process comprises an anisotropic etching process.

14. The method of claim 5, wherein forming the contact plug comprises:

forming a barrier layer along an inner surface of each of the contact holes; and

The inside of each of the contact holes provided with the barrier layer is filled with a conductive layer, and the contact plugs each including the barrier layer and the conductive layer are formed.

15. The method of claim 14, further comprising, after filling the inside of each of the contact holes with the conductive layer, performing a planarization process so that the contact plugs are electrically connected to each other Disconnect.

16. The method of claim 5, further comprising:

forming a bit line over a contact plug formed in the cell region among the contact plugs; and

Metal lines are formed over the contact plugs formed in the abbreviated regions among the contact plugs.

17. A method of manufacturing a memory device, comprising:

forming a stacked structure formed by alternately stacking the first material layers and the second material layers;

forming an etching resist layer and an interlayer insulating layer in sequence on the stacked structure;

forming a slit region vertically passing through the interlayer insulating layer, the etching resist layer, and the stacked structure;

performing an etching process to remove the second material layer exposed through the slit region;

forming a third material layer in the region where the second material layer was removed; and

forming a fourth material layer in the slit region,

The etching resist layer is formed of a material having an etching selectivity different from that of the second material layer.

18. The method of claim 17, wherein each of the first material layer, the interlayer insulating layer, and the fourth material layer is formed of an oxide layer.

19. The method of claim 17, wherein each of the second material layers is formed of a nitride layer.

20. The method of claim 17, wherein the etch resist layer is formed of a SiCN layer.