CN112601255B - MAC frame transmitting method and device, PHY frame aggregation method and device - Google Patents

Abstract

The invention discloses a MAC frame sending method and device, and a PHY frame aggregation method and device. The method includes: generating a MAC frame according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: sequentially arranged Ethernet receiving Address, Ethernet sending address, frame sequence number control, Ethernet destination address, Ethernet source address, and IP packet; sending the generated MAC frame to the physical layer PHY. The PHY receives multiple MAC frames and analyzes the MAC frames; according to the analysis results, the multiple MAC frames are aggregated into a PHY frame in a predetermined PHY frame format, which solves the problem of low transmission efficiency and high power consumption in the prior art The problem.

Description

MAC frame transmission method and device, PHY frame aggregation method and device

Technical Field

The present invention relates to the field of communication technology, and in particular to a MAC frame sending method and device, and a PHY frame aggregation method and device.

Background Art

Wireless ad hoc networks use distributed technology, without the management of central control nodes, and have strong self-organization and mobility, and the network is simple to establish. WIFI modules based on the 802.11 protocol are widely used in wireless ad hoc network communication systems. The 802.11 protocol uses CSMA/CA access technology. The advantage of this access technology is that it does not require complex time synchronization and control scheduling algorithms, but the disadvantage is that the protocol overhead is large and the power consumption is high. As shown in Figure 1, the mapping of standard Ethernet frames to the physical layer frame format requires the addition of MAC headers and PLCP headers, and the actual data carried is only the content in the IP payload.

In order to optimize the problem of high protocol overhead, the 802.11 standard introduces the following A-MPDU aggregation technology. A-MPDU is a relatively simple form of aggregation, which aggregates multiple frames together and then transmits them as a single aggregated frame. In the transmission process without aggregation in Figure 1, the MAC layer provides the MAC Header and CRC for the IP Payload, and then submits it to the PHY layer. After the PLCP Header is added at the PHY layer for transmission, each IP packet has its own PLCP Header.

In the transmission process shown in Figure 2, although each IP Payload has its own MAC Header and CRC, they share a PLCP Header, which reduces the waste of air interface resources. In the aggregation process, these separate MAC frames are put together, so they are called A-MPDU subframes at this stage. The receiving address and sending address of all subframes in the A-MPDU must be the same.

Defect 1: Low transmission efficiency:

The MPDU delimiter format is shown in Figure 3, where MPDU length is the MAC frame length in the current A-MPDU subframe, CRC is the check bit of the MPDU delimiter, and Delimiter Signature is a 1-byte delimiter identifier.

The MAC Header format is shown in Figure 4. RA is the 6-byte Ethernet receiving address, and TA is the 6-byte Ethernet sending address. Duration indicates the duration of the frame, and Sequence control contains the sequence number information of the frame. DA is the 6-byte Ethernet destination address, and SA is the 6-byte Ethernet source address. Frame ctrl contains information such as the protocol type.

The format of PLCP Header is shown in Figure 5, where Preamble is used for receiving gain control, frequency offset correction and synchronization. Control Information stores decoding parameters required by the receiver such as coding modulation.

In summary, each IP packet in the A-MPDU needs to add a MAC header and an MPDU delimiter totaling 34 bytes. Especially when the IP packets of each subframe in the A-MPDU are short, resources are seriously wasted. The transmission efficiency Te can be calculated as follows when N Ethernet frames are aggregated:

When N is large and the length of IP payload (i) is the same as IP payload, formula (I) can be approximated as:

Defect 2: High power consumption:

As shown in Figure 1 or Figure 2, the receiving address of the data packet is included in the MAC header. Whether it is its own data needs to be decoded by the PHY payload to determine, and the receiver has no sleep process. The data processing flow is shown in Figure 6.

Summary of the invention

The purpose of the present invention is to provide a MAC frame sending method and device, and a PHY frame aggregation method and device, aiming to solve the shortcomings of low transmission efficiency and high power consumption in the prior art.

The present invention provides a medium access control MAC frame sending method, comprising:

Generate a MAC frame according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet sending address, a frame sequence number control, an Ethernet destination address, an Ethernet source address, and an IP packet arranged in sequence;

The generated MAC frame is sent to the physical layer PHY.

Preferably, the length of the Ethernet receiving address is 6 bytes, the length of the Ethernet sending address is 6 bytes, the length of the frame sequence number control is 1 byte, the length of the Ethernet destination address is 6 bytes, the length of the Ethernet source address is 6 bytes, and the length of the IP packet is 48-1502 bytes.

Preferably, the method is implemented by a general-purpose processor.

The present invention provides a physical layer PHY frame aggregation method, comprising:

Receiving multiple MAC frames and parsing the MAC frames;

According to the analysis results, the multiple MAC frames are aggregated into a PHY frame in a predetermined PHY frame format, wherein the predetermined PHY frame format includes: a Physical Layer Convergence Protocol PLCP header connected in sequence, multiple PHY payloads, and a cyclic redundancy check bit in the middle of each PHY payload, the PLCP header specifically includes: a random access preamble code connected in sequence, control information, frame type, protocol data unit PDU number, length information of each PHY payload, a common Ethernet receiving address and Ethernet sending address of multiple PHY payloads, and each PHY payload specifically includes: frame sequence number control, Ethernet destination address, Ethernet source address, and IP packet.

Preferably, receiving multiple MAC frames specifically includes:

A plurality of MAC frames are received and generated according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet sending address, a frame sequence number control, an Ethernet destination address, an Ethernet source address, and an IP packet arranged in sequence.

Preferably, the method further comprises:

Step 1, receiving the PHY frame at an air interface;

Step 2, synchronizing the physical layer random access preamble of the PHY frame, and determining whether the synchronization is successful, if so, executing step 3, otherwise, executing step 1;

Step 3, decode the PHY PLCP and determine whether the decoding is successful. If successful, execute step 4; otherwise, execute step 1;

Step 4, judging whether it is its own data packet according to the Ethernet receiving address obtained by PHY PLCP decoding, if it is judged to be yes, executing step 6, otherwise, determining the sleep time according to each PHY load length information obtained by PHY PLCP decoding, turning off the RF receiver to enter the sleep mode, and executing step 5;

Step 5, determining whether the sleep time has expired, if so, exiting the sleep mode and executing step 1, otherwise, continuing to maintain the sleep mode;

Step 6: Decode the PHY payload and determine whether the decoding is successful. If successful, report the PHY frame to the upper layer. Otherwise, execute step 1.

Preferably, the method is implemented by a vector digital signal processor DSP.

The embodiment of the present invention further provides a medium access control MAC frame sending device, including:

A generating module, configured to generate a MAC frame according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet sending address, a frame sequence number control, an Ethernet destination address, an Ethernet source address, and an IP packet arranged in sequence;

The sending module is used to send the generated MAC frame to the physical layer PHY.

The embodiment of the present invention further provides a physical layer PHY frame aggregation device, including:

A receiving module, used for receiving multiple MAC frames and parsing the MAC frames;

An aggregation module is used to aggregate the multiple MAC frames into a PHY frame in a predetermined PHY frame format according to the parsing result, wherein the predetermined PHY frame format includes: a physical layer convergence protocol PLCP header connected in sequence, multiple PHY payloads, and a cyclic redundancy check bit in the middle of each PHY payload, the PLCP header specifically includes: a random access preamble code connected in sequence, control information, frame type, protocol data unit PDU number, each PHY payload length information, a common Ethernet receiving address and Ethernet sending address of multiple PHY payloads, and each PHY payload specifically includes: frame sequence number control, Ethernet destination address, Ethernet source address, and IP packet.

Preferably, the receiving module is specifically used for:

A plurality of MAC frames are generated according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet sending address, a frame sequence number control, an Ethernet destination address, an Ethernet source address, and an IP packet arranged in sequence.

Preferably, the device further comprises:

An air interface module, used for receiving the PHY frame at an air interface;

A synchronization module, used to synchronize the physical layer random access preamble of the PHY frame and determine whether the synchronization is successful. If so, the decoding module is called; otherwise, the air interface module is called;

A decoding module, used to decode the PHY PLCP and determine whether the decoding is successful. If successful, the processing module is called; otherwise, the air interface module is called;

A processing module, used to determine whether it is its own data packet according to the Ethernet receiving address obtained by PHY PLCP decoding, and if it is, call the decoding module; otherwise, determine the sleep time according to each PHY load length information obtained by PHY PLCP decoding, turn off the RF receiver to enter the sleep mode, and call the sleep module;

A sleep module, used to determine whether the sleep time has expired, if so, exit the sleep mode and call the air interface module, otherwise, continue to maintain the sleep mode;

The decoding module is used to decode the PHY load and determine whether the decoding is successful. If successful, the PHY frame is reported to the upper layer; otherwise, the air interface module is called.

An embodiment of the present invention also provides a medium access control MAC frame sending device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the above-mentioned medium access control MAC frame sending method when executed by the processor.

An embodiment of the present invention also provides a physical layer PHY frame aggregation device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the above-mentioned physical layer PHY frame aggregation method when executed by the processor.

An embodiment of the present invention further provides a computer-readable storage medium, on which a program for implementing information transmission is stored. When the program is executed by a processor, the steps of the above-mentioned medium access control MAC frame sending method are implemented.

An embodiment of the present invention further provides a computer-readable storage medium, on which a program for implementing information transmission is stored, and when the program is executed by a processor, the steps of the above-mentioned physical layer PHY frame aggregation method are implemented.

By adopting the embodiment of the present invention, the format of the MAC frame is changed and a new PHY frame aggregation method is provided, thereby improving transmission efficiency and being able to determine in advance whether a data packet matches a local MAC address. If not, the receiver is turned off and enters a power saving mode, thereby saving energy.

The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of a conventional PHY frame generation process and related frame formats in the prior art;

FIG2 is a schematic diagram of the MPDU aggregation process and PHY frame format of the prior art;

FIG3 is a schematic diagram of the MPDU delimiter format of the prior art;

FIG4 is a schematic diagram of a MAC Header format in the prior art;

FIG5 is a schematic diagram of the PLCP Header format of the prior art;

FIG6 is a conventional decoding data processing flow chart of the prior art;

7 is a schematic diagram of an efficient MAC frame format of an efficient frame aggregation method according to an embodiment of the present invention;

8 is a schematic diagram of a PHY aggregation process and a PHY frame format of a method for efficient frame aggregation according to an embodiment of the present invention;

9 is a flowchart of decoding data processing with a power saving function according to a method for efficient frame aggregation according to an embodiment of the present invention;

10 is a schematic diagram of a PHY aggregation implementation scheme of the efficient frame aggregation method according to an embodiment of the present invention;

11 is a flowchart of a method for sending a medium access control MAC frame according to an embodiment of the present invention;

12 is a flowchart of a physical layer PHY frame aggregation method according to an embodiment of the present invention;

13 is a schematic diagram of a physical layer PHY frame aggregation device module according to an embodiment of the present invention;

14 is a schematic diagram of a module of a medium access control MAC frame sending device according to an embodiment of the present invention;

15 is a schematic diagram of a medium access control MAC frame sending device according to an embodiment of the present invention;

FIG16 is a schematic diagram of a physical layer PHY frame aggregation device according to an embodiment of the present invention.

Description of reference numerals:

1000: generating module; 1020: sending module; 2000: receiving module; 2020: aggregation module; 1510: memory; 1520: processor; 1610: memory; 1620: processor.

DETAILED DESCRIPTION

The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as limiting the present invention.

In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

Method Example 1

According to an embodiment of the present invention, a method for sending a medium access control MAC frame is provided. FIG11 is a flow chart of the method for sending a medium access control MAC frame according to an embodiment of the present invention, as shown in FIG11 , specifically including the following processing:

Step 101, generating a MAC frame according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet sending address, a frame sequence number control, an Ethernet destination address, an Ethernet source address, and an IP packet arranged in sequence; wherein the length of the Ethernet receiving address is 6 bytes, the length of the Ethernet sending address is 6 bytes, the length of the frame sequence number control is 1 byte, the length of the Ethernet destination address is 6 bytes, the length of the Ethernet source address is 6 bytes, and the length of the IP packet is 48-1502 bytes.

Step 102: Send the generated MAC frame to the physical layer PHY.

Specifically, a MAC frame is generated according to a predetermined MAC frame format. The predetermined MAC frame needs to delete the useless fields in Figure 4. As shown in Table 1, the useless fields include Protocol, Type, Subtype, ToDS, FromDS, Morefrag, Retry, Pwrmgmt., Moredata, Protectedframe, Order, Duration in Framectrl, and the length of Sequencecontrol is reduced to one byte.

Table 1

The predetermined MAC frame format is shown in FIG. 7 and includes: an Ethernet receiving address,

Ethernet sending address, frame sequence number control, Ethernet destination address, Ethernet source address, and IP packet; the generated MAC frame is sent to the physical layer PHY, the length of the Ethernet receiving address is 6 bytes, the length of the Ethernet sending address is 6 bytes, the length of the frame sequence number control is 1 byte, the length of the Ethernet destination address is 6 bytes, the length of the Ethernet source address is 6 bytes, and the length of the IP packet is 48-1502 bytes. The method is implemented by a general processor.

In the embodiment of the present invention, the above method is implemented by a general-purpose processor.

Method Example 2

According to an embodiment of the present invention, a physical layer PHY frame aggregation method is provided. FIG12 is a flow chart of the physical layer PHY frame aggregation method according to an embodiment of the present invention, as shown in FIG12, specifically including the following processing:

Step 201, receiving multiple MAC frames and parsing the MAC frames;

Step 202, based on the parsing result, aggregate multiple MAC frames into a PHY frame in a predetermined PHY frame format, wherein the predetermined PHY frame format includes: a Physical Layer Convergence Protocol PLCP header connected in sequence, multiple PHY payloads, and a cyclic redundancy check bit in the middle of each PHY payload, the PLCP header specifically includes: a random access preamble code connected in sequence, control information, frame type, protocol data unit PDU number, each PHY payload length information, a common Ethernet receiving address and Ethernet sending address of multiple PHY payloads, and each PHY payload specifically includes: frame sequence number control, Ethernet destination address, Ethernet source address, and IP packet.

In an embodiment of the present invention, PHY receives multiple MAC frames and parses the MAC frames; based on the parsing results, the multiple MAC frames are aggregated into a PHY frame in a predetermined PHY frame format, as shown in Figure 8, wherein the predetermined PHY frame format includes: a Physical Layer Convergence Protocol PLCP header connected in sequence, multiple PHY payloads, and a cyclic redundancy check bit in the middle of each PHY payload, the PLCP header specifically includes: a random access preamble code connected in sequence, control information, a frame type, a protocol data unit PDU number, each PHY payload length information, a common Ethernet receiving address and an Ethernet sending address of multiple PHY payloads, and each PHY payload specifically includes: a frame sequence number control, an Ethernet destination address, an Ethernet source address, and an IP packet.

Receiving multiple MAC frames specifically includes:

A plurality of MAC frames are received and generated according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet sending address, a frame sequence number control, an Ethernet destination address, an Ethernet source address, and an IP packet arranged in sequence.

During the PHY aggregation process, the PLCPheaderextended includes a common RA and DA. Each MAC packet can be directly aggregated to the PHY layer, further reducing the waste of air interface resources. LEN1, LEN2, etc. are used for head and tail delimitation, reducing the resources occupied by the MPDUdelimiter and improving the rate.

The transmission efficiency Te when N Ethernet frames are aggregated can be calculated as follows:

When N is large and the length of IPpayload(i) is IPpayload, formula (III) can be approximated as:

Compared with formula (2), the efficiency of formula (4) is significantly improved, especially when the IP payload is small.

Based on the aggregated frame, a data processing flow with power saving function is invented as shown in Figure 9, which determines in advance whether the data packet matches the local MAC address. If it does not match, the receiver is turned off and enters power saving mode. The specific steps include:

Step 1: receiving a PHY frame via the air interface;

Step 2, synchronize the physical layer random access preamble of the PHY frame, and determine whether the synchronization is successful. If it is, execute step 3, otherwise, execute step 1;

Step 3, decode PHYPLCP and determine whether the decoding is successful. If successful, execute step 4; otherwise, execute step 1;

Step 4, judging whether it is its own data packet according to the Ethernet receiving address obtained by PHYPLCP decoding, if it is judged to be yes, executing step 6, otherwise, determining the sleep time according to each PHY load length information obtained by PHYPLCP decoding, turning off the RF receiver to enter the sleep mode, and executing step 5;

Step 5, determine whether the sleep time has expired, if so, exit the sleep mode and execute step 1, otherwise, continue to stay in the sleep mode;

Step 6: Decode the PHY payload and determine whether the decoding is successful. If successful, report the PHY frame to the upper layer. Otherwise, execute step 1.

The method is implemented by a vector digital signal processor DSP.

The embodiment of the present invention optimizes the MACframe structure of Figure 1, removes useless fields, shortens the MACheader of the MAC frame, integrates the fields in Figure 4 that are meaningless to the transmission of the ad hoc network system, and improves the transmission efficiency. The detailed deleted fields are shown in Table 1, and the RA/TA/data packet length/frame type in the MACheader is extracted to the PHYPLCPheader to form Figure 7, thereby improving the frame efficiency of the MAC.

The MAC in FIG2 is aggregated into the PHY aggregation in FIG8 , so that the PHY frame efficiency is improved.

Based on the new PHY frame format in FIG. 8 , a power saving function is added to the data receiving process flow in FIG. 6 to form FIG. 9 , so that power consumption is reduced.

In the above two method embodiments, the CSMA/CA scheme is implemented by using a vector DSP (Digital Signal Processing) plus a general ARM processor. As shown in Figure 10, CSMA/CA is implemented by the PHY layer (Physical layer) and the MAC layer (Media Access Control). Among them, the application layer runs on a general processor 1, the MAC layer runs on a general processor 0, and the PHY layer runs on the vector DSP. The application layer and the MAC layer interact with each other using Ethernet frames, and the MAC layer and the PHY layer interact with each other using MAC frames.

The MAC frame of FIG. 7 is generated at the MAC layer, the PHY frame aggregation of FIG. 8 and the data receiving process with the power saving function of FIG. 9 are completed at the PHY layer.

Device Example 1

According to an embodiment of the present invention, a medium access control MAC frame sending device is provided. FIG. 13 is a schematic diagram of the medium access control MAC frame sending device according to an embodiment of the present invention. As shown in FIG. 13 , the device specifically includes:

The generating module 1000 is used to generate a MAC frame according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet sending address, a frame sequence number control, an Ethernet destination address, an Ethernet source address, and an IP packet arranged in sequence; wherein the length of the Ethernet receiving address is 6 bytes, the length of the Ethernet sending address is 6 bytes, the length of the frame sequence number control is 1 byte, the length of the Ethernet destination address is 6 bytes, the length of the Ethernet source address is 6 bytes, and the length of the IP packet is 48-1502 bytes.

The sending module 1020 is used to send the generated MAC frame to the physical layer PHY.

The device can be implemented by a general-purpose processor.

Device Example 2

According to an embodiment of the present invention, a physical layer PHY frame aggregation device is provided. FIG14 is a schematic diagram of a physical layer PHY frame aggregation device according to an embodiment of the present invention. As shown in FIG14 , the device specifically includes:

The receiving module 2000 is used to receive multiple MAC frames and parse the MAC frames; the receiving module 2000 is specifically used to:

A plurality of MAC frames are generated according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet sending address, a frame sequence number control, an Ethernet destination address, an Ethernet source address, and an IP packet arranged in sequence.

The aggregation module 2020 is used to aggregate multiple MAC frames into a PHY frame in a predetermined PHY frame format according to the parsing results, wherein the predetermined PHY frame format includes: a physical layer convergence protocol PLCP header connected in sequence, multiple PHY payloads, and a cyclic redundancy check bit in the middle of each PHY payload, the PLCP header specifically includes: a random access preamble code connected in sequence, control information, frame type, protocol data unit PDU number, each PHY payload length information, a common Ethernet receiving address and Ethernet sending address of multiple PHY payloads, and each PHY payload specifically includes: frame sequence number control, Ethernet destination address, Ethernet source address, and IP packet.

The above device further comprises:

Air interface module, used for receiving PHY frames at air interface;

The synchronization module is used to synchronize the physical layer random access preamble of the PHY frame and determine whether the synchronization is successful. If it is, the decoding module is called, otherwise, the air interface module is called;

The decoding module is used to decode the PHY PLCP and determine whether the decoding is successful. If successful, the processing module is called; otherwise, the air interface module is called;

A processing module, used to determine whether it is its own data packet according to the Ethernet receiving address obtained by PHY PLCP decoding, and if it is, call the decoding module; otherwise, determine the sleep time according to each PHY load length information obtained by PHY PLCP decoding, turn off the RF receiver to enter the sleep mode, and call the sleep module;

The sleep module is used to determine whether the sleep time has expired. If so, it exits the sleep mode and calls the air interface module. Otherwise, it continues to stay in the sleep mode.

The decoding module is used to decode the PHY load and determine whether the decoding is successful. If successful, the PHY frame is reported to the upper layer, otherwise, the air interface module is called.

The embodiment of the present invention is a device embodiment corresponding to the above-mentioned method embodiment. The specific operations of each module can be understood by referring to the description of the method embodiment, which will not be repeated here.

Device Example 3

An embodiment of the present invention provides a medium access control MAC frame sending device, which includes: a memory 1510, a processor 1520, and a computer program stored in the memory 1510 and executable on the processor 1520. When the computer program is executed by the processor, the steps of the medium access control MAC frame sending method in the above-mentioned method embodiment 1 are implemented.

Device Example 4

An embodiment of the present invention provides a physical layer PHY frame aggregation device, as shown in Figure 16, comprising: a memory 1610, a processor 1620, and a computer program stored in the memory 1610 and executable on the processor 1620. When the computer program is executed by the processor, the steps of the physical layer PHY frame aggregation method in the second embodiment of the above method are implemented.

Device Example 5

An embodiment of the present invention provides a computer-readable storage medium, on which a program for implementing information transmission is stored. When the program is executed by the processor 1520, the steps of the medium access control MAC frame sending method in the first embodiment of the above method are implemented.

Device Example 6

An embodiment of the present invention provides a computer-readable storage medium, on which a program for implementing information transmission is stored. When the program is executed by the processor 1620, the steps of the physical layer PHY frame aggregation method in the second embodiment of the above method are implemented.

The computer-readable storage medium of this embodiment includes, but is not limited to, ROM, RAM, magnetic disk or optical disk, etc.

Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims (15)

1. A medium access control MAC frame sending method, characterized in that, comprising: Generate a MAC frame according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: Ethernet receiving address, Ethernet sending address, frame number control, Ethernet destination address, Ethernet source address, and IP packets arranged in sequence; Send the generated MAC frame to the physical layer PHY. 2. The method according to claim 1, wherein the length of the Ethernet receiving address is 6 bytes, the length of the Ethernet sending address is 6 bytes, and the length of the frame sequence number control is 1 bytes, the length of the Ethernet destination address is 6 bytes, the length of the Ethernet source address is 6 bytes, and the length of the IP packet is 48-1502 bytes. 3. The method according to claim 1, characterized in that, the method is implemented by a general-purpose processor. 4. A physical layer PHY frame aggregation method, characterized in that, comprising: receiving multiple MAC frames, and parsing the MAC frames; According to the parsing result, the plurality of MAC frames are aggregated into a PHY frame in a predetermined PHY frame format, wherein the predetermined PHY frame format includes: a sequentially connected Physical Layer Convergence Protocol PLCP header, a plurality of PHY loads, and each PHY The cyclic redundancy check bit in the middle of the load, the PLCP header specifically includes: sequentially connected random access preamble, control information, frame type, protocol data unit PDU number, each PHY load length information, multiple PHY load common The Ethernet receiving address and the Ethernet sending address, and each PHY load specifically includes: frame sequence number control, Ethernet destination address, Ethernet source address, and IP packets. 5. The method according to claim 4, wherein receiving a plurality of MAC frames specifically comprises: Receive multiple MAC frames generated according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: Ethernet receiving address, Ethernet sending address, frame sequence number control, Ethernet destination address, Ethernet source address, and IP packets. 6. The method according to claim 4, wherein the method further comprises: Step 1, the air interface receives the PHY frame; Step 2, performing the synchronization of the physical layer random access preamble on the PHY frame, and judging whether the synchronization is successful, if it is judged to be yes, then execute step 3, otherwise, execute step 1; Step 3, carry out the decoding of PHY PLCP, and judge whether the decoding is successful, if successful, perform step 4, otherwise, perform step 1; Step 4, judge whether it is your own data packet according to the Ethernet receiving address obtained by PHY PLCP decoding, if it is judged to be yes, then perform step 6, otherwise, determine the sleep time according to each PHY load length information obtained by PHY PLCP decoding , turn off the RF receiver and enter sleep mode, go to step 5; Step 5, judging whether the sleep time is up, if it is time, exit the sleep mode, and execute step 1, otherwise, continue to maintain the sleep mode; Step 6: Decode the PHY payload, and judge whether the decoding is successful, if successful, report the PHY frame to the upper layer, otherwise, perform step 1. 7. The method according to claim 4, characterized in that, the method is realized by a vector digital signal processor (DSP). 8. A medium access control MAC frame sending device, characterized in that, comprising: A generating module, configured to generate a MAC frame according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: Ethernet receiving address, Ethernet sending address, frame sequence number control, Ethernet destination address, and Ethernet source address arranged in sequence , and IP packets; A sending module, configured to send the generated MAC frame to a physical layer PHY. 9. A physical layer PHY frame aggregation device, characterized in that, comprising: A receiving module, configured to receive multiple MAC frames and analyze the MAC frames; An aggregation module, configured to aggregate the plurality of MAC frames into a PHY frame in a predetermined PHY frame format according to the parsing result, wherein the predetermined PHY frame format includes: sequentially connected Physical Layer Convergence Protocol PLCP headers, multiple PHY loads , and the cyclic redundancy check bit in the middle of each PHY load, the PLCP header specifically includes: sequentially connected random access preamble, control information, frame type, protocol data unit PDU number, length information of each PHY load, The common Ethernet receiving address and Ethernet sending address of multiple PHY loads, each PHY load specifically includes: frame sequence number control, Ethernet destination address, Ethernet source address, and IP packets. 10. The device according to claim 9, wherein the receiving module is specifically used for: A plurality of MAC frames are generated according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: Ethernet receiving address, Ethernet sending address, frame sequence number control, Ethernet destination address, Ethernet source address, and IP Bag. 11. The device according to claim 9, further comprising: An air interface module, configured to receive the PHY frame through an air interface; A synchronization module, used to synchronize the physical layer random access preamble of the PHY frame, and judge whether the synchronization is successful, if it is judged to be yes, then call the decoding module, otherwise, call the air interface module; The decoding module is used for decoding the PHY PLCP, and judging whether the decoding is successful, if successful, calling the processing module, otherwise, calling the air interface module; The processing module is used to judge whether it is its own data packet according to the Ethernet receiving address obtained by PHY PLCP decoding, if it is judged to be yes, call the decoding module, otherwise, determine according to the information of each PHY load length obtained by PHY PLCP decoding Sleep time, turn off the RF receiver to enter sleep mode, call the sleep module; The sleep module is used to judge whether the sleep time is up, if it is time, exit the sleep mode, call the air interface module, otherwise, continue to maintain the sleep mode; The decoding module is used for decoding the PHY load, and judging whether the decoding is successful, if successful, reporting the PHY frame to a higher layer, otherwise, calling the air interface module. 12. A medium access control MAC frame sending device, characterized in that it comprises: a memory, a processor, and a computer program stored on the memory and operable on the processor, the computer program being processed by the Implementing the steps of the medium access control MAC frame sending method according to any one of claims 1 to 3 when executed by a device. 13. A device for aggregating physical layer PHY frames, comprising: a memory, a processor, and a computer program stored on the memory and operable on the processor, the computer program being executed by the processor During execution, the steps of the physical layer PHY frame aggregation method according to any one of claims 4 to 7 are realized. 14. A computer-readable storage medium, characterized in that, the computer-readable storage medium is stored with an implementation program for information transmission, and when the program is executed by a processor, it implements the information described in any one of claims 1 to 3. Steps of the above-mentioned medium access control MAC frame sending method. 15. A computer-readable storage medium, characterized in that, the computer-readable storage medium is stored with an implementation program for information transfer, and when the program is executed by a processor, it realizes the implementation as described in any one of claims 4 to 7. Steps of the physical layer PHY frame aggregation method described above.

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