CN112599668A - Phase change memory and manufacturing method thereof - Google Patents
Phase change memory and manufacturing method thereof Download PDFInfo
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- CN112599668A CN112599668A CN202011482008.8A CN202011482008A CN112599668A CN 112599668 A CN112599668 A CN 112599668A CN 202011482008 A CN202011482008 A CN 202011482008A CN 112599668 A CN112599668 A CN 112599668A
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
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- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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Abstract
The embodiment of the disclosure discloses a phase change memory and a manufacturing method of the phase change memory, wherein the phase change memory comprises: a substrate; a memory array on the first surface of the substrate; a heat dissipating unit comprising: the first heat dissipation layer is positioned on the side surface of the storage array; wherein the sides of the memory array are perpendicular to the substrate; and/or a second heat dissipation layer located on the second surface of the substrate; wherein the second surface and the first surface are two surfaces arranged opposite to the substrate.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, and in particular relates to a phase change memory and a manufacturing method of the phase change memory.
Background
Phase Change Memories (PCMs), which are a type of nonvolatile memory device, have many advantages such as fast access speed, large capacity, and high reliability. In order to increase the integration level and obtain higher storage capacity, more and more memory cell stacks are stacked together to form a three-dimensional phase change memory.
Phase change memories may store data using a difference between resistivities of an amorphous phase and a crystalline phase of a phase change material based on heating and quenching of the phase change material in an electro-thermal manner. Therefore, the phase change memory generates a large amount of heat in the memory array when performing an operation (e.g., writing), and if the heat cannot be rapidly transferred out, the temperature in the phase change memory increases, which may affect the performance of the memory, such as data retention performance and writing performance. Therefore, how to quickly dissipate the heat in the phase change memory is important to keep the temperature of the phase change memory low.
Disclosure of Invention
In view of the above, the present disclosure provides a phase change memory and a method for manufacturing the same.
According to a first aspect of embodiments of the present disclosure, there is provided a phase change memory, including:
a substrate;
a memory array on the first surface of the substrate;
a heat dissipating unit comprising:
the first heat dissipation layer is positioned on the side surface of the storage array; wherein the sides of the memory array are perpendicular to the substrate;
and/or the presence of a gas in the gas,
the second heat dissipation layer is positioned on the second surface of the substrate; wherein the second surface and the first surface are two surfaces arranged opposite to the substrate.
In some embodiments, the first heat dissipation layer comprises:
the first heat dissipation sublayer extends along a first direction and covers the first side face of the storage array; wherein the first direction is parallel to the first side;
and/or the presence of a gas in the gas,
the second heat dissipation sublayer extends along a second direction and covers the second side face of the storage array; wherein the second direction is parallel to the second side;
wherein the first direction and the second direction are perpendicular to each other and parallel to the substrate.
In some embodiments, the height of the first heat dissipation layer, in a direction perpendicular to the substrate, is greater than or equal to the height of the memory array.
In some embodiments, the heat dissipation unit is conductive, and the phase change memory includes:
and the insulating dielectric layer is positioned between the storage array and the first heat dissipation layer.
In some embodiments, a first projection of the memory array onto the substrate is located within a second projection of the second heat spreading layer onto the substrate in a direction perpendicular to the substrate.
According to a second aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a phase change memory, including:
providing a substrate;
forming a memory array on a first surface of the substrate;
forming a heat dissipation unit around the memory array; wherein, the heat dissipation unit includes:
a first heat dissipation layer located on a side of the memory array; wherein the sides of the memory array are perpendicular to the substrate;
and/or the presence of a gas in the gas,
a second heat sink layer on a second surface of the substrate; wherein the first surface and the second surface are two surfaces oppositely arranged to the substrate.
In some embodiments, when the heat dissipation unit includes the first heat dissipation layer, the forming the heat dissipation unit around the memory array includes:
forming a first heat dissipation sub-layer extending along a first direction on a first side face of the memory array; wherein the first direction is parallel to the first side, the first heat dissipation layer comprises the first heat dissipation sublayer;
and/or the presence of a gas in the gas,
forming a second heat dissipation sub-layer extending along a second direction on a second side of the memory array; wherein the second direction is parallel to the second side, the first heat dissipation layer comprising the second heat dissipation sublayer;
wherein the first direction and the second direction are perpendicular to each other and parallel to the substrate.
In some embodiments, the method further comprises:
forming an insulating dielectric layer surrounding the side face of the storage array; wherein, along the direction vertical to the substrate, the height of the dielectric layer is larger than or equal to that of the memory array;
when the heat dissipation unit includes the first heat dissipation layer, the forming the heat dissipation unit around the memory array includes:
forming a groove vertical to the substrate in the dielectric layer; filling the groove with the material of the first heat dissipation layer, thereby forming the first heat dissipation layer; wherein, along the direction vertical to the substrate, the height of the groove is larger than or equal to the height of the memory array.
In some embodiments, the storage array comprises: at least two memory sub-arrays arranged in a stack in a direction perpendicular to the substrate, the method comprising:
after a first memory sub-array is formed, forming a first heat dissipation unit around the first memory sub-array;
after the first heat dissipation unit is formed, at least one memory sub-array is formed on the first memory sub-array;
forming a second heat dissipation unit on the first heat dissipation unit after the at least one memory sub-array is formed; wherein the second heat dissipating unit surrounds the at least one memory sub-array.
In some embodiments, when the memory array includes the second heat dissipation layer, the forming a heat dissipation unit around the memory array includes:
depositing the material of the second heat sink layer on the second surface of the substrate, thereby forming the second heat sink layer; wherein the second surface and the first surface are two surfaces arranged opposite to the substrate.
The phase change memory generates a large amount of heat during the erase/write operation, and the heat accumulated in the memory array raises the internal temperature of the phase change memory, generates thermal crosstalk inside the memory array, and affects the performance of the phase change material, such as the write performance and the data retention performance of the phase change memory.
The embodiment of the disclosure arranges the heat dissipation unit around the storage array of the phase change memory, that is, arranges the first heat dissipation layer on the side surface of the storage array, and/or arranges the second heat dissipation layer on the second surface of the substrate, to dissipate heat of the storage array, so that heat accumulated in the storage array can be quickly conducted to the heat dissipation unit, and dissipated to the outside of the storage array through the heat dissipation unit, thereby keeping relatively low ambient temperature in the storage array, and reducing the possibility that the performance of the phase change memory is affected due to overhigh ambient temperature in the storage array.
Drawings
FIG. 1a is a schematic diagram of a phase change memory in accordance with an exemplary embodiment;
FIG. 1b is a schematic diagram illustrating another phase change memory according to an example embodiment;
FIG. 2 is a schematic diagram illustrating yet another phase change memory in accordance with an exemplary embodiment;
FIG. 3 is a schematic diagram illustrating yet another phase change memory in accordance with an exemplary embodiment;
FIG. 4 is a schematic diagram illustrating yet another phase change memory in accordance with an exemplary embodiment;
FIG. 5 is a flow chart illustrating a method of fabricating a phase change memory according to one exemplary embodiment;
FIGS. 6 a-6 c are schematic diagrams illustrating a method of fabricating a phase change memory according to an exemplary embodiment;
fig. 7a to 7c are schematic views illustrating another phase change memory manufacturing method according to an exemplary embodiment.
Detailed Description
The technical solution of the present invention is further described in detail with reference to the drawings and the specific embodiments of the specification.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not used for describing a particular order or sequence.
In the disclosed embodiment, the term "a is in contact with B" includes the case where a is in direct contact with B, or A, B is in contact with B indirectly with another component interposed between the two.
In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. Also, a layer may include multiple sublayers.
It is to be understood that the meaning of "on … …," "over … …," and "over … …" in this disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.
It should be noted that although the present description is described in terms of embodiments, not every embodiment includes only a single technical solution, and such description of the embodiments is merely for clarity, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Fig. 1a and 1b are partial schematic diagrams illustrating a phase change memory 100 according to an exemplary embodiment. As shown in fig. 1a and 1b, the phase change memory 100 includes:
a substrate 101;
a memory array on the first surface 101a of the substrate 101;
a heat dissipating unit comprising:
as shown in fig. 1a, a first heat dissipation layer 150 is located at a side of the memory array; wherein the sides of the memory array are perpendicular to the substrate 101;
and/or the presence of a gas in the gas,
as shown in fig. 1b, a second heat dissipation layer 160 is disposed on the second surface 101b of the substrate 101; the second surface 101b and the first surface 101a are two surfaces disposed opposite to the substrate 101.
Illustratively, the substrate 101 is a material to which subsequent layers of material are added, and may itself be patterned. The substrate 101 may comprise a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. The substrate 101 may also include a portion of a structure formed thereon, including, for example, an insulating layer 102 thereon. The constituent material of the insulating layer 102 may include silicon oxide or the like.
The memory array includes: the plurality of phase change memory cells 120 are arranged in parallel in a direction parallel to the substrate 101. Each phase change memory cell 120 includes a first conductive line 110, a first electrode layer 121, a gate layer 122, a second electrode layer 123, a phase change memory layer 124, a third electrode layer 125, and a second conductive line 130 stacked from bottom to top in a direction perpendicular to the substrate 101.
The material of the phase-change storage layer 124 comprises a chalcogen compound based phase-change material, such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase-change material. The phase change memory may store data using a difference between the resistivity of the phase change memory layer 124 in an amorphous phase and the resistivity of a crystalline phase based on heating and quenching of the phase change memory layer 124 such that the phase change memory layer 124 is switched between the amorphous phase and the crystalline phase.
The first conductive line 110 and the second conductive line 130 are parallel to the substrate 101 and perpendicular to each other, and the memory cell 120 is located between the first conductive line 110 and the second conductive line 130. First conductive line 110 and second conductive line 130 may be used to locate phase change memory cells 120 and apply a current to perform a memory operation individually for each memory cell 120.
For example, in the phase change memory, the first conductive line 110 may be a word line, and the second conductive line 130 may be a bit line.
The composition material of the first and second conductive lines 110 and 130 includes a conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or polysilicon.
Around the memory array, a heat dissipation unit is disposed, such as a first heat dissipation layer 150 disposed on the side of the memory array, a second heat dissipation layer 160 disposed on the second surface 101b of the substrate 101 under the memory array, or both the first heat dissipation layer 150 and the second heat dissipation layer 160.
It is understood that the heat dissipation effect can be enhanced compared to the case where only the first heat dissipation layer 150 or only the second heat dissipation layer 160 is disposed, and the case where the first heat dissipation layer 150 and the second heat dissipation layer 160 are disposed at the same time is advantageous for further reducing the probability of the performance degradation of the phase change memory due to the high temperature in the memory array.
In the embodiment of the disclosure, the heat dissipation unit is arranged around the storage array of the phase change memory, so that heat accumulated in the storage array can be quickly conducted to the heat dissipation unit and dissipated out through the heat dissipation unit, thereby keeping the storage array at a relatively low ambient temperature and reducing the possibility that the performance of the phase change memory is affected due to the overhigh ambient temperature in the storage array.
In some embodiments, the first heat dissipation layer 150 includes:
as shown in fig. 2, the first heat-dissipation sublayer 151 extends along a first direction and covers a first side of the memory array; wherein the first direction is parallel to the first side;
and/or the presence of a gas in the gas,
as shown in fig. 3, the second heat dissipation sublayer 152 extends along the second direction and covers the second side of the memory array; wherein the second direction is parallel to the second side;
illustratively, as shown in fig. 2 and 3, the y-direction is a direction perpendicular to the plane xoz, the first direction is parallel to the y-direction, the second direction is parallel to the x-direction, and the x-direction and the y-direction are perpendicular to each other and parallel to the plane of the substrate 101. The third direction is perpendicular to the plane of the substrate 101 and parallel to the z-axis direction. It is understood that the plane in which the substrate 101 lies is parallel to the xoy plane.
Illustratively, as shown in fig. 2, the memory array may include two of the first sides juxtaposed in parallel with the second direction, both of the first sides being parallel with the first direction. Therefore, in order to improve the heat dissipation efficiency, the first heat dissipation layer may include two first heat dissipation sub-layers, a first heat dissipation sub-layer 151a covers the first side surface, and a second first heat dissipation sub-layer 151b covers the second first side surface.
It will be appreciated that the first side and the second first side are parallel to each other and both parallel to the yoz plane.
Illustratively, as shown in fig. 3, the memory array may include two of the above-described second side surfaces juxtaposed in parallel with the first direction, both of the second side surfaces being parallel with the second direction. Therefore, in order to improve the heat dissipation efficiency, the first heat dissipation layer may include two second heat dissipation sublayers, a first second heat dissipation sublayer 152a covers the first second side, and a second heat dissipation sublayer 152b covers the second side.
It will be appreciated that the first second side and the second side are parallel to each other and both parallel to the plane xoz.
For example, as shown in fig. 4, the first heat dissipation layer 150 may include both the two first heat dissipation sub-layers 151 and the two second heat dissipation sub-layers 152, forming a layout that fully encloses the sides of the memory array. Compared with the case that only the first heat dissipation sublayer 151 is arranged or only the second heat dissipation sublayer 152 is arranged, the heat dissipation effect of the heat dissipation unit on the memory array can be improved by simultaneously arranging one first heat dissipation sublayer 151 on each of two opposite first side surfaces of the memory array and arranging one second heat dissipation sublayer 152 on each of two opposite second side surfaces of the memory array.
In the embodiment of the present disclosure, the composition material of the first heat dissipation layer 150 may include a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo).
When the phase change memory cell 120 in the memory array generates a large amount of heat to be accumulated in the memory array during operation, because the first heat dissipation layer 150 is made of materials such as metal and the like, the heat conductivity is good, a certain temperature difference can be formed between the first heat dissipation layer 150 and the memory array, and the heat accumulated in the memory array can be conducted to the first heat dissipation layer 150 and further quickly conducted out through the first heat dissipation layer 150, so that the memory array is kept at a relatively low temperature without affecting the performance of the phase change memory, and the data retention performance of the memory is favorably ensured to be good.
In some embodiments, the height of the first heat dissipation layer 150, in a direction perpendicular to the substrate 101, is greater than or equal to the height of the memory array.
As in the phase change memory 100 shown in fig. 2, 3 and 4, the first and second heat-dissipating sub-layers 151 and 152 have a height in a direction perpendicular to the substrate 101 (illustrating the z-direction) that is not lower than the height of the memory array to ensure complete coverage of the sides of the memory array in the z-direction. Meanwhile, in the y direction, the first heat dissipation sublayer 151 extends a width greater than or equal to the width of the memory array; in the x direction, the second heat dissipation sublayer 152 extends a width greater than or equal to the width of the memory array. Therefore, the first heat dissipation layer 150 completely covers the side surface of the memory array, and has a heat dissipation area greater than or equal to the area of the side surface of the memory array, thereby better performing the heat dissipation function.
It is understood that the height of the first heat dissipation sub-layer and the height of the second heat dissipation sub-layer may be the same or different, and is not limited herein.
It is emphasized that, when the first heat dissipation layer includes both the first heat dissipation sublayer and the second heat dissipation sublayer, the height of the first heat dissipation sublayer is equal to the height of the second heat dissipation sublayer in the direction perpendicular to the plane of the substrate. Therefore, the first heat dissipation sub-layer and the second heat dissipation sub-layer with the same height can be formed at the same time, and compared with the case that the first heat dissipation sub-layer and the second heat dissipation sub-layer with different heights are formed respectively, the process flow can be simplified.
In some embodiments, the first heat dissipation layer 150 is conductive, and the phase change memory further includes: an insulating dielectric layer 140 is disposed between the memory array and the first heat dissipation layer 150.
The dielectric layer 140 has a height greater than or equal to the first heat dissipation layer 150 in a direction perpendicular to the substrate 101.
The constituent materials of the dielectric layer 140 may include: silicon oxide, aluminum oxide, or the like.
Since the first heat dissipation layer 150 is made of a heat conductive metal material and has electrical conductivity, the insulating dielectric layer 140 is disposed between the memory array and the first heat dissipation layer 150, so as to prevent short circuit caused by electrical conduction between the memory array and the first heat dissipation layer 150, and ensure that the memory array can still operate normally after the first heat dissipation layer 150 is disposed.
In some embodiments, along a direction perpendicular to the substrate 101 (the z-direction is illustrated), a first projection of the memory array onto the substrate 101 is located within a second projection of the second heat spreader layer 160 onto the substrate 101.
The composition material of the second heat dissipation layer 160 may include a metal material such as copper (Cu), aluminum (Al), or tungsten (W). Alternatively, the composition material of the second heat dissipation layer 160 may further include an alloy material such as a tungsten copper (WCu) alloy or an aluminum alloy (Al alloy).
It will be appreciated that when the first projection is within the second projection, the area of the second heat spreading layer 160 is greater than or equal to the area of the bottom of the memory array, ensuring that the bottom of the memory array is completely covered by the second heat spreading layer 160. Because the thermal conductivity of the second heat dissipation layer 160 is greater than the thermal conductivity of the substrate 101 and the insulating layer 102, the overall thermal conductivity of the bottom structure of the memory array can be improved by reasonably setting the area of the second heat dissipation layer 160, so that the conduction of heat in the memory array to the second heat dissipation layer 160 is promoted, and the heat is dissipated through the second heat dissipation layer 160.
In some embodiments, the memory array may include at least two memory sub-arrays stacked in a direction perpendicular to the substrate 101, each memory sub-array including a plurality of phase change memory cells 120 juxtaposed in a plane parallel to the substrate 101; wherein the first conductive line 110 or the second conductive line 130 is disposed between two adjacent memory sub-arrays.
Illustratively, when the memory array includes 2 memory sub-arrays arranged in a stack, the first conductive line 110 or the second conductive line 130 is arranged between the adjacent 2 memory sub-arrays. When the memory array includes M memory sub-arrays stacked, where M is an integer greater than 2, the first conductive line 110 is located between the 2N-th memory sub-array and the 2N + 1-th memory sub-array, and the second conductive line 130 is located between the 2N-1-th memory sub-array and the 2N-th memory sub-array. Wherein N is a positive integer, and 2N +1 is less than or equal to M.
Taking M equal to 2 as an example, when the memory array includes a first memory sub-array and a second memory sub-array stacked in a direction perpendicular to the substrate 101, the first heat dissipation layer may include a first portion and a second portion stacked in the direction perpendicular to the substrate 101. A first portion of the first heat spreader layer surrounds the first memory sub-array and a second portion of the first heat spreader layer surrounds the second memory sub-array.
Fig. 5 illustrates a method of manufacturing a phase change memory 100 according to an exemplary embodiment, and referring to fig. 5, the method includes the steps of:
s1: providing a substrate;
s2: forming a memory array on a first surface of a substrate;
s3: forming a heat dissipation unit around the memory array; wherein, the radiating unit includes:
a first heat dissipation layer located on a side of the memory array; wherein the side of the memory array is perpendicular to the substrate;
and/or the presence of a gas in the gas,
a second heat dissipation layer on the second surface of the substrate; the first surface and the second surface are two surfaces which are arranged opposite to the substrate.
The embodiment of the disclosure dissipates heat to the memory array by forming the heat dissipating unit around the memory array, that is, forming the first heat dissipating layer on the side surface of the memory array, and/or forming the second heat dissipating layer on the second surface of the substrate, so that heat accumulated in the memory array can be quickly conducted to the heat dissipating unit and dissipated to the outside of the memory array through the heat dissipating unit, thereby keeping relatively low ambient temperature in the memory array, and reducing the possibility that the performance of the phase change memory is affected by too high ambient temperature in the memory array.
In some embodiments, step S3 includes:
forming a first heat dissipation sublayer 151 extending along a first direction on a first side of the memory array; wherein the first direction is parallel to the first side surface, the first heat dissipation layer 150 includes a first heat dissipation sublayer 151;
and/or the presence of a gas in the gas,
forming a second heat dissipation sub-layer 152 extending along a second direction on a second side of the memory array; wherein the second direction is parallel to the second side, the first heat dissipation layer 150 includes a second heat dissipation sublayer 152;
the first direction and the second direction are perpendicular to each other and parallel to the plane of the substrate 101.
Illustratively, the first direction is parallel to the y-direction, the second direction is parallel to the x-direction, and the x-direction and the y-direction are perpendicular to each other and parallel to the plane of the substrate 101.
For example, the memory array may include two of the above first sides disposed parallel to the second direction, extending parallel to the first direction. Forming the first heat dissipation sub-layer 151 may include forming a first heat dissipation sub-layer 151a on the first side, and forming a second first heat dissipation sub-layer 151b on the second first side. It will be appreciated that the first side and the second first side are parallel to each other and both parallel to the yoz plane.
For example, the memory array may include two of the above-described second side surfaces arranged parallel to the first direction, extending in parallel to the second direction. Forming the second thermal sub-layer 152 can include forming a first second thermal sub-layer 152a on a first second side and forming a second thermal sub-layer 152b on a second side. It will be appreciated that the first second side and the second side are parallel to each other and both parallel to the plane xoz.
Forming the first heat dissipation layer 150 around the memory array may include one of:
forming a first heat-dissipating sub-layer 151 only on a first side of the memory array;
forming a second heat-dissipating sublayer 152 only on the second side of the memory array;
while a first heat-spreading sublayer 151 is formed on a first side of the memory array and a second heat-spreading sublayer 152 is formed on a second side of the memory array.
It is easy to understand that, when the first heat dissipation sublayer 151 and the second heat dissipation sublayer 152 are formed at the same time, it is beneficial to improve the heat dissipation effect of the heat dissipation unit on the memory array compared to when only the first heat dissipation sublayer 151 or only the second heat dissipation sublayer 152 is formed.
In some embodiments, step S3 further includes:
forming an insulating dielectric layer 140 around the sides of the memory array; wherein, along the direction perpendicular to the substrate 101, the height of the dielectric layer 140 is greater than or equal to the height of the memory array;
when the heat dissipation unit includes the first heat dissipation layer 150, the heat dissipation unit is formed around the memory array, including:
in the dielectric layer 140, a trench 153 is formed perpendicular to the substrate 101; filling the trench 153 with a material of the first heat dissipation layer 150, thereby forming the first heat dissipation layer 150; wherein, along the direction perpendicular to the substrate 101, the height of the trench 153 is greater than or equal to the height of the memory array.
Exemplarily, as shown in fig. 6a (taking the formation of the first heat dissipation sublayer 151 on the first side of the memory array in the x direction as an example), after the formation of the memory array, an insulating dielectric layer 140 is formed around the memory array, so as to electrically isolate the memory array from its surrounding structure, thereby improving the reliability of the phase change memory.
Illustratively, as shown in fig. 6b, a trench 153 may be formed in the dielectric layer 140 on the x-direction side of the memory array by photolithography and Reactive Ion Etching (RIE), the trench 153 extending perpendicular to the substrate 101 and along the y-direction. The height of the trench 153 in the direction perpendicular to the substrate 101 is not less than the height of the memory array.
Illustratively, as shown in fig. 6c, a material of the first heat dissipation Layer 150, for example, a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), is deposited into the trench 153 using one or more thin film Deposition processes, for example, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like, or a combination thereof, so as to form the first heat dissipation sublayer 151.
The second heat dissipation sublayer 152 is formed in the same manner as the first heat dissipation sublayer 151, and a description thereof will not be repeated.
In some embodiments, a memory array comprises: at least two memory sub-arrays arranged in a stacked manner in a direction perpendicular to the substrate 101, step S3 includes:
forming a first heat dissipation unit around the first memory sub-array after the first memory sub-array is formed;
after the first heat dissipation unit is formed, at least one memory sub-array is formed on the first memory sub-array;
forming a second heat dissipation unit on the first heat dissipation unit after the at least one memory sub array is formed; wherein the second heat dissipating unit surrounds at least one of the memory sub-arrays.
When the memory array comprises a plurality of memory sub-arrays, the first heat dissipation layer 150 is formed after the memory array is formed, because the height of the stacked memory sub-arrays is high, the depth of the groove 153 formed in the surrounding dielectric layer 140 is deep, and the depth-width ratio is large, when the material of the first heat dissipation layer 150 is filled into the groove 153 through the conventional thin film deposition process, the material is difficult to fill near the bottom of the groove 153, so that the formed first heat dissipation layer 150 is not uniform, and the heat dissipation effect is reduced.
Therefore, the present disclosure provides a method of forming a segment to form the first heat dissipation layer 150, which can avoid the above problem. Next, a method of forming the first heat dissipation layer 150 in segments is described by taking the example of forming the first heat dissipation sublayer 151 on the first side of the memory array in the x direction.
Illustratively, as shown in fig. 7a, a first memory sub-array is formed above the first surface 101a of the substrate 101, including forming a first conductive line 110a, a first phase change memory cell 120a and a second conductive line 130, which are stacked in sequence from bottom to top. A dielectric layer 140 is then formed around the first memory sub-array to be equal in height thereto, and then a first heat dissipation unit (i.e., a first portion of the first heat dissipation sub-layer 151) is formed in the dielectric layer 140 with reference to the method of fig. 6a to 6 c.
Illustratively, as shown in FIG. 7b, forming a second sub-array of memory cells on the first sub-array of memory cells includes forming a second phase change memory cell 120b and a second first conductive line 110b on top of the second conductive line 130. The first memory sub-array shares a second conductive line 130 therebetween with the second memory sub-array.
It is noted that first phase change memory cell 120a and second phase change memory cell 120b are phase change memory cells 120, and may comprise the same or different materials, and the different reference numbers are only used to distinguish the difference in location between the two phase change memory cells and are not necessarily used to describe a particular order or sequence.
Illustratively, as shown in fig. 7c, a dielectric layer 140 is formed around the second memory sub-array, and referring also to the method of fig. 6a to 6c, a second heat sink unit (i.e., the second portion of the first heat-sink sub-layer 151) is formed in the dielectric layer 140 above the first heat sink unit in a position aligned with the first heat sink unit and is integrally connected to the first heat sink unit.
By analogy, illustratively, when the memory array includes M memory sub-arrays, M being an integer greater than 2, a 2N memory sub-array is formed on the 2N-1 memory sub-array, including forming the first conductive line 110 on top of the 2N memory sub-array. Then, a dielectric layer 140 is formed around the 2N-th memory sub-array, and a 2N-th heat dissipation unit (i.e., the 2N-th portion of the first heat dissipation sub-layer 151) is formed in the dielectric layer 140 at a position aligned with the 2N-1-th heat dissipation unit and is integrally connected with the 2N-1-th heat dissipation unit. Wherein N is a positive integer, and 2N +1 is less than or equal to M.
Illustratively, a 2N +1 memory sub-array is formed on the 2N memory sub-array, including forming the second conductive line 130 on top of the 2N +1 memory sub-array, then forming the dielectric layer 140 around the 2N +1 memory sub-array, and forming a 2N +1 heat dissipation unit (i.e., the 2N +1 part of the first heat dissipation sub-layer 151) in the dielectric layer 140 at a position aligned with the 2N heat dissipation unit, and integrally connecting with the 2N heat dissipation unit.
In some embodiments, step S3 further includes:
depositing a material of a second heat sink layer 160 on the second surface 101b of the substrate 101, thereby forming a second heat sink layer 160; the second surface 101b and the first surface 101a are two surfaces disposed opposite to the substrate 101.
For example, before the memory array is formed on the first surface 101a of the substrate 101, a material layer of the second heat dissipation layer 160 may be deposited on the second surface 101b of the substrate 101 by a thin film deposition process such as CVD, PVD, ALD, or a combination thereof, and then the memory array is formed on the first surface 101a of the substrate 101.
Along the direction perpendicular to the substrate 101, the projection of the memory array on the substrate 101 is located in the projection of the second heat dissipation layer 160 on the substrate 101, so that the second heat dissipation layer 160 is ensured to completely cover the bottom of the memory array, and the heat dissipation efficiency is improved by reasonably setting the area of the second heat dissipation layer 160.
According to the phase change memory manufactured by the method, the heat dissipation unit is formed around the storage array, so that the heat conductivity of the structure around the storage array can be improved, the heat in the storage array is promoted to be conducted outwards, the function of heat dissipation and cooling of the storage array is achieved, the performance of the phase change memory is prevented from being influenced by temperature rise, and the reliability is improved.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A phase change memory, comprising:
a substrate;
a memory array on the first surface of the substrate;
a heat dissipating unit comprising:
the first heat dissipation layer is positioned on the side surface of the storage array; wherein the sides of the memory array are perpendicular to the substrate;
and/or the presence of a gas in the gas,
the second heat dissipation layer is positioned on the second surface of the substrate; wherein the second surface and the first surface are two surfaces arranged opposite to the substrate.
2. The phase change memory of claim 1, wherein the first heat spreading layer comprises:
the first heat dissipation sublayer extends along a first direction and covers the first side face of the storage array; wherein the first direction is parallel to the first side;
and/or the presence of a gas in the gas,
the second heat dissipation sublayer extends along a second direction and covers the second side face of the storage array; wherein the second direction is parallel to the second side;
wherein the first direction and the second direction are perpendicular to each other and parallel to the substrate.
3. The phase change memory according to claim 1,
the height of the first heat dissipation layer is larger than or equal to the height of the memory array along the direction perpendicular to the substrate.
4. The phase change memory according to claim 1, wherein the heat dissipation unit is conductive, the phase change memory comprising:
and the insulating dielectric layer is positioned between the storage array and the first heat dissipation layer.
5. The phase change memory according to claim 1,
along a direction perpendicular to the substrate, a first projection of the storage array to the substrate is located within a second projection of the second heat dissipation layer to the substrate.
6. A method of manufacturing a phase change memory, comprising:
providing a substrate;
forming a memory array on a first surface of the substrate;
forming a heat dissipation unit around the memory array; wherein, the heat dissipation unit includes:
a first heat dissipation layer located on a side of the memory array; wherein the sides of the memory array are perpendicular to the substrate;
and/or the presence of a gas in the gas,
a second heat sink layer on a second surface of the substrate; wherein the first surface and the second surface are two surfaces oppositely arranged to the substrate.
7. The method of claim 6, wherein forming a heat-dissipating unit around the memory array when the heat-dissipating unit comprises the first heat-dissipating layer comprises:
forming a first heat dissipation sub-layer extending along a first direction on a first side face of the memory array; wherein the first direction is parallel to the first side, the first heat dissipation layer comprises the first heat dissipation sublayer;
and/or the presence of a gas in the gas,
forming a second heat dissipation sub-layer extending along a second direction on a second side of the memory array; wherein the second direction is parallel to the second side, the first heat dissipation layer comprising the second heat dissipation sublayer;
wherein the first direction and the second direction are perpendicular to each other and parallel to the substrate.
8. The method of claim 6,
the method further comprises the following steps:
forming an insulating dielectric layer surrounding the side face of the storage array; wherein, along the direction vertical to the substrate, the height of the dielectric layer is larger than or equal to that of the memory array;
when the heat dissipation unit includes the first heat dissipation layer, the forming the heat dissipation unit around the memory array includes:
forming a groove vertical to the substrate in the dielectric layer; filling the groove with the material of the first heat dissipation layer, thereby forming the first heat dissipation layer; wherein, along the direction vertical to the substrate, the height of the groove is larger than or equal to the height of the memory array.
9. The method of claim 6, wherein the storage array comprises: at least two memory sub-arrays arranged in a stack in a direction perpendicular to the substrate, the method comprising:
after a first memory sub-array is formed, forming a first heat dissipation unit around the first memory sub-array;
after the first heat dissipation unit is formed, at least one memory sub-array is formed on the first memory sub-array;
forming a second heat dissipation unit on the first heat dissipation unit after the at least one memory sub-array is formed; wherein the second heat dissipating unit surrounds the at least one memory sub-array.
10. The method of claim 6, wherein forming a heat-dissipating unit around the memory array when the memory array comprises a second heat-dissipating layer comprises:
depositing the material of the second heat sink layer on the second surface of the substrate, thereby forming the second heat sink layer; wherein the second surface and the first surface are two surfaces arranged opposite to the substrate.
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