CN112599587B - A semiconductor device with a buffer layer structure - Google Patents

Abstract

The invention belongs to the field of power semiconductor device testing, and in particular relates to a semiconductor device with a buffer layer structure, comprising a first dopant region, a second dopant region, and a third dopant region arranged in sequence, and further comprising an optional or a plurality of upper dopant regions, lower dopant regions, and middle dopant regions arranged in combination; the upper dopant region is located between the first dopant region and the second dopant region; the The lower dopant region is located between the second dopant region and the third dopant region; the middle dopant region is located in the middle of the second dopant region, and the present invention has the advantage that smaller leakage can be achieved current, thereby improving the withstand voltage capability of the device, as well as the maximum junction temperature that can be operated, and increasing the current capacity of the device.

Description

A semiconductor device with a buffer layer structure

technical field

The invention belongs to the field of power semiconductor device testing, in particular to a semiconductor device with a buffer layer structure.

Background technique

As the core component of power equipment, large-capacity power electronic devices have gradually become the key to improving reliability and reducing costs. In the application of unidirectional flow and bidirectional blocking, the device is required to have reverse blocking capability, so the method of connecting an asymmetric device and a diode in series is generally used. The reverse resistance device has forward flow and bidirectional blocking capabilities, which can save series diodes, reduce the number of devices, save costs, and reduce losses. It has significant advantages in applications such as current source converters and bidirectional solid state circuit breakers.

The traditional asymmetric device changes the electric field distribution by setting the buffer layer or the field stop layer, and reduces the overall thickness of the device under the condition of ensuring the same withstand voltage, thereby reducing the parameters such as the on-voltage drop, and belongs to the punch-through structure. The non-punch-through IGCT structure with the buffer layer and its internal electric field distribution are shown in FIG. 1 , and the punch-through IGCT structure and its internal electric field distribution are shown in FIG. 2 . The buffer layer can change the electric field distribution from triangular to trapezoidal, greatly reducing the thickness requirement.

In order to achieve reverse voltage withstand capability, the buffer layer structure shown in Figure 1 cannot be used for the reverse resistance device. This is because if both sides of the PN junction are highly doped, the electric field distribution is concentrated on both sides of the junction, and the peak electric field strength exceeds the critical electric field. After the strength, the PN junction will have avalanche breakdown at very low voltage. After the buffer layer structure is removed, the subsequent problem is that the leakage current of the device increases, especially the leakage current at high temperature.

The leakage current of the reverse resistance device mainly consists of two parts, the body leakage current and the edge leakage current. Under the same voltage level, if the same edge termination structure is used, the edge leakage current of the asymmetric device and the reverse resistance device are theoretically the same, but the body leakage current is completely different. The body leakage current consists of two parts, one is generated by the diffusion of free carriers, and the other is generated in the space charge region. Among them, the leakage current generated by free carrier diffusion is closely related to the amplification factor of the PNP transistor.

Taking the traditional reverse resistance IGCT as an example, when the gate cathode is short-circuited, the depletion layer distribution in the forward blocking state is shown in Figure 3, where W is the extension width of the depletion layer, and L is the undepleted width of the drift region. As the voltage increases, the width of the undepleted layer gradually decreases. The holes injected from the anode side pass through the undepleted layer under the action of diffusion motion. Under the action of the strong electric field in the space charge region, the carriers drift to the cathode. , forming part of the leakage current. In order to realize the reverse blocking capability of the reverse resistance device, the J1 junction needs to ensure that one side of the junction is low-doped, so that in the blocking state, the anode side of the reverse resistance device has a higher emission efficiency and a larger amplification factor of the PNP transistor.

The structure of the traditional reverse resistance device is shown in Figure 4. The device consists of a first dopant region, a second dopant region and a third dopant region. The first dopant region often has an emitter structure. When considering device blocking, this part of the structure can be ignored. The first dopant region is connected to the cathode and the second dopant region, and the third dopant region is connected to the anode and the second dopant region. If the first dopant region of the device is P-type doped, the second dopant region is N-type doped, and the third dopant region is P-type doped, when the device anode withstands the forward voltage, the first The withstand voltage of the PN junction between the dopant and the second dopant; when the anode of the device withstands the reverse voltage, the withstand voltage of the PN junction between the second dopant and the third dopant is used.

SUMMARY OF THE INVENTION

In HVDC application scenarios, the blocking voltage level of the switching device needs to be as high as possible, and the leakage current should be as small as possible. The smaller leakage current can not only reduce the loss of the system, but also improve the withstand voltage capability of the device, as well as the maximum junction temperature that can be operated, and increase the current capacity of the device. In order to solve the above problems, the present patent proposes a semiconductor device with a buffer layer structure.

The specific technical solutions are as follows:

A semiconductor device with a buffer layer structure, comprising a first dopant region (1), a second dopant region (2), and a third dopant region (3) arranged in sequence, and further comprising selecting one or more an upper dopant region (4), a lower dopant region (5), and a middle dopant region (6) arranged in combination;

the upper dopant region (4) is located between the first dopant region (1) and the second dopant region (2);

the lower dopant region (5) is located between the second dopant region (2) and the third dopant region (3);

The central dopant region (6) is located in the middle of the second dopant region (2).

Specifically, the upper dopant region (4) and the lower dopant region (5) are located at the positions of the PN junctions subjected to withstand voltage

Specifically, the upper dopant region (4) and the lower dopant region (5) are of the same doping type as the second dopant region (2).

Specifically, the upper dopant region (4) and the lower dopant region (5) are N-type doped.

Specifically, the thickness of the upper dopant region (4) and the lower dopant region (5) is 1-10 um.

Specifically, the doping concentration of the upper dopant region (4) and the lower dopant region (5) is greater than the concentration of the second dopant region (2) and smaller than that of the third dopant region (3). ) peak concentration.

Specifically, the doping concentration range of the upper dopant region (4) and the lower dopant region (5) is 1e13-1e16 cm ⁻³ .

Specifically, two sides of the middle dopant region (6) are respectively a second upper dopant region (21) and a second dopant lower region (22); the middle dopant region (6) The thicknesses of both are smaller than the thicknesses of the second dopant upper region (21) and the second dopant lower region (22). .

Specifically, the thickness of the central dopant region (6) ranges from 1 to 50 um.

Specifically, if the doping type of the central dopant region (6) is the same as the type of the two parts by which the second dopant region (2) is divided, the doping concentration of the central dopant region (6) is greater than that of the second dopant region (2). Doping concentration of the dopant region (2).

Specifically, the doping concentration range of the central dopant region (6) is 1e13-1e16 cm ⁻³ .

The advantages of the present invention are:

(1) The corresponding structure when the upper dopant region and the lower dopant region are provided, since the doping concentration of the transparent buffer layer is higher than that of the n-base region, according to the Poisson equation, the electric field intensity of the transparent buffer layer has a larger slope. However, because the transparent buffer layer is very thin, its actual adjustment effect on the electric field distribution is very small, or even negligible. In this case, the device is still a non-punch-through type, which can ensure the bidirectional blocking capability of the device. The transparent buffer layer can reduce the emission efficiency of PNP transistors at low current density, and greatly reduce the leakage current formed by the diffusion of free carriers without increasing the thickness of the film, which is especially suitable for various semiconductor reverse resistance devices.

(2) The structure of the central dopant region has a modulating effect on the electric field, and the coordination of the doping concentration and thickness of the second dopant upper region, the second dopant lower region, and the middle dopant region can reduce the overall sheet thickness , thereby reducing the voltage drop of the device, and at the same time, it can effectively suppress the leakage current formed by the diffusion of free carriers, reduce the loss of the system, and at the same time improve the maximum operating junction temperature of the device and increase the current capacity of the device. .

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

Figure 1 is a non-punch-through IGCT structure and its internal electric field distribution diagram;

Fig. 2 is the punch-through IGCT structure and its internal electric field distribution diagram;

Figure 3 is the traditional reverse resistance IGCT depletion layer distribution diagram;

Figure 4 is a structural diagram of a traditional reverse resistance device;

5 is a semiconductor device structure having an upper dopant region and a lower dopant region;

6 is a semiconductor device structure with a central dopant region;

7 is a structural diagram of a reverse-resistance IGCT with an upper dopant region and a lower dopant region, and a diagram of electric field strengths at different positions corresponding to forward withstand voltage and reverse withstand voltage;

FIG. 8 is a structural diagram of a reverse resistance IGCT with a central dopant region, and electric field strength diagrams at different positions corresponding to forward withstand voltage and reverse withstand voltage.

The reference numerals are explained as follows:

1. first dopant region; 2. second dopant region; 21, second dopant upper region; 22, second dopant lower region; 3, third dopant region; 4, upper Dopant region; 5. Lower dopant region; 6. Middle dopant region

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

A semiconductor device with a buffer layer structure, comprising a first dopant region 1, a second dopant region 2, and a third dopant region 3 arranged in sequence, and further comprising the first dopant region 1 and the third dopant region 3. At least one other dopant region is also included between the three dopant regions 3 . Specifically, the other dopant region includes the following technical solutions: as shown in FIGS. 5-6 , the upper dopant located between the first dopant region 1 and the second dopant region 2 region 4, lower dopant region 5 located between second dopant region 2 and third dopant region 3, middle dopant region 6 located in the middle of second dopant region 2; Explanation of specific plans.

The first option is as follows:

As shown in FIG. 5, an upper dopant region 4 and a lower dopant region 5 are provided simultaneously. The upper dopant region 4 and the lower dopant region 5 are located at the PN junction position that withstands the withstand voltage; the doping type of the upper dopant region 4 and the lower dopant region 5 is the same as that of the second dopant region 2 , in a specific embodiment of the reverse resistance device, the second dopant type is N-type doping; in the semiconductor structure, both P-type doping and N-type doping are acceptable. Both the upper dopant region 4 and the lower dopant region 5 have a thickness of 1-10 um, and their doping concentration is greater than that of the second dopant region 2 and the peak concentration of the third dopant region 3 . In this scheme, the doping concentration of the upper dopant region 4 and the lower dopant region 5 is 1e13-1e16 cm ⁻³ .

When this scheme is applied to a specific reverse resistance IGCT, as shown in FIG. 7 , the first dopant region 1 is a p-based region, the second dopant region 2 is an n-based region, and the third dopant region is The region 3 is the P+ emitter, the upper dopant region 4 is located between the P base region and the n- base region, and the lower dopant region 5 is located between the n- base region and the P+ emitter, wherein the outside of the P base region is provided with In the P+ base region, an n+ emitter is arranged as a cathode in the outer middle of the P+ base region, and gate electrodes are arranged on both sides. The upper dopant region 4 and the lower dopant region 5 are collectively referred to as a transparent buffer layer. In this scheme, the thickness of the P+ emitter on the anode side is 50-120um, and the peak doping concentration is 1e14-1e16cm ^-3 ; the thickness of the n+ emitter in the cathode region is 10-25um, and the peak doping concentration is 1e18-1e21cm ^-3 ; The thickness of the P+ base region is 30-60um, and the peak doping concentration is 1e16-1e18cm ^-3 ; The thickness of the P base region is 50-120um, and the peak doping concentration is 1e14-5e15cm ^-3 ; The doping concentration of the n-base region in the drift region Between 5e11-1e14cm ^-3 , in this scheme less than 5e13cm ^-3 ; the above peak doping concentration refers to the net doping concentration, which refers to the maximum concentration in each layer in the actual structure.

The electric field distribution of the structure under forward voltage and reverse voltage is shown in Figure 7. Since the doping concentration of the transparent buffer layer is higher than that of the n-base region, according to Poisson's equation, the change slope of the electric field strength of the transparent buffer layer is relatively large. . However, because the transparent buffer layer is very thin, its actual adjustment effect on the electric field distribution is very small, or even negligible. In this case, the device is still a non-punch-through type, which can ensure the bidirectional blocking capability of the device. The transparent buffer layer can reduce the emission efficiency of PNP transistors at low current density, and greatly reduce the leakage current formed by the diffusion of free carriers without increasing the thickness of the film, which is especially suitable for various semiconductor reverse resistance devices.

The second option is as follows:

As shown in FIG. 6 , a middle dopant region 6 is provided in the middle of the second dopant region 2 , and the middle dopant region 6 divides the second dopant region 2 in the conventional structure into two parts, an upper and lower part, They are the second dopant upper region 21 and the second dopant lower region 22, respectively. In this scheme, the middle dopant region 6 is located in the center of the overall structure; the doping type of the middle dopant region 6 can be the same as that of the second dopant region 2, or it can be opposite to it; if the middle dopant region 6 The doping type is the same as that of the second dopant region 2 , and its doping concentration is greater than that of the second dopant region 2 . The thickness of the middle dopant region 6 is both smaller than that of the second dopant upper region 21 and the second dopant lower region 22 , specifically, less than 50 μm.

This scheme is applied to a specific reverse resistance IGCT, as shown in Figure 8, wherein the first dopant region 1 is a p-based region, the second dopant region 2 is an n-based region, and the third dopant region is 3 is a P+ emitter, and the middle dopant region 6 divides the second dopant region 2 into a second dopant upper region 21 and a second dopant lower region 22, wherein P+ is provided outside the P base region In the base region, an n+ emitter is set as a cathode in the outer middle of the P+ base region, and gate electrodes are set on both sides. In this solution, the doping type of the central dopant region 6 may be N-type doping or P-type doping. Specifically, the thickness of the central dopant region 6 ranges from 1 to 50um, and The impurity concentration range is 1e13-1e16cm ^-3 ; the characteristics of the anode side P+ emitter, P base region, and P+ base region in this structure are the same as those of the reverse resistance IGCT with a transparent buffer layer in the first method. When the doping type of the central dopant region 6 is different, the electric field distribution is also different. When the doping type of the central dopant region 6 is N-type doping, the electric field distribution during the forward withstand voltage is shown as the forward withstand voltage 1 in FIG. The upper region 21 and the second lower dopant region 22 are the same, but have a greater slope than the second upper dopant region 21 and the second lower dopant region 22 . When the doping type of the central dopant region 6 is P-type doping, the electric field distribution during the forward withstand voltage is shown as the forward withstand voltage 2 in FIG. The upper region 21 and the second dopant lower region 22 are opposite.

The structure of the middle dopant region 6 has a modulating effect on the electric field, and the coordination of the doping concentration and thickness of the second dopant upper region 21, the second dopant lower region 22, and the middle dopant region 6 can reduce the overall sheet Thickness, thereby reducing the voltage drop of the device, and at the same time, it can effectively suppress the leakage current formed by the diffusion of free carriers, reduce the loss of the system, and at the same time increase the maximum operating junction temperature of the device and increase the current of the device. ability.

Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these Modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (5)

1. A semiconductor device having a buffer layer structure, the semiconductor device is a reverse resistance IGCT, comprising a first dopant region (1), a second dopant region (2), and a third dopant region (2) arranged in sequence Region (3), characterized by, also comprising an upper dopant region (4), a lower dopant region (5) and a central dopant region (6); Wherein, the first dopant region (1) is a P base region, the second dopant region (2) is an n-base region, and the third dopant region (3) is a P+ emitter , a P+ base region is arranged on the outside of the P base region, an n+ emitter is arranged as a cathode in the outer middle of the P+ base region, and a gate electrode is arranged on both sides of the n+ emitter; the upper dopant region (4) and the lower dopant The doping concentration of the region (5) is greater than the concentration of the second dopant region (2); the upper dopant region (4) and the lower dopant region (5) are located at the positions of the PN junctions subjected to withstand voltage, the upper dopant region (4) and the lower dopant region (5) The thickness of the dopant region (4) and the lower dopant region (5) is 1-10 μm; the upper dopant region (4) and the lower dopant region (5) are buffer layers, and the upper dopant region (4) and the lower dopant region (5) are buffer layers. The dopant region (4) and the lower dopant region (5) are of the same doping type as the second dopant region (2); the upper dopant region (4) is located between the first dopant region (1) and the second dopant region (2); the lower dopant region (5) is located between the second dopant region (2) and the third dopant region (3); The middle dopant region (6) is located in the middle of the second dopant region (2), the middle dopant region (6) is N-type doped or P-type doped, and the middle dopant region (6) is N-type doped or P-type doped (6) The two sides are respectively the second dopant upper region (21) and the second dopant lower region (22); the thickness of the middle dopant region (6) is smaller than that of the second dopant upper region (21) and the thickness of the second dopant region (22), if the doping type of the central dopant region (6) is the same as the type of the two parts by which the second dopant region (2) is divided, the central dopant region (2) is of the same type. The doping concentration of the dopant region (6) is greater than the doping concentration of the second dopant region (2). 2 . The semiconductor device having a buffer layer structure according to claim 1 , wherein the doping concentration of the upper dopant region ( 4 ) and the lower dopant region ( 5 ) is less than that of the third dopant region. 3 . Peak concentration of dopant region (3). 3. A semiconductor device with a buffer layer structure according to claim 1, wherein the doping concentration range of the upper dopant region (4) and the lower dopant region (5) is 1e13- 1e16cm ^-3 . 4 . The semiconductor device with a buffer layer structure according to claim 1 , wherein the thickness of the central dopant region ( 6 ) ranges from 1 to 50 μm. 5 . 5 . The semiconductor device with a buffer layer structure according to claim 1 , wherein the doping concentration of the central dopant region ( 6 ) ranges from 1e13 to 1e16 cm ⁻³ . 6 .

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