CN112599571A - Display panel - Google Patents
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- CN112599571A CN112599571A CN202011443916.6A CN202011443916A CN112599571A CN 112599571 A CN112599571 A CN 112599571A CN 202011443916 A CN202011443916 A CN 202011443916A CN 112599571 A CN112599571 A CN 112599571A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 158
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 128
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 128
- 230000000149 penetrating effect Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims description 142
- 239000000463 material Substances 0.000 claims description 11
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 10
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 239000011787 zinc oxide Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The application provides a display panel, display panel includes: a substrate; the first polycrystalline silicon transistor comprises a first polycrystalline silicon active layer, the first polycrystalline silicon active layer comprises a first polycrystalline silicon channel, a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are positioned on two opposite sides of the first polycrystalline silicon channel; the first metal oxide transistor comprises a first metal oxide active layer, the first metal oxide active layer comprises a first metal oxide channel, a second source electrode and a second drain electrode, the second source electrode and the second drain electrode are positioned on two opposite sides of the first metal oxide channel, and the first metal oxide active layer is positioned above the first polycrystalline silicon active layer; the insulating layer is arranged between the first metal oxide active layer and the first polycrystalline silicon active layer; one of the second source electrode and the second drain electrode is electrically connected with one of the first source electrode and the first drain electrode through a first via hole penetrating through the insulating layer.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel.
Background
As shown in fig. 1, it is a schematic cross-sectional view of a conventional Low-Temperature polysilicon Oxide (Low-Temperature polysilicon Oxide) display panel. The display panel 200 includes a low temperature polysilicon transistor M1 and a metal oxide transistor M2. The low temperature polysilicon transistor M1 includes a low temperature polysilicon active layer including a low temperature polysilicon channel M1a, a first source M1b and a first drain M1c, wherein the first source M1b and the first drain M1c are located at two opposite sides of the low temperature polysilicon channel M1 a. The metal oxide transistor M2 includes a metal oxide active layer including a metal oxide channel M2a, a second source M2b and a second drain M2c, the second source M2b and the second drain M2c are located at two opposite sides of the metal oxide channel M2 a. One end of the bridging lead 1 is electrically connected to the low temperature polysilicon active layer through the first via 200a, and the other end of the bridging lead 1 is electrically connected to the metal oxide active layer through the second via 200 b. Before the bridge lead 1 is formed, the first via 200a and the second via 200b need to be formed at the same time, and in order to improve the overlap resistance between the low temperature polysilicon active layer and the bridge lead 1, the native oxide layer structure on the polysilicon active layer needs to be removed by cleaning with hydrofluoric acid during the manufacturing process.
Therefore, a technical solution is needed to solve the problem that the performance of the metal oxide active layer is affected due to the bridging of the metal oxide active layer and the low temperature polysilicon active layer by the bridging wires and the cleaning of the low temperature polysilicon active layer.
Disclosure of Invention
The present application is directed to a display panel, which avoids affecting the performance of a metal oxide active layer of the display panel.
A display panel, the display panel comprising:
a substrate;
the first polycrystalline silicon transistor comprises a first polycrystalline silicon active layer, the first polycrystalline silicon active layer comprises a first polycrystalline silicon channel, a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are positioned on two opposite sides of the first polycrystalline silicon channel;
a first metal oxide transistor comprising a first metal oxide active layer comprising a first metal oxide channel, a second source and a second drain, the second source and the second drain being on opposite sides of the first metal oxide channel, the first metal oxide active layer being over the first polysilicon active layer; and
an insulating layer disposed between the first metal oxide active layer and the first polysilicon active layer;
wherein one of the second source and the second drain is electrically connected to one of the first source and the first drain through a first via hole penetrating the insulating layer.
Has the advantages that: the application provides a display panel, one of a second source electrode and a second drain electrode of a first metal oxide active layer is electrically connected with one of a first source electrode and a first drain electrode of a first polycrystalline silicon transistor through a first via hole penetrating through an insulating layer, so that the polycrystalline silicon active layer can be cleaned before the metal oxide active layer is formed, the performance of the metal oxide active layer cannot be influenced, and the situation that when a bridging lead is adopted to bridge the first metal oxide active layer and the first polycrystalline silicon active layer, a via hole for bridging is required to be formed simultaneously to cause damage to the metal oxide active layer when the polycrystalline silicon active layer is cleaned is avoided. In addition, the second source electrode and the second drain electrode of the first metal oxide active layer are transparent, metal wiring for overlapping can be reduced, the aperture opening ratio is improved, and therefore the resolution ratio of the display panel is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional LTPS-Si display panel;
FIG. 2 is a schematic diagram of a pixel driving circuit of a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional view of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The application provides a display panel, display panel is flexible organic light emitting diode display panel. The display panel comprises a plurality of pixel driving circuits arranged in an array.
As shown in fig. 2, the pixel driving circuit includes a first polysilicon transistor M1, a second polysilicon transistor M2, a first metal oxide transistor M3, a second metal oxide transistor M4, a third polysilicon transistor M5, a fourth polysilicon transistor M6, a fifth polysilicon transistor M7, a light emitting device OLED, and a capacitor C. The first polysilicon transistor M1 is a second switch control transistor, the second polysilicon transistor M2 is a driving transistor, the first metal oxide transistor M3 is a compensation transistor, the second metal oxide transistor M4 is an initialization transistor, the third polysilicon transistor M5 is a first light-emitting control transistor, the fourth polysilicon transistor M6 is a switch transistor, and the fifth polysilicon transistor M7 is a reset transistor.
The first polysilicon transistor M1, the second polysilicon transistor M2, the third polysilicon transistor M5, the fourth polysilicon transistor M6 and the fifth polysilicon transistor M7 are all low-temperature polysilicon transistors, and the first metal oxide transistor M3 and the second metal oxide transistor M4 are all metal oxide transistors. The first polysilicon transistor M1, the second polysilicon transistor M2, the first metal oxide transistor M3, the second metal oxide transistor M4, the third polysilicon transistor M5, the fourth polysilicon transistor M6 and the fifth polysilicon transistor M7 are P-type transistors.
The light emitting device OLED is an organic light emitting diode. The organic light emitting diode includes a cathode, an anode, and an organic light emitting layer between the cathode and the anode.
The gate of the second polysilicon transistor M2 is connected to the first electrode plate of the capacitor C, the source of the second metal oxide transistor M4 and the drain of the first metal oxide transistor M3, the source of the second polysilicon transistor M2 is connected to the data line d (M) through the fourth polysilicon transistor M6, the source of the second polysilicon transistor M2 is further connected to the dc power supply signal line VDD through the third polysilicon transistor M5, the drain of the second polysilicon transistor M2 is connected to the light emitting device OLED through the first polysilicon transistor M1, and the drain of the second polysilicon transistor M2 is connected to the source of the first metal oxide transistor M3. The second polysilicon transistor M2 is used to supply a driving current to the light emitting device OLED.
The fourth polysilicon transistor M6 is a switching transistor. A gate of the fourth polysilicon transistor M6 is connected to the nth stage scan signal line scan (n), a source of the fourth polysilicon transistor M6 is connected to the data line d (M), and a drain of the fourth polysilicon transistor M6 is connected to a source of the second polysilicon transistor M2 and a drain of the third polysilicon transistor M5. The fourth polysilicon transistor M6 is turned on or off according to the nth scan signal inputted from the nth scan signal line scan (n), and controls whether to output the data signal transmitted from the data line d (M) to the source of the second polysilicon transistor M2.
The gate of the first metal oxide transistor M3 is connected to the nth scan signal line scan (n), the source of the first metal oxide transistor M3 is connected to the drain of the second polysilicon transistor M2 and the source of the first polysilicon transistor M1, and the drain of the first metal oxide transistor M3 is connected to the gate of the second polysilicon transistor M2, the source of the second metal oxide transistor M4 and the first electrode plate. The first metal oxide transistor M3 is turned on or off according to an nth scan signal inputted from an nth scan signal line scan (n), and controls whether the gate of the second polysilicon transistor M2 is electrically connected to the drain of the second polysilicon transistor M2. The first metal oxide transistor M3 is a metal oxide transistor, which is beneficial to improving the problem of gate leakage of the second polysilicon transistor M2 in the process of outputting the driving current.
The gate of the second metal oxide transistor M4 is connected to the n-1 th SCAN signal line SCAN (n-1), the source of the second metal oxide transistor M4 is connected to the first electrode plate, the gate of the second polysilicon transistor M2 and the drain of the first metal oxide transistor M3, and the drain of the second metal oxide transistor M4 is connected to the initialization signal line VI and the drain of the fifth polysilicon transistor M7. The second metal oxide transistor M4 is turned on or off according to the (n-1) th SCAN signal inputted from the (n-1) th SCAN signal line SCAN (n-1), and controls whether the initialization signal inputted from the initialization signal line VI is transmitted to the gate of the second polysilicon transistor M2. The second metal oxide transistor M4 is a metal oxide transistor, which can improve the problem of gate leakage of the second polysilicon transistor M2 during the process of outputting the driving current by the second polysilicon transistor M2.
The gate of the third polysilicon transistor M5 is connected to the light emission control signal line em (n), the source of the third polysilicon transistor M5 is connected to the second electrode plate and the dc power supply signal line VDD, and the drain of the third polysilicon transistor M5 is connected to the drain of the fourth polysilicon transistor M6 and the source of the second polysilicon transistor M2. The third polysilicon transistor M5 controls whether the dc power signal transmitted by the dc power signal line VDD is transmitted to the source of the second polysilicon transistor M2 according to whether the light emission control signal transmitted by the light emission control signal line em (n) is in an on or off state.
The gate of the first polysilicon transistor M1 is connected to the light emission control signal line em (n), the source of the first polysilicon transistor M1 is connected to the drain of the second polysilicon transistor M2 and the source of the first metal oxide transistor M3, and the drain of the first polysilicon transistor M1 is connected to the anode of the light emitting device OLED and the source of the fifth polysilicon transistor M7. The first polysilicon transistor M1 controls whether the driving current is output to the light emitting device OLED or not according to whether the light emission control signal transmitted by the light emission control signal line em (n) is on or off.
The gate of the fifth polysilicon transistor M7 is electrically connected to the nth stage scan signal line scan (n), the source of the fifth polysilicon transistor M7 is connected to the drain of the first polysilicon transistor M1 and the anode of the light emitting device OLED, and the drain of the fifth polysilicon transistor M7 is connected to the drain of the second metal oxide transistor M4 and the initialization signal line VI. The fifth polysilicon transistor M7 is turned on or off according to the nth scan signal transmitted through the nth scan signal line scan (n), and controls whether or not to output the initialization signal transmitted through the initialization signal line to the anode of the light emitting device OLED.
A first electrode plate of the capacitor C is connected to the gate of the second polysilicon transistor M2, the drain of the first metal oxide transistor M3, and the source of the second metal oxide transistor M4, and a second electrode plate of the capacitor C is connected to the dc power supply signal line VDD and the source of the third polysilicon transistor M5.
Fig. 3 is a schematic cross-sectional view of a display panel according to an embodiment of the present application. The display panel includes a substrate 101, a buffer layer 102, an inorganic stack 103, a first polysilicon transistor M1, a first metal oxide transistor M3, a second polysilicon transistor M2, and a second metal oxide transistor M4.
The substrate 101 is a flexible substrate. The substrate 101 includes two polyimide layers and a barrier layer between the two polyimide layers. The barrier layer is made of at least one material selected from silicon nitride and silicon oxide.
The buffer layer 102 is disposed on the substrate 101. The buffer layer 102 is made of at least one of silicon oxide and silicon nitride. The buffer layer 102 functions to protect the substrate 101.
The inorganic stack 103 includes a silicon nitride layer, a silicon oxide layer, and an amorphous silicon layer sequentially disposed on the buffer layer 102. The silicon nitride layer functions to block impurities in the substrate 101. The silicon oxide layer plays a role in heat preservation. The amorphous silicon layer is subsequently treated by a dehydrogenation process, so that hydrogen explosion in the excimer laser annealing process caused by overhigh hydrogen content in the amorphous silicon is prevented.
The first polysilicon transistor M1 includes a first polysilicon active layer including a first polysilicon channel M1a, a first source M1b and a first drain M1c, the first source M1b and the first drain M1c being located at opposite sides of the first polysilicon channel M1 a. The first polysilicon active layer is disposed on the inorganic stack 103. The first polysilicon active layer is a low temperature polysilicon active layer, and the first source M1b and the first drain M1c are obtained by ion doping the low temperature polysilicon active layer.
The first metal oxide transistor M3 includes a first metal oxide active layer including a first metal oxide channel M3a, a second source M3b and a second drain M3c, a second source M3b and a second drain M3c on opposite sides of the first metal oxide channel M3a, a second gate M32 and a third gate M33. The first metal oxide active layer is made of indium gallium zinc oxide, wherein the second source electrode M3b and the second drain electrode M3c are obtained by conducting the indium gallium zinc oxide layer by any one of, but not limited to, plasma treatment, doping and implantation.
The first metal oxide active layer is positioned above the first polysilicon active layer. An insulating layer is disposed between the first metal oxide active layer and the first polysilicon active layer. One of the second source M3b and the second drain M3c is electrically connected to one of the first source M1b and the first drain M1c through a first via penetrating through the insulating layer, so as to achieve the electrical connection between the first metal oxide transistor M3 and the first polysilicon transistor M1, and in the manufacturing process, the first polysilicon active layer of the first polysilicon transistor M1 may be cleaned by hydrofluoric acid to remove the native oxide layer and then form the first metal oxide active layer, thereby preventing the hydrofluoric acid from affecting the performance of the first metal oxide active layer. In addition, the second source electrode M3b and the second drain electrode M3c of the first metal oxide active layer are both transparent, so that metal wiring for overlapping can be reduced, the aperture ratio of the display panel can be improved, and the preparation of the display panel with high resolution can be facilitated.
Specifically, the insulating layer includes a first insulating layer 104, a second insulating layer 105, and a third insulating layer 106, and the second insulating layer 105 is disposed between the first insulating layer 104 and the third insulating layer 106. The first insulating layer 104 is disposed adjacent to the first polysilicon active layer, and the first insulating layer 104 covers the first polysilicon active layer and the inorganic stack. The second insulating layer 105 is disposed on the first insulating layer 104. The third insulating layer 106 is disposed adjacent to the first metal oxide active layer, and the first metal oxide active layer is disposed on the third insulating layer 106. The thickness of the first insulating layer 104 is 1500 angstroms to 2500 angstroms, the thickness of the second insulating layer 105 is 1500 angstroms to 2500 angstroms, and the thickness of the third insulating layer 106 is 4500 angstroms to 6000 angstroms. The first insulating layer 104 and the second insulating layer 105 are made of a material selected from at least one of silicon nitride and silicon oxide. The third insulating layer 106 is made of at least one material selected from silicon nitride and silicon oxide.
The second source M3b is electrically connected to the first source M1b through a first via 100b penetrating the first insulating layer 104, the second insulating layer 105 and the third insulating layer 106, so that the first metal oxide transistor M3 is electrically connected to the first polysilicon transistor M1.
The second polysilicon transistor M2 includes a second polysilicon active layer and a first gate M22, the first gate M22 is located above the second polysilicon active layer and is disposed corresponding to the second polysilicon active layer, the second polysilicon active layer and the first polysilicon active layer are disposed at the same layer, and a first insulating layer 104 is disposed between the first gate M22 and the second polysilicon active layer. The second polysilicon active layer includes a second polysilicon channel M2a, a fourth source M2b and a fourth drain M2c, and the fourth source M2b and the fourth drain M2c are located at opposite sides of the second polysilicon active layer M2 a. The fourth drain M2c of the second polysilicon active layer is electrically connected to the first source M1b of the first polysilicon active layer through the conductive polysilicon active layer, so as to electrically connect the first polysilicon transistor M1 to the second polysilicon transistor M2, and further electrically connect the fourth drain M2c of the second polysilicon transistor M2 to the first source M1b of the first metal oxide transistor M3.
The other of the second source M3b and the second drain M3c is electrically connected to the first gate M22 through a second hole 100b penetrating through the second insulating layer 105 and the third insulating layer 106, and since the second source M3b and the second drain M3c are both transparent wires, the overlapping wire between the second drain M3c of the first metal oxide transistor M3 and the first gate M22 of the second polysilicon transistor M2 is transparent, so that the aperture ratio is further improved, and the resolution of the display panel is further improved.
Specifically, the second drain M3c is electrically connected to the first gate M22 through a second hole 100b penetrating through the second insulating layer 105 and the third insulating layer 106, so that the second drain M3c of the first metal oxide transistor M3 is electrically connected to the first gate M22 of the second polysilicon transistor M2.
The display panel 100 further includes an electrode plate C2, the electrode plate C2 is located above the first gate M22 and is disposed corresponding to the first gate M22, a second insulating layer 105 is disposed between the electrode plate C2 and the first gate M22, and a third insulating layer 106 is disposed between the first metal oxide active layer and the electrode plate C2. The first gate M22 is a first electrode plate of the capacitor, the electrode plate C2 is a second electrode plate of the capacitor, and the first gate M22 and the electrode plate C2 form the capacitor. The electrode plate C2 is disposed corresponding to the second polysilicon channel M2a of the second polysilicon active layer.
The second metal oxide transistor M4 includes a second metal oxide active layer including a second metal oxide channel M4a, a third source M4b and a third drain M4c, a fourth gate M42 and a fifth gate M43, and the third source M4b and the third drain M4c are located at two opposite sides of the second metal oxide channel M4 a. The second metal oxide active layer and the first metal oxide active layer are arranged on the same layer. The second metal oxide active layer is made of indium gallium zinc oxide, and the third source electrode M4b and the third drain electrode M4c are obtained by conducting the indium gallium zinc oxide layer. The method of conductor formation is as described above and will not be described in detail here.
One of the third source M4b and the third drain M4c is electrically connected to the first gate M22 through a third via 100c passing through the second insulating layer 105 and the third insulating layer 106, so that the second metal oxide transistor M4 is electrically connected to the first gate M22 of the second polysilicon transistor M2, and since the third source M4b and the third drain M4c are transparent, the bonding wire for electrically connecting the second metal oxide transistor M4 to the first gate M22 of the second polysilicon transistor M2 is transparent, thereby further improving the aperture ratio of the display panel, and facilitating the preparation of a high-resolution display panel.
Specifically, the third source M4b is electrically connected to the first gate M22 through a third via 100c penetrating through the second insulating layer 105 and the third insulating layer 106, and since the first gate M22 is also a first electrode plate, the third source M4b is also electrically connected to the first electrode plate.
The display panel 100 further includes an initialization signal line VI, which is disposed on the same layer as the electrode plate C2, i.e., the initialization signal line VI is disposed on the second insulating layer 105. The other of the third source M4b and the third drain M4c is electrically connected to the initialization signal line VI through the fourth via 100d penetrating through the third insulating layer 106, so that the second metal oxide transistor M4 is electrically connected to the initialization signal line VI, and since the third source M4b and the third drain M4c are both transparent and the conductive wire for electrically connecting the second metal oxide transistor M4 and the initialization signal line VI is transparent, the display panel has a higher aperture ratio, which is beneficial to achieving high resolution of the display panel.
The display panel 100 further includes a fourth insulating layer 107, and the fourth insulating layer 107 is disposed corresponding to the first metal oxide channel M3a and the second metal oxide channel M4 a. The thickness of the fourth insulating layer 107 is 1500 angstroms to 2500 angstroms. The material for forming the fourth insulating layer 107 is at least one of silicon oxide and silicon nitride.
The second gate M32 is disposed in the same layer as the electrode plate C2, the second gate M32 is disposed on the second insulating layer 105, and the second gate M32 is disposed corresponding to the first metal oxide channel M3 a. The third gate M33 is disposed on the fourth insulating layer 107, and the third gate M33 is disposed corresponding to the first metal oxide channel M3a, i.e., the first metal oxide transistor M3 is a double-gate transistor.
The fourth gate M42 is disposed on the same layer as the electrode plate C2, the fourth gate M42 is disposed on the second insulating layer 105, and the fourth gate M42 is disposed corresponding to the second metal oxide channel M4 a. The fifth gate M43 is disposed on the fourth insulating layer 107, and the fifth gate M43 is disposed corresponding to the second metal oxide channel M4a, i.e., the second metal oxide transistor M4 is a double-gate transistor.
The display panel 100 further includes a fifth insulating layer 108, wherein the fifth insulating layer 108 covers the first metal oxide active layer, the second metal oxide active layer, the third insulating layer 106 and the fourth insulating layer 107. The thickness of the fifth insulating layer 108 is 4500 a-6000 a, and the fifth insulating layer 108 is made of at least one material selected from silicon nitride and silicon oxide.
The display panel 100 further includes an anode lead 111, wherein the anode lead 111 is disposed on the fifth insulating layer 108 and electrically connected to the other of the first source M1b and the first drain M1c through a fifth via 100e penetrating through the fifth insulating layer 108, the third insulating layer 106, the second insulating layer 105 and the first insulating layer 104. Specifically, the anode lead 111 is electrically connected to the first drain M1c through a fifth via 100e penetrating through the fifth insulating layer 108, the third insulating layer 106, the second insulating layer 105, and the first insulating layer 104. The fifth via hole 100e is opened separately from the first via hole 100a, the second via hole 100b, the third via hole 100c, and the fourth via hole 100e, which is more favorable for avoiding damage to the metal oxide active layer when the low temperature polysilicon active layer is cleaned.
The display panel 100 further includes a sixth insulating layer disposed on the anode lead 111 and the fifth insulating layer 108. The sixth insulating layer includes a planarization layer 1092 and a passivation layer 1091, the passivation layer 1091 covers the anode lead 111 and the fifth insulating layer 108, and the planarization layer 1092 is disposed on the passivation layer 1091. The passivation layer 1091 is made of at least one material selected from silicon oxide and silicon nitride, and the thickness of the passivation layer 1091 is 1500 angstroms to 2500 angstroms. The preparation material of the planarization layer 1092 is polyimide or polyacrylate, etc., and the thickness of the planarization layer 1092 is 1.5 micrometers-2.5 micrometers.
The display panel 100 further includes an anode 112, wherein the anode 112 is disposed on the sixth insulating layer and electrically connected to the anode lead 111 through a sixth via 100f penetrating through the sixth insulating layer. The anode 112 is made of at least one material selected from silver, copper, and indium tin oxide.
The display panel 100 further includes a pixel defining layer 110, the pixel defining layer 110 is disposed on the sixth insulating layer and has an opening corresponding to the anode 112, and the organic light emitting layer is disposed in the opening and on the anode 112.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
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