CN112596444A

CN112596444A - Electronic equipment shutdown control method and system

Info

Publication number: CN112596444A
Application number: CN202011523581.9A
Authority: CN
Inventors: 杨文继; 谷和勇; 顾晓敏; 浦虹; 曹李军; 张琰
Original assignee: Suzhou Keda Technology Co Ltd
Current assignee: Suzhou Keda Technology Co Ltd
Priority date: 2020-12-21
Filing date: 2020-12-21
Publication date: 2021-04-02

Abstract

The invention provides a method and a system for controlling shutdown of electronic equipment, wherein the method comprises the following steps: detecting a shutdown key signal of the electronic equipment; sending a shutdown request to a currently running application program; receiving a shutdown feedback signal returned by the application program; and determining whether to execute shutdown operation according to the shutdown feedback signal. By adopting the invention, when the shutdown key signal of the electronic equipment is detected, the shutdown operation is not immediately executed, but whether the shutdown operation can be executed or not is determined by sending the shutdown request to the application program and receiving the shutdown feedback signal, so that the delayed shutdown when the shutdown key of the electronic equipment is pressed is realized, and the problem of data loss caused by misoperation of personnel or forced shutdown by using a power key during abnormal shutdown is solved.

Description

Electronic equipment shutdown control method and system

Technical Field

The present invention relates to the field of data processing technologies, and in particular, to a shutdown control method and system for an electronic device.

Background

There are many schemes for preventing Data loss in the storage field, such as UPS (Uninterruptible Power Supply), BBU (Base Band unit), DCPMM (Data Center Persistent Memory) of Intel, and so on; the storage of the existing data is realized at the time of power failure or shutdown of the data to prevent the data from being lost in abnormal conditions.

In the UPS technology, a backup power supply is externally configured in storage system equipment, and sufficient time is provided for supplying power to a system during abnormal power failure so as to protect important data by software.

The BBU is an independent system designed based on a hardware battery or a large capacitor, when the equipment is abnormally powered off, data in the memory of the equipment is written into an external storage medium (such as an EMMC (Embedded multimedia storage Card) and the like) under the condition that the data is maintained by a power supply on the BBU, and the data read from the EMMC is recovered into the memory after being powered on, so that the host is recovered to a power-down running state, the data is better protected, and the data loss is prevented.

The Intel DCPMM is a storage medium between a DDR (Double Data Rate) and an external storage set by the Intel based on an XPOINT technology, and has performance closer to the DDR and cost performance closer to the external storage medium such as an SSD (Solid State Disk). When the DCPMM is in the App Direct mode, the DCPMM has the function of power-down protection. The protocol followed is NVDIMM (Non-volatile Dual in-line Memory Module).

The three modes can effectively prevent data loss in abnormal power failure, but are not applicable to a scene that abnormal shutdown is caused by careless operation of personnel. When abnormal shutdown is caused by careless operation of personnel, the processing mechanism in abnormal power failure cannot be started, so that data loss still can be caused. The electronic device based on the ARM architecture or the electronic device based on the soar does not have a Power Management IC (Power Management IC) function, and a hardware implementation manner of delayed shutdown does not exist, so that data protection during misoperation of personnel or forced shutdown by a Power key cannot be realized.

Disclosure of Invention

The invention aims to provide a shutdown control method and system for electronic equipment, aiming at solving the problem of data loss during abnormal shutdown caused by misoperation of personnel or forced shutdown by using a power key.

The embodiment of the invention provides a shutdown control method of electronic equipment, which comprises the following steps:

detecting a shutdown key signal of the electronic equipment;

sending a shutdown request to a currently running application program;

receiving a shutdown feedback signal returned by the application program;

and determining whether to execute shutdown operation according to the shutdown feedback signal.

In some embodiments, the detecting the shutdown key signal of the electronic device includes the programmable logic device detecting the shutdown key signal of the electronic device.

In some embodiments, after the step of detecting the power-off key signal of the electronic device, the method further includes the following steps:

the programmable logic device generates a shutdown signal and sends the shutdown signal to the main control chip;

the main control chip sets the level of the first shutdown indication pin as the level indicating hardware shutdown.

In some embodiments, the sending the shutdown request to the currently running application includes the following steps:

and the driver detects that the level of the first shutdown indication pin is the level indicating hardware shutdown, and sends a shutdown request to the currently running application program.

In some embodiments, the shutdown feedback signal includes a shutdown permission signal and a shutdown non-permission signal, and determining whether to perform a shutdown operation according to the shutdown feedback signal includes the following steps:

if the driver receives a signal which does not allow the shutdown of the application program, determining not to execute shutdown operation;

and if the driver receives the allowed shutdown operation of all the application programs, determining to execute the shutdown operation.

In some embodiments, after determining to perform the shutdown operation, the method further includes:

the driver sets the level of a second shutdown indication pin of the main control chip as a level for indicating software to shut down through a register;

and when the main control chip detects that the level of the second shutdown indication pin is the level indicating the shutdown of the software, executing shutdown operation.

In some embodiments, the first power-off indication pin is a GPIO pin configured in an input mode and the second power-off indication pin is a GPIO pin configured in an output mode.

In some embodiments, the first power-off indication pin is realized by multiplexing a GPIO pin of the main control chip.

By adopting the electronic equipment shutdown control method, when the shutdown key signal of the electronic equipment is detected, the shutdown operation is not immediately executed, but whether the shutdown operation can be executed or not is determined by sending the shutdown request to the application program and receiving the shutdown feedback signal, so that the delayed shutdown when the shutdown key of the electronic equipment is pressed is realized, and the problem of data loss when abnormal shutdown is caused by misoperation of personnel or forced shutdown by using a power key is solved.

An embodiment of the present invention further provides a shutdown control system for an electronic device, which is applied to the shutdown control method for an electronic device, and the control system includes:

the shutdown detection module is used for detecting a shutdown key signal;

and the application interaction module is used for sending a shutdown request to the currently running application program, receiving a shutdown feedback signal returned by the application program, and determining whether to execute shutdown operation according to the shutdown feedback signal.

In some embodiments, the shutdown detection module is implemented by a programmable logic device, the control system further includes a main control chip, the programmable logic device generates a shutdown signal and sends the shutdown signal to the main control chip after detecting a shutdown key signal of the electronic device, and the main control chip sets a level of the first shutdown indication pin as a level indicating hardware shutdown.

In some embodiments, the application interaction module is implemented by using a driver, and the driver is configured to send a shutdown request to a currently running application program when detecting that the level of the first shutdown indication pin is a level indicating hardware shutdown.

In some embodiments, the driver is further configured to set, through a register, a level of a second shutdown indication pin of the main control chip to a level indicating shutdown of software after confirming that a shutdown operation is performed;

and the main control chip is also used for executing shutdown operation when detecting that the level of the second shutdown indication pin is the level indicating software shutdown.

By adopting the electronic equipment shutdown control system, when the shutdown detection module detects the shutdown key signal of the electronic equipment, the shutdown operation is not immediately executed, but the application interaction module firstly determines whether the shutdown operation can be executed by sending the shutdown request to the application program and receiving the shutdown feedback signal, so that the delayed shutdown when the shutdown key of the electronic equipment is pressed is realized, and the problem of data loss when abnormal shutdown is caused by misoperation of personnel or forced shutdown by using a power key is solved.

The electronic equipment shutdown control method and the electronic equipment shutdown control system can be applied to delayed shutdown control of electronic equipment based on Feiteng and delayed shutdown control of other types of electronic equipment.

Drawings

Other features, objects and advantages of the present invention will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings.

Fig. 1 is a flowchart of a shutdown control method of an electronic device according to an embodiment of the present invention;

FIG. 2 is a block diagram of a shutdown control system of an electronic device according to an embodiment of the invention;

FIG. 3 is a block diagram of an implementation of a shutdown control system of an electronic device according to an embodiment of the invention;

FIG. 4 is a block diagram of an FPGA of an embodiment of the present invention;

FIG. 5 is a timing diagram for LPC control for a programmable control logic device in accordance with one embodiment of the present invention;

FIG. 6 is a timing diagram of an FPGA of an embodiment of the present invention.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted.

As shown in fig. 1, in an embodiment, the present invention provides a shutdown control method for an electronic device, including the following steps:

s100: detecting a shutdown key signal of the electronic equipment;

s200: sending a shutdown request to a currently running application program;

s300: receiving a shutdown feedback signal returned by the application program;

s400: and determining whether to execute shutdown operation according to a shutdown feedback signal returned by the application program.

By adopting the electronic equipment shutdown control method of the invention, when the shutdown key signal of the electronic equipment is detected in the step S100, the shutdown operation is not immediately executed, but the shutdown request is firstly sent to the application program in the step S200, the shutdown feedback signal is received in the step S300, and whether the shutdown operation can be executed or not is determined in the step S400, so that the delayed shutdown when the shutdown key of the electronic equipment is pressed is realized, and the problem of data loss when abnormal shutdown is caused by misoperation of personnel or forced shutdown by using a power key is solved.

As shown in fig. 2, an embodiment of the present invention further provides an electronic device shutdown control system, which is applied to the electronic device shutdown control method, where the control system includes:

a shutdown detection module M100, configured to detect a shutdown key signal;

the application interaction module M200 is configured to send a shutdown request to a currently running application program, receive a shutdown feedback signal returned by the application program, and determine whether to execute a shutdown operation according to the shutdown feedback signal returned by the application program.

By adopting the electronic equipment shutdown control method of the invention, when the shutdown detection module M100 detects the shutdown key signal of the electronic equipment, the shutdown operation is not immediately executed, but the application interaction module M200 firstly sends the shutdown request to the application program and receives the shutdown feedback signal to determine whether the shutdown operation can be executed, so that the delayed shutdown when the shutdown key of the electronic equipment is pressed is realized, and the problem of data loss when abnormal shutdown is caused by misoperation of personnel or forced shutdown by using a power key is solved.

The following describes the technical solution of the present invention by taking an example of a shutdown control method of a soar electronic device. It is to be understood that the present invention is not limited thereto, and the shutdown control method and system of the electronic device of the present invention can be applied to the delayed shutdown control of the electronic device based on the soar environment, and can also be applied to the delayed shutdown control of other types of electronic devices.

As shown in fig. 3, in this embodiment, the shutdown detection module M100 is implemented by using a programmable logic device, and the step S100 of detecting the shutdown key signal of the electronic device includes that the programmable logic device detects the shutdown key signal of the electronic device. The Programmable logic device may be a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA), and all of them fall within the protection scope of the present invention. The programmable logic device directly monitors the switch signal of the on/off key of the electronic equipment to realize the detection of the off key signal of the electronic equipment. Specifically, if a power-on key and a power-off key are used, the programmable logic device detects a power-off key signal when the power-off key is pressed. If one key is used for power-on and power-off control, the electronic equipment is in a power-off state and detects that the key is pressed down. The programmable logic device detects a power-on key signal, and when the electronic equipment is in a power-on state and detects that the key is pressed down, the programmable logic device detects a power-off key signal.

In other alternative embodiments, other design circuits may be used to implement the function of the shutdown detection module M100, for example, a key signal detection unit is used to detect a shutdown switch signal of the power on/off key, and the key signal detection unit is further connected to a main control chip communication unit, and is configured to generate a shutdown signal after detecting the shutdown switch signal and send the shutdown signal to the main control chip.

As shown in fig. 3, in this embodiment, the electronic device shutdown control system further includes a main control chip, where the main control chip may communicate with the programmable control logic device and receive a shutdown signal from the programmable control logic device. In this embodiment, the step S100: after the shutdown key signal of the electronic equipment is detected, the method further comprises the following steps:

As shown in fig. 3, the application interaction module M200 is implemented by using a driver of the electronic device, and the step S200 of sending the shutdown request to the currently running application program includes the following steps:

and the driver detects that the level of the first shutdown indication pin is a level indicating hardware shutdown, generates shutdown requests facing each currently running application program, and sends the generated shutdown requests to the currently running application program.

In this embodiment, when the first power-off indication pin is at a high level, it indicates that there is no hardware power-off signal, and when the first power-off indication pin is at a low level, it indicates that there is a hardware power-off signal. Therefore, the main control chip sets the level of the first shutdown indication pin as the level indicating hardware shutdown, that is, the main control chip pulls down the level of the first shutdown indication pin.

Fig. 4 is a block diagram of a structure of the programmable logic device in this embodiment, and here, the programmable logic device is a Gowin FPGA, and the main control chip is an FT1500A chip. The programmable logic device comprises the following units:

the watchdog control unit is used for realizing the watchdog function in the FPGA;

the voltage conversion control unit is used for performing voltage conversion control on the interaction signals between the main control chip and each chip;

the FT1500A power-on control unit is used for controlling and managing the power-on time sequence of the main control chip;

the FT1500A power-off control unit is used for controlling and managing the power-off time sequence of the main control chip;

the power-off and soft reset control unit is used for controlling and managing the power-off and soft reset of the main control chip;

the LPC _ LAD control unit is used for controlling and managing LAD (command, data, address multiplexing signal) of LPC (Low pin count bus);

the signal delay time-varying control unit is used for detecting a switch key signal;

and the signal generating unit is used for generating a starting signal or a shutdown signal when detecting the switch key signal and reporting the starting signal or the shutdown signal to the main control chip.

When the programmable logic device is a CPLD, it may also adopt a functional module structure as shown in fig. 4.

The interfaces included in the FPGA are shown in tables 1 and 2 below:

table 1 FPGA interface list 1

Interface	I/O type	Function(s)
			FT_LPC	IO	Input-output signal voltage conversion at end FT1500A
LPC	IO	LPC end input and output signal voltage conversion
			LED	IO	Status indicator light signal
Other	IO	Other input-output signals

Table 2 FPGA interface list 2

As shown in fig. 5, it is an LPC control timing chart of the programmable control logic device of this embodiment. Where i _ FT _ LPC _ clk is the input clock signal of the LPC of FT 1500A. i _ ft _ lpc _ lframe _ n is an input signal at the beginning of the operating cycle. i _ ft _ LPC _ LAD [3:0] is the input LAD control signal of LPC. o _ LPC _ clk is the output clock signal of LPC. o _ lpc _ lfame _ n is an output signal at the start of the operation cycle. o _ ft _ LPC _ LAD [3:0] is the output LAD control signal of LPC. start indicates the start or end of the transmission. ADD0, ADD1, ADD2, ADD3, and ADD3_ N indicate address information.

The power-up (power-off) and reset (restart) request paths of the programmable control logic device employing the present invention are shown in table 3 below. The response control of the power-up and power-down and reset requests is shown in table 4 below. The on/off key is used as shown in table 5 below. The reset key is used as shown in table 6 below.

TABLE 3 startup and shutdown and reset request Path Table

The GPIO _ C0, GPIO _ B5, and GPIO _ B6 correspond to different indication pins of the CPU, and are described in detail below.

Table 4 power-up and power-down and reset request response control table

Watch 5 on-off key using watch

The FPGA needs system reset. After the FPGA program is loaded, the FPGA is reset and then the normal working flow is started. The reset time is required to be at least 20ns or more.

Table 6 reset key usage table

The control timing signals of the FPGA when performing power-on control on the main control chip can be seen in fig. 6. The values of T1 to T10 in fig. 6 are default values or preset values.

When the programmable logic device is an FPGA, the electrifying sequence is as follows:

the shutdown state PWRBIN is pressed- > waits for PWRBIN release- > ATX _ EN- > delays 1ms- >3V3S _ EN- > ATX _ PWRGD pull high- > starts the peripheral and hard disk power-up (wherein AST2510_ VCC _ PG delays 3ms power-up compared with other peripherals, the hard disk group power-up interval is 10s) - > delays 20ms- > P1V8_ EN- > P1V8_ PWRGD pull high-back delay 20ms- > VDD _ CORE _ EN- > VDD _ CORE _ PG pull high-back delay 10ms- > VDDA _ PCIE _ EN- > VDDA _ PCIE _ PG pull high- > VDD _ MCU _ EN- > VDD _ PG pull high-back-P0V 75_ DDR01_ pull high/P0V 75_ DDR23_ DDR pull high/FT _ N _ pull low- > FT _ N _ pull high- > FT 40- > PCIE _ PG pull high-pull high-up delay completes the hard disk power-up delay 120ms- > PCIE _ PT _ OT- > pull high-up.

The system comprises an ATX mainboard power supply, a power switch control signal, an ATX _ EN, a mainboard switch signal, an ATX _ PWRGD, an AST2510_ VCC _ PG, a 1.8V power switch signal, a CORE switch signal, a VDD _ CORE _ PG, a CORE power switch signal, a VDD _ MCU _ EN, a MCU power switch signal, a VDD _ MCU _ PG, a DDR _ 75_ 01_ EN, a switch signal of a DDR01 port of an FPGA, a P0V75_ DDR23_ EN, a power on reset signal of the mainboard, and a PCIE _ SLOT _ RST _ N.

When the programmable logic device is an FPGA, the power-off sequence is as follows:

PCIE _ SLOT _ RST _ N is pulled down- > delayed by 2ms- > P0V75_ DDR01_ EN is pulled down- > delayed by 2ms- > VDD _ MCU _ EN is pulled down- > delayed by 2ms- > VDDA _ PCIE _ EN is pulled down- > delayed by 2ms- > VDD _ CORE _ EN is pulled down- > delayed by 2ms- > P1V8_ EN is pulled down- > delayed by 2ms- > peripheral and hard disk power down- > delayed by 2ms- >3V3S _ EN is pulled down- > delayed by 2ms- > ATX _ EN is pulled up- > waits for 4S and PWRBIN is released- > power down is completed.

In this embodiment, the shutdown feedback signals returned by the application program include a shutdown enable signal and a shutdown not enable signal. The application program is a business application running in the electronic device, such as a WeChat, a network disk, office software, and the like. When the application program receives a shutdown request sent by the driver program, whether the shutdown can be performed currently is judged, if the data loss cannot be caused by the current shutdown, the application program can directly return a shutdown permission signal to the driver program, if the data loss may be caused by the current shutdown, the application program firstly returns a shutdown non-permission signal to the driver program and executes data storage operation, and after the data storage operation is completed, the shutdown permission signal can be sent to the driver program.

The step S400: determining whether to execute a shutdown operation according to a shutdown feedback signal returned by the application program, wherein the method comprises the following steps:

if the driver receives a shutdown forbidding signal returned by at least one application program, the shutdown forbidding of the at least one application program is indicated, and the shutdown operation is determined not to be executed;

and if the driver receives the shutdown permission operation returned by all the application programs, indicating that all the application programs are permitted to be shut down, and determining to execute the shutdown operation.

In this embodiment, the electronic device shutdown control system further includes a shutdown execution module, and after determining to execute the shutdown operation, the shutdown execution module further executes the shutdown operation. In this embodiment, the shutdown execution module is implemented by the main control chip, and the executing of the shutdown operation includes the following steps:

In this embodiment, the main control chip is a main control chip of the electronic device, the programmable logic device receives a signal of the power on/off key, and when the signal of the power on/off key is detected, may send a power on signal or a power off signal to the main control chip, and the driver is a program running on the electronic device and serves as a bridge for controlling hardware by the application program. The first power-off indication pin and the second power-off indication pin are both pins of the main control chip. When the main control chip receives a shutdown signal of the programmable logic device, the level of the first shutdown indication pin may be set to a level indicating hardware shutdown, so that a driver may read the level of the first shutdown indication pin and confirm whether shutdown is allowed or not to an application program. When the shutdown is confirmed, the driver can set the level of the second shutdown indication pin to be the level indicating the software shutdown through the register. The main control chip can determine that the shutdown operation can be executed by reading the level of the second shutdown indication pin, and cut off the power supply of the power supply system.

In this embodiment, the first power-off indication pin is a General-purpose input/output (GPIO) pin of the main control chip, which is configured in an input mode, and the second power-off indication pin is a GPIO pin of the main control chip, which is configured in an output mode.

Specifically, the first shutdown indication pin is realized by multiplexing a GPIO pin of the main control chip, and the second shutdown indication pin is a GPIO pin of the main control chip that indicates a software shutdown signal, so that multiplexing does not need to be modified.

Here, the main control chip is FT1500A which is a FT, for example, to be specifically described. The first shutdown indication pin may be multiplexed into GPIO mode according to register specifications using a GPIO _ C [0] pin. In other alternative embodiments, other idle GPIO pins may be selected for multiplexing the indication function of implementing the first shutdown indication pin. The second power-off indication pin may use a GPIO _ B [6:5] pin to interact with the programmable logic device, and after the driver is started, the GPIO _ B [6:5] pin is set to {1,1 }. When the programmable logic device is powered off and restarted by software, the value of GPIO _ B [6:5] is set according to the following table 7. Specifically, the driver may use mmap (a method of mapping a file or other object into the memory) to map the physical address of the GPIO into the virtual memory, and then operate the corresponding register bit to implement data writing to the GPIO _ B [6:5] pin.

TABLE 7 GPIO _ B [6:5] truth table

Because GPIO _ B [6:5] belongs to the multiplexing pin, random signals are output in the starting process, the programmable logic device reads the value of GPIO _ B [6:5] after being electrified for 5 seconds.

Before the electronic equipment power-off control method is applied, the first power-off indication pin and the second power-off indication pin are configured. Specifically, a GPIOB _ DDR register and a GPIOC _ DDR register inside the GPIO are configured, a GPIO _ B [5] pin and a GPIO _ B [6] pin are configured to be in an output mode, a GPIO _ C [0] pin is configured to be in an input mode, and meanwhile, a GPIOV _ DR register is configured to configure the GPIO _ B [5] pin and the GPIO _ B [6] pin to be in high-level output. When the GPIO _ C [0] is configured to be in an input mode, the driving program needs to read input data from a corresponding GPIO _ EXT _ PORTX register, wherein the GPIO _ EXT _ PORTX register is an input data register corresponding to the GPIO _ C [0], and data is written into the input data register by the main control chip. Therefore, the master control chip controls the level of GPIO _ C [0] to be high or low by controlling the data in the GPIO _ EXT _ PORTX register. The invention controls the level of GPIO _ C0 pin through the main control chip, to realize the control function of delayed shutdown, to avoid the loss of application data when the shutdown key is pressed.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A shutdown control method for electronic equipment is characterized by comprising the following steps:

detecting a shutdown key signal of the electronic equipment;

sending a shutdown request to a currently running application program;

receiving a shutdown feedback signal returned by the application program;

2. The method according to claim 1, wherein the detecting the shutdown key signal comprises the programmable logic device detecting the shutdown key signal of the electronic device.

3. The method for controlling power-off of an electronic device according to claim 2, further comprising the following steps after detecting a power-off key signal of the electronic device:

4. The electronic device power-off control method according to claim 3, wherein the sending the power-off request to the currently running application program comprises the following steps:

5. The electronic device shutdown control method according to claim 4, wherein the shutdown feedback signal includes a shutdown permission signal and a shutdown non-permission signal, and determining whether to perform a shutdown operation according to the shutdown feedback signal includes:

6. The electronic device power-off control method according to claim 5, further comprising, after determining to perform a power-off operation, the steps of:

7. The electronic device power-off control method of claim 6, wherein the first power-off indication pin is a GPIO pin configured in an input mode, and the second power-off indication pin is a GPIO pin configured in an output mode.

8. The electronic device power-off control method of claim 4, wherein the first power-off indication pin is implemented by multiplexing a GPIO pin of the main control chip.

9. An electronic device power-off control system applied to the electronic device power-off control method according to any one of claims 1 to 8, the control system comprising:

the shutdown detection module is used for detecting a shutdown key signal;

10. The electronic device shutdown control system of claim 9, wherein the shutdown detection module is implemented by a programmable logic device, the control system further includes a main control chip, the programmable logic device generates a shutdown signal and sends the shutdown signal to the main control chip after detecting a shutdown key signal of the electronic device, and the main control chip sets a level of the first shutdown indication pin to a level indicating hardware shutdown.

11. The electronic device shutdown control system of claim 10, wherein the application interaction module is implemented by using a driver, and the driver is configured to send a shutdown request to a currently running application program when detecting that the level of the first shutdown indication pin is a level indicating hardware shutdown.

12. The electronic device shutdown control system of claim 11, wherein the driver is further configured to set, through a register, a level of a second shutdown indication pin of the main control chip to a level indicating software shutdown after confirming that a shutdown operation is performed;