CN112579002A - SRAM with transmission gate in bit line structure and access promotion method - Google Patents
SRAM with transmission gate in bit line structure and access promotion method Download PDFInfo
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Abstract
The invention provides an SRAM with a transmission gate in a bit line structure and an access improving method, wherein the SRAM comprises: a plurality of memory cells forming a memory array; each memory cell includes a peripheral driver circuit, a word line WL, a latch, and a bit line; the bit lines include bit line BL and bit line
A bidirectional transmission gate is inserted at a preset position of a bit line, the bit line is divided into two sections by taking the bidirectional transmission gate as a node, so that the bit line parasitic RC close to one side of a sense amplifier is reduced, and the access speed is improved.
Description
Technical Field
The invention relates to the field of computer data storage, in particular to an SRAM with a transmission gate in a bit line structure and an access promotion method.
Background
Static Random Access Memory (SRAM) is widely used in modern digital systems such as CPUs, and is mainly used as a secondary cache to coordinate the operating speeds of CPUs and memories. With the progress of semiconductor technology, the operating frequency of MOSFETs has been greatly increased, and the switching speed of gates (standard cells) formed of MOSFETs and the operating speed of CPU operating units formed of basic standard cells have also been greatly increased. However, the access speed of SRAM is not increased in the same proportion as that of gate circuits due to the special access structure of SRAM as a cache and the requirement of CPU for SRAM storage capacity, so the overall operation speed of CPU is limited. SRAM has become a limiting factor for realizing high-speed CPU, and in the design synthesis from RTL to gate-level netlist, the access time of SRAM is often long and cannot meet the timing requirement, so that the waiting time of clock has to be increased, and the speed of digital operation system is reduced. High speed CPUs require high speed SRAMs as support.
A typical SRAM 6-transistor memory cell is shown in FIG. 1, and an NRow x 1Column memory array composed of memory cells is shown in FIG. 2.
The working principle of the SRAM is as follows:
data writing: the SRAM peripheral driver circuit drives the bit line BL to a high potential "1",
to the low potential "0", the word line WL goes high to turn on the pass transistors M5 and M6,
will be provided with
Pulling to low level and storing '1' into Q node through latch formed by M1-M4; similarly, if BL is driven to low level "0", then "0" will be stored in node Q
Data reading: BL and
precharged to high, the word line WL goes high turning pass transistors M5 and M6 on. If "1" is stored "
The conducted M5 and M1 are pulled to the ground potential, BL is not changed because the sum Q is basically equal to the potential, and the voltage difference formed by the two bit lines
The output is amplified by a peripheral sense amplifier, and the stored '1' is read out; similarly, if "0" (Q ═ 0 ") is stored,
negative, the sense amplifier output is "0".
It can be seen from the above SRAM read-write principle that whether it is a write operation or a read operation, it is mainly realized by changing the potential value of the bit line: the bit line potential is pulled down by the peripheral driver, so as to further store the node Q or
The potential is pulled down to change the state of a latch consisting of M1-M4, so that the writing operation is realized; the bit line potential is pulled down through a pull-down NMOS tube M1 or M3 at the side of storing the '0' level to form a bit line potential difference delta V, and then the output is detected by a sense amplifier to realize the read operation. No matter read-write operation, the process of charging or discharging the bit line exists, and the parasitic resistance and capacitance of the metal layer of the bit line and the drain parasitic capacitance of the transmission tubes M5 and M6 connected with the metal layer of the bit line all have influence on the bit line charging and discharging speed, and further influence the read-write speed of the SRAM. Such as the memory cell parasitic resistance capacitance shown in fig. 3.
Fig. 4 shows an Nrow x 1column SRAM array with parasitic RC on the bit lines. The length of the bit line depends on the size of the row address, for example, a 1Mbit SRAM, and when the physical area occupied by the row decoding, Column decoding and block decoding is balanced to make the physical aspect ratio of the whole SRAM close to 1, the allocated row address is 10 bits, which means that one Column (1Column) has 1024 memory cells, the bit line length is 1024 × the cell height, and the bit line parasitic RC simplified circuit is shown in fig. 5
At the beginning of a read operation, the precharge MOSFET M0 is turned off, the static charge stored on the bit line is discharged to ground through the M1 or M3 transistor of the selected memory cell, and a pair of bit lines form a Δ V output to the input of the sense amplifier. The memory cell Row1023 farthest from the sense amplifier takes the longest discharge time and the longest sensing time because of the largest bit line parasitic RC. The read time of the SRAM depends on the read time of Row 1023.
Disclosure of Invention
In order to solve the above technical problems, the present invention adopts an SRAM with a transmission gate in a bit line structure and an access boosting method, wherein the bit line structure with the transmission gate enables the access speed of 1/2 memory cells (or other ratios, depending on the requirements) in the SRAM to be increased by nearly one time through an external gating control signal compared with the SRAM with the same process and the conventional design structure. In an SRAM, the high-speed memory cells addressed by partial addresses are used for meeting the occasion with limit requirement on the SRAM speed, and simultaneously the cost of abandoning the chip area of the rest low-speed memory cells is taken as the cost; when the high-speed access mode is not needed, the gating signal can be deselected to enable the SRAM to recover a normal access state.
The technical scheme of the invention is as follows: an SRAM provided with a transmission gate control unit in a bit line structure, the SRAM comprising:
a plurality of memory cells forming a memory array;
each memory cell includes a peripheral driver circuit, a word line WL, a latch, and a bit line;
the bit lines include bit line BL and bit line
The bit line is divided into two sections by taking the bidirectional transmission gate as a node, so that the parasitic RC of the bit line close to one side of the sense amplifier is reduced, and the access speed is improved; wherein the portions adjacent to the sense amplifier and the data write driver: because the parasitic RC of the bit line is reduced, the access speed of the corresponding unit is accelerated, and the unit is defined as a high-speed access unit; a portion remote from the sense amplifier and the data write driver, or a portion adjacent to the high-speed access portion is a normal-speed access portion;
a fuse wire parallel structure is added at two ends of the bidirectional transmission gate, and the fuse wire short-circuits the transmission gate when the SRAM acceleration mode is not needed; when the SRAM acceleration mode is started, the fuse wire is fused, and the transmission gate is started.
Furthermore, the size of the high-speed access area is divided by a row address section, the high-speed access area corresponds to a low-order row address section, and the normal access speed part corresponds to a high-order row address; for an M-bit row address (A)M-1～A0) If A is the memory array ofM-1The high-speed access part is gated at 0, and the corresponding decoding address of the rest row is AM-2～A0The high-speed area is 1/2 of the whole SRAM, the bidirectional transmission gate is inserted into the word decoding address of WL 2M-1-1 and 2M-1On the bit line in between; if AM-1AM-2The high-speed access part is gated at 00, and the corresponding residual row decoding address is AM-3～A0The high-speed region occupies 1/4 of the whole SRAM, and the bidirectional transmission gate is inserted into the word decoding address with WL 2M-2-1 and 2M-2On the bit line in between.
Furthermore, the transmission gate is composed of a pair of PMOS and NMOS, and the potentials of two sides of the bit line are ensured to be equal when the transmission gate is conducted.
Furthermore, the opening and closing of the transmission gate is controlled by an external access speed selection signal HS _ Strobe, when the HS _ Strobe is in a high level, the transmission gate is closed, and the high-speed mode is opened; HS _ Strobe is low, the transmission gate is on, and the high-speed mode is off.
Further, when HS _ Strobe is active, i.e., equal to "1", the opening and closing of the transfer gates is controlled by the SRAM external write enable WE and read enable RE signals; when the write enable or the read enable is valid, the transfer gate is closed; when the write enable and the read enable are both invalid, the transmission gate is conducted; the write enable and read enable cannot be active simultaneously.
Furthermore, a fuse parallel structure is added at two ends of the transmission gate, and the fuse short-circuits the transmission gate when the SRAM acceleration mode is not needed; when the SRAM acceleration mode is started, the fuse wire is fused, and the transmission gate is started.
According to the inventionIn another aspect of the present invention, a method for improving access of an SRAM by providing a transmission gate control unit in a bit line structure is provided, where the SRAM includes a plurality of memory cells, forming a memory array; each memory cell includes a peripheral driver circuit, a word line WL, a latch, and a bit line; the bit lines include bit line BL and bit line
The method comprises the following steps:
inserting a bidirectional transmission gate at a preset position of a bit line, and cutting the bit line into two sections by taking the bidirectional transmission gate as a node;
the bit line is divided into two sections by taking the bidirectional transmission gate as a node, so that the parasitic RC of the bit line close to one side of the sense amplifier is reduced, and the access speed is improved; wherein the portions adjacent to the sense amplifier and the data write driver: because the parasitic RC of the bit line is reduced, the access speed of the corresponding unit is accelerated, and the unit is defined as a high-speed access unit; a portion remote from the sense amplifier and the data write driver, or a portion adjacent to the high-speed access portion is a normal-speed access portion;
a fuse wire parallel structure is added at two ends of the bidirectional transmission gate, and the fuse wire short-circuits the transmission gate when the SRAM acceleration mode is not needed; when the SRAM acceleration mode is started, the fuse wire is fused, and the transmission gate is started.
Furthermore, the opening and closing of the transmission gate is controlled by an external access speed selection signal HS _ Strobe, when the HS _ Strobe is in a high level, the transmission gate is closed, and the high-speed mode is opened; HS _ Strobe is low, the transmission gate is on, and the high-speed mode is off.
Further, when HS _ Strobe is active, i.e., equal to "1", the opening and closing of the transfer gates is controlled by the SRAM external write enable WE and read enable RE signals;
when the write enable or the read enable is valid, the transfer gate is closed; when the write enable and the read enable are both invalid, the transmission gate is conducted; the write enable and read enable cannot be active simultaneously.
Has the advantages that:
on the premise of basically not changing the original SRAM structure (bitcell, decoding, row and column arrangement, sense amplifier and the like), the invention blocks the parasitic RC on the bit line by inserting a transmission gate (switch) at a proper position on the bit line, thereby improving the access speed. For any speed SRAM with definite row-column structure, the access speed can still be improved by nearly 50% (1/2 bit line length) or nearly 75% (1/4 bit line length) by adopting the method, and the cost of abandoning the use of partial memory cells is avoided. The invention provides an acceleration/conventional mode option, and is greatly convenient for selecting a proper SRAM in the occasions with extreme requirements on the SRAM access speed (such as the SRAM is a time sequence bottleneck).
Drawings
FIG. 1: conventional SRAM6 tube cells;
FIG. 2: n rows and 1 columns of SRAM;
FIG. 3: SRAM cell parasitic resistance capacitance;
FIG. 4: an SRAM array with a parasitic RC on a bit line;
FIG. 5: a bitline parasitic RC simplified circuit;
FIG. 6: a transmission gate schematic;
FIG. 7: bit line insertion pass gate schematic;
FIG. 8: the transmission gate inserts 1/2 column length position schematic;
FIG. 9: high speed memory mode transmission gate control schematic;
FIG. 10: a transmission gate fuse schematic diagram;
fig. 11 (a): a discharge test schematic diagram of a conventional bit line structure;
fig. 11 (b): a test schematic diagram of a special bit line structure inserted into a transmission gate;
fig. 12 (a): bit line discharge simulation waveforms of the two bit line structures;
fig. 12 (b): bit line discharge simulation waveforms of two bit line structures.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person skilled in the art based on the embodiments of the present invention belong to the protection scope of the present invention without creative efforts.
The invention provides an SRAM with a transmission gate control unit in a bit line structure, which can improve the access speed of the SRAM by controlling the opening and closing of a transmission gate, and comprises:
a plurality of memory cells forming a memory array;
each memory cell includes a peripheral driver circuit, a word line WL, a latch, and a bit line;
the bit lines include bit line BL and bit line
The method comprises the following steps that a bidirectional transmission gate is inserted into a preset position of a bit line, the bidirectional transmission gate is used as a node, and the bit line is divided into two sections, so that the lengths of the two sections of bit lines and parasitic RC are greatly reduced;
the SRAM also comprises a read amplifier and a data write driver which are connected with the storage unit in the SRAM;
furthermore, the part close to the sense amplifier and the data write driver (the time for the memory cell close to the sense amplifier to discharge the potential of the bit line at the input end of the amplifier to delta V is shorter than the discharge time required by the memory cell at the second, third and subsequent positions, so the reading speed is the fastest; the bit line is divided into an upper part and a lower part by the transmission gate, the reading speed of the memory cell part close to the sense amplifier is generally faster than that of the memory cell part above; the portion remote from the sense amplifiers and data write drivers, or the portion adjacent to the high speed access (fig. 8) is the normal speed access portion; the specific implementation method comprises the following steps:
inserting a bidirectional transmission gate on the bit line, cutting the bit line into two sections, the bit line length and parasitic RC of the two sections are greatly reduced (fig. 7)
The part close to the read amplifier and the data write driver has reduced bit line parasitic RC, so that the corresponding unit has higher access speed and is defined as a high-speed access unit; normal speed access part adjacent to high speed access part (fig. 8)
The size of the high-speed access area may be divided by a row address section. The high-speed access area corresponds to a low-order row address section, and the normal access speed portion corresponds to a high-order row address. For an M-bit row address (A)M-1～A0) If A is the memory array ofM-1The high-speed access part is gated at 0, and the corresponding decoding address of the rest row is AM-2～A0The high-speed area is 1/2 of the whole SRAM, the bidirectional transmission gate is inserted into the word decoding address of WL 2M-1-1 and 2M-1On the bit line in between; if AM-1AM-2The high-speed access part is gated at 00, and the corresponding residual row decoding address is AM-3～A0The high-speed region occupies 1/4 of the whole SRAM, and the bidirectional transmission gate is inserted into the word decoding address with WL 2M-2-1 and 2M-2On the bit line in between. (FIG. 8)
The transmission gate is formed by a pair of PMOS and NMOS (figure 6), which ensures the potentials of both sides of the bit line are equal when the transmission gate is conducted. The input and output ports A and B of the transmission gate are respectively connected with the bit line of the cut-off memory array, and the gates of the PMOS and NMOS are connected with the on/off logic control circuit of the transmission gate. The substrates of the PMOS and the NMOS are respectively connected with VDD and GND to form a source (source) and drain (drain) interchange structure so as to ensure the bidirectional transmission of charges/potentials when the transmission gate is opened.
The opening and closing of the transmission gate is controlled by an external access speed selection signal HS _ Strobe, when the HS _ Strobe is in a high level and a read-write operation is performed (RE or WE is '1'), the transmission gate is closed, and a high-speed mode is opened; HS _ Strobe is low, the transmission gate is on, and the high speed mode is off (FIG. 9).
When HS _ Strobe is active (═ 1 "), the transmission gate is turned on and off by the SRAM external write enable WE and read enable RE signals. When the write enable or the read enable is valid, the transfer gate is closed; when the write enable and the read enable are both invalid, the transmission gate is conducted; write enable and read enable cannot be active simultaneously (FIG. 9)
The transmission gate input control truth table is shown in table 1.
TABLE 1 truth table for transmission gate control in high speed access mode
| HS_Strobe | WE | RE | OUT |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
When the SRAM acceleration mode is not needed, HS _ Strobe is set to be low level, the transmission gate is conducted, and the SRAM enters the constant speed mode. The source-drain parasitic capacitance of the transfer gate itself and the channel on-resistance Rdson will increase the total parasitic RC on the bit line, resulting in a slow access speed. Therefore, the SRAM with the bit line transmission gate structure is suitable for an application scene with low requirement on access speed when the SRAM works in a constant speed mode.
When the transmission gate is closed, the SRAM enters an accelerated access mode. The source or drain capacitances of the NMOS and PMOS in the transfer gate will increase the bit line parasitic RC of the high speed access memory cell portion, the source drain capacitance becoming larger as the channel width (W) of the NMOS and PMOS increases. Therefore, the size of the transmission gate should be selected as small as possible without affecting the bit line precharging speed (the transmission gate is turned on during bit line precharging, and the bit line parasitic RC is increased), so as to reduce the contribution of the bit line parasitic RC to the high-speed access unit part.
A fuse parallel structure is added at two ends of the transmission gate, and when an SRAM acceleration mode is not needed, the fuse short-circuits the transmission gate, which is the same as a conventional SRAM structure without the transmission gate on a bit line; when the SRAM acceleration mode is enabled, the fuse is blown and the transmission gate is enabled (FIG. 10).
Concept verification
To verify the effect of the special bit line structure adopted by the present invention on the SRAM access speed, the test circuit shown in FIG. 11 was designed
FIG. 11(a) is a schematic diagram of a discharge test of a conventional bit line structure. The 511 th row of cells performs a read operation, the WL511 word line is selected, the bit line is discharged through the NMOS transistor (M1, M5 or M3, M6), the voltage at the input Vin-of the sense AMP is monitored, and the time T0 required for the voltage to drop 200mV is measured. The memory content is read when 200mV assumes the input threshold voltage of the sense amplifier, i.e., the difference in bit line voltages reaches 200 mV.
FIG. 11(b) is a schematic diagram of a discharge test of a special bit line structure. The transfer gates in row 511 are closed, the cells in row 511 perform a read operation, WL511The word line is selected, the bit line is discharged through the NMOS transistor (M1, M5 or M3, M6), and the input end V of the sense AMP is monitoredin-The time T1 required for the voltage to drop by 200mV was measured. Δ T-T0-T1 represents the bit line discharge time difference between the two bit line structures when reading the same memory cell, which is equivalent to the sensing time difference
As can be seen from the simulation result in fig. 12, the time required for the bit line voltage of the special bit line structure to drop by 200mV is T1-0.31 ns, while the time required for the conventional bit line structure to drop by T0-0.57 ns, the time Δ T0-T1 is shortened by nearly 50%, and the sensing speed is increased by nearly 50%.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but various changes may be apparent to those skilled in the art, and it is intended that all inventive concepts utilizing the inventive concepts set forth herein be protected without departing from the spirit and scope of the present invention as defined and limited by the appended claims.
Claims (10)
1. An SRAM provided with a transmission gate control unit in a bit line structure, the SRAM comprising:
a plurality of memory cells forming a memory array; each memory cell comprises a peripheral driving circuit, a word line WL, a latch and a bit line; the bit lines include bit line BL and bit line
The method is characterized in that:
the method comprises the following steps that a bidirectional transmission gate is inserted into a preset position of a bit line, fuse wires are added to two ends of the bidirectional transmission gate in a parallel connection structure, and the fuse wires short-circuit the transmission gate when an SRAM acceleration mode is not needed; when the SRAM acceleration mode is started, the fuse wire is fused, and the bidirectional transmission gate is started;
the bidirectional transmission gate is used as a node, and the bit line is divided into two sections, so that the parasitic RC of the bit line close to one side of the sense amplifier is reduced, and the access speed is improved; wherein the portions adjacent to the sense amplifier and the data write driver: because the parasitic RC of the bit line is reduced, the access speed of the corresponding unit is accelerated, and the unit is defined as a high-speed access unit; a portion remote from the sense amplifier and the data write driver, or a portion adjacent to the high-speed access portion is a normal-speed access portion;
the size of the high-speed access area is divided by a row address section, the high-speed access area corresponds to a low-order row address section, and the normal access speed part corresponds to a high-order row address; for an M-bit row address (A)M-1～A0) If A is the memory array ofM-1The high-speed access part is gated at 0, and the corresponding decoding address of the rest row is AM-2～A0The high-speed area is 1/2 of the whole SRAM, the bidirectional transmission gate is inserted into the word decoding address of WL 2M-1-1 and 2M-1On the bit line in between; if AM-1AM-2The high-speed access part is gated at 00, and the corresponding residual row decoding address is AM-3～A0The high-speed region occupies 1/4 of the whole SRAM, and the bidirectional transmission gate is inserted into the word decoding address with WL 2M-2-1 and 2M-2On the bit line in between.
2. The SRAM having a transmission gate control unit provided in a bit line structure according to claim 1, wherein:
the SRAM further comprises a sense amplifier and a data write driver connected to the memory cells in the SRAM.
3. The SRAM having a transmission gate control unit provided in a bit line structure according to claim 1, wherein:
the bidirectional transmission gate is composed of a pair of PMOS and NMOS, and the potentials of two sides of the bit line are ensured to be equal when the bidirectional transmission gate is conducted.
4. The SRAM having a transmission gate control unit provided in a bit line structure according to claim 1, wherein:
the input and output ports of the transmission gate are respectively connected with the bit lines of the cut-off memory array, and the gates of the PMOS and NMOS are connected with the on/off logic control circuit of the transmission gate; the substrates of the PMOS and the NMOS are respectively connected with VDD and GND to form a source-drain interchange structure so as to ensure the bidirectional transmission of charges/potentials when the transmission gate is opened.
5. The SRAM having a transmission gate control unit provided in a bit line structure according to claim 1, wherein:
the opening and closing of the bidirectional transmission gate is controlled by an external access speed selection signal HS _ Strobe, when the HS _ Strobe is in a high level, the bidirectional transmission gate is closed, and a high-speed mode is opened; HS _ Strobe is low, the bidirectional transmission gate is on, and the high-speed mode is off.
6. The SRAM having a transmission gate control unit provided in a bit line structure as claimed in claim 5, wherein:
when HS _ Strobe is active, i.e., equal to "1", the opening and closing of the bidirectional transmission gate is controlled by the SRAM external write enable WE and read enable RE signals; when the write enable or the read enable is valid, the bidirectional transmission door is closed; when the write enable and the read enable are both invalid, the bidirectional transmission gate is conducted.
7. The SRAM having a transmission gate control unit provided in a bit line structure as claimed in claim 6, wherein: the write enable and read enable cannot be active simultaneously.
8. Control unit for transmission door by arranging transmission door in bit line structureThe method for improving SRAM access includes forming memory array with several memory units; each memory cell includes a peripheral driver circuit, a word line WL, a latch, and a bit line; the bit lines include bit line BL and bit line
The method is characterized by comprising the following steps:
inserting a bidirectional transmission gate at a preset position of a bit line, and cutting the bit line into two sections by taking the bidirectional transmission gate as a node; the parasitic RC of the bit line close to one side of the sense amplifier is reduced, and the access speed is improved; wherein the portions adjacent to the sense amplifier and the data write driver: because the parasitic RC of the bit line is reduced, the access speed of the corresponding unit is accelerated, and the unit is defined as a high-speed access unit; a portion remote from the sense amplifier and the data write driver, or a portion adjacent to the high-speed access portion is a normal-speed access portion;
a fuse wire parallel structure is added at two ends of the bidirectional transmission gate, and the fuse wire short-circuits the transmission gate when the SRAM acceleration mode is not needed; when the SRAM acceleration mode is started, the fuse wire is fused, and the bidirectional transmission gate is started;
the opening and closing of the bidirectional transmission gate is controlled by an external access speed selection signal HS _ Strobe, when the HS _ Strobe is in a high level, the bidirectional transmission gate is closed, and a high-speed mode is opened; HS _ Strobe is low level, the bidirectional transmission gate is conducted, and the high-speed mode is closed;
the size of the high-speed access area is divided by a row address section, the high-speed access area corresponds to a low-order row address section, and the normal access speed part corresponds to a high-order row address; for an M-bit row address (A)M-1～A0) If A is the memory array ofM-1The high-speed access part is gated at 0, and the corresponding decoding address of the rest row is AM-2～A0The high-speed area is 1/2 of the whole SRAM, the bidirectional transmission gate is inserted into the word decoding address of WL 2M-1-1 and 2M-1On the bit line in between; if AM-1AM-2The high-speed access part is gated at 00, and the corresponding residual row decoding address is AM-3～A0High speed region size integral1/4 of SRAM, bidirectional transmission gate is inserted to word decode address WL 2M-2-1 and 2M-2On the bit line in between.
9. The method of claim 8, wherein the access of the SRAM is promoted by providing a transmission gate control unit in the bit line structure, further comprising:
when HS _ Strobe is active, i.e., equal to "1", the opening and closing of the bidirectional transmission gate is controlled by the SRAM external write enable WE and read enable RE signals.
10. The method of claim 8, wherein the access of the SRAM is promoted by providing a transmission gate control unit in the bit line structure, further comprising:
when the write enable or the read enable is valid, the bidirectional transmission door is closed; when the write enable and the read enable are both invalid, the bidirectional transmission gate is conducted; the write enable and read enable cannot be active simultaneously.
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