CN112567351B

CN112567351B - Method, device and system for controlling prefetching data from dynamic random access memory

Info

Publication number: CN112567351B
Application number: CN201880096481.7A
Authority: CN
Inventors: 夏晶; 信恒超; 涂珍喜; 闵文斌
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2024-04-09
Anticipated expiration: 2038-11-15
Also published as: WO2020097868A1; CN112567351A

Abstract

A method, apparatus and system for controlling prefetching data from a dynamic random access memory, the method comprising the steps of obtaining at least one refresh indication signal (S1) of said DRAM by a last level cache LLC; the LLC generating at least one control signal (S2) from the at least one refresh indication signal; the LLC controls prefetching data from the DRAM according to the at least one control signal (S3). The last level cache LLC of the method realizes the combination of the DRAM and the LLC by acquiring at least one refresh indication signal of the DRAM and generating the control signal according to the refresh indication signal, and can control the operation of prefetching data from the DRAM based on the control signal, thereby solving the problem that the refresh has negative influence on the efficiency of the DRAM, particularly the problem that the refresh influence has superposition effect, and effectively improving the performance of the DRAM.

Description

Method, device and system for controlling prefetching data from dynamic random access memory

Technical Field

The present disclosure relates to communication technologies, and in particular, to a method, an apparatus, and a system for controlling prefetching data from a dynamic random access memory.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM for short) is very popular in the industry. DRAM may be used as the main memory of the system, also called memory. DRAM uses the charge in a capacitor to store data, but these charges are continuously lost with the existence of leakage. Therefore, the data in the capacitor must be periodically read and rewritten to compensate for the lost charge, an operation called Refresh.

The DRAM may generally include: single Data Rate (SDR), double Data Rate (DDR), high-Bandwidth Memory (HBM), etc.

For the CPU, the depth of the download/Store Queue is shallow, wherein the download refers to reading the data in the DRAM. Specifically, as shown in fig. 1, when the CPU 100 receives a memory access request sent by an external device, the CPU may perform read/write operations on data in the DRAM 200 through the memory controller (Memory Controller, MC) 101 according to the memory access request. Since the CPU design mechanism is usually the rule of orderly exiting the Retire in Order, that is, if a certain access request cannot exit (i.e., DDR returns data), all subsequent access requests cannot release the Queue even if completed. In combination with the DDR refresh operation, after the DDR refresh operation, the DDR cannot return data for a certain access request, so that a situation that no request can be processed for a period of time is likely to occur, and the DDR efficiency is greatly reduced.

From the above, it is clear that refresh has a negative impact on DRAM efficiency, and the more channels, the greater the impact of refresh on efficiency. In addition, in the scene of strong memory access continuity, the influence is more serious, because in the continuous address access, the access in a short time can be uniformly interwoven to all channels (in order to improve the bandwidth, the channel interweaving generally adopts address low-order interweaving), at the moment, as long as any channel in the system is in a refreshing state, the system can possibly generate a short cut-off phenomenon, so that in the multi-channel process, the influence of refreshing generates a superposition effect, and the efficiency of the DRAM is further reduced.

Disclosure of Invention

The application provides a method, a device and a system for controlling prefetching data from a dynamic random access memory, which are used for solving the problem that refreshing has a negative effect on DRAM efficiency in the prior art, and particularly, the effect of refreshing has a superposition effect in the multi-channel process.

In a first aspect, the present application provides a method for controlling prefetching data from a dynamic random access memory DRAM, comprising:

the LLC of the last level acquires at least one refresh indication signal of the DRAM;

the LLC generates at least one control signal according to the at least one refresh indication signal;

the LLC controls prefetching of data from the DRAM according to the at least one control signal.

The last level cache LLC effectively realizes the combination of the DRAM and the LLC by acquiring at least one refresh indication signal of the DRAM and generating a control signal according to the refresh indication signal, and can control the operation of prefetching data from the DRAM based on the control signal, thereby effectively solving the problem that the refresh has negative influence on the DRAM efficiency, particularly the influence of the refresh has superposition effect during multiple channels, and effectively improving the performance of the DRAM.

In one possible design, the LLC generates at least one control signal from the at least one refresh indication signal, including:

The LLC performs a logical operation on the at least one refresh indication signal to generate the at least one control signal.

The LLC can generate at least one control signal by carrying out logic operation on at least one refresh indication signal, so that the stable reliability of control signal acquisition is effectively ensured.

In one possible design, the LLC logically operates on the at least one refresh-indication signal, including:

the LLC performs an or operation on the at least one refresh-indication signal, or,

the LLC ANDs the at least one refresh indication signal.

The LLC can adopt different implementation modes according to different use requirements and use scenes by carrying out OR operation or AND operation on the at least one refresh indication signal, so that the flexible reliability of carrying out logic operation on the refresh indication signal is effectively ensured, and the application range of the method is further improved.

the LLC acquires at least one refresh unit identifier, the at least one refresh unit identifier corresponds to the at least one refresh indication signal one by one, the refresh unit identifier is an identifier corresponding to a refresh unit in the DRAM, and the refresh unit performs one-time refresh on a storage space included in the DRAM;

Determining the at least one refresh indication signal as the at least one control signal corresponding to the at least one refresh unit identification.

The LLC acquires the refresh unit identifier corresponding to the refresh indication signal, and further determines the refresh indication signal as a control signal of the refresh unit corresponding to the refresh unit identifier, so that the refresh indication signal is directly used as the control signal without any processing, the accuracy of control signal acquisition is ensured, the acquired control signal has the best effect, and the stability and reliability of the method are further ensured.

In one possible design, the LLC controls prefetching data from the DRAM based on the at least one control signal, including:

the LLC acquires the current working state of the refreshing unit;

adjusting the preset prefetching capacity of the LLC according to the current working state and the at least one control signal;

and controlling prefetching data from the DRAM according to the adjusted prefetching capacity.

The LLC obtains the adjusted prefetching capacity by detecting the current working state of the refreshing unit in the DRAM and analyzing and processing the current working state and the control signal, so that the operation of prefetching data from the DRAM can be controlled according to the adjusted prefetching capacity, and the accuracy of the method is further improved.

In one possible design, the adjusting the pre-set prefetching capability of the LLC according to the current operating state and the at least one control signal includes:

if the current working state is a refreshing state, enhancing the prefetching capability according to the at least one control signal; or,

and if the current working state is a non-refreshing state, reducing the prefetching capability according to the at least one control signal.

After detecting the current working state of the refresh unit in the DRAM, different adjustment processes can be performed on the prefetching capability of the LLC according to different working states, specifically, the prefetching capability is enhanced during the refresh of the DRAM, and the prefetching capability is weakened during the non-refresh period, so that excessive prefetching can be prevented, and the refresh quality and efficiency of the DRAM are ensured.

In one possible design, the controlling prefetching data from the DRAM according to the adjusted prefetching capability includes:

determining a DRAM access request of the adjusted pre-fetch capability according to the adjusted pre-fetch capability;

prefetching data from the DRAM is controlled by the DRAM access request.

By determining the DRAM access request with the adjusted prefetching capability, the operation of prefetching data from the DRAM is further controlled according to the DRAM access request, so that the process of controlling the operation of prefetching data from the DRAM according to the adjusted prefetching capability is effectively realized, and the accuracy of the method is ensured.

In one possible design, the refresh unit includes at least one of the following refresh units:

CHANNEL, dual inline memory module DIMM, memory granule group RANK, or memory granule CHIP.

In a second aspect, the present application provides an apparatus for controlling prefetching data from a dynamic random access memory DRAM, comprising:

an acquisition module for acquiring at least one refresh indication signal of the DRAM;

a generating module for generating at least one control signal according to the at least one refresh indication signal;

and the control module is used for controlling the prefetching of data from the DRAM according to the at least one control signal.

The acquisition module acquires at least one refresh indication signal of the DRAM, the generation module generates a control signal according to the refresh indication signal, the combination of the DRAM and the LLC is effectively realized, and the operation of prefetching data from the DRAM can be controlled based on the control signal, so that the problem that the refresh has negative influence on the DRAM efficiency, especially in the multi-channel process, the influence of the refresh has superposition effect is effectively solved, and the performance of the DRAM is effectively improved.

In one possible design, the generating module is configured to:

And carrying out logic operation on the at least one refresh indication signal to generate the at least one control signal.

The generation module carries out logic operation on at least one refresh indication signal, so that at least one control signal can be generated, and the stable reliability of control signal acquisition is effectively ensured.

In one possible design, the generating module is configured to:

or the at least one refresh indication signal, or,

and performing AND operation on the at least one refresh indication signal.

The generation module performs OR operation or AND operation on the at least one refresh indication signal, different implementation modes can be adopted according to different use requirements and use situations, the flexibility and reliability of logic operation on the refresh indication signal are effectively ensured, and the application range of the device is further improved.

In one possible design, the generating module is configured to:

acquiring at least one refresh unit identifier, wherein the at least one refresh unit identifier corresponds to the at least one refresh indication signal one by one, the refresh unit identifier is an identifier corresponding to a refresh unit in the DRAM, and the refresh unit performs one-time refresh on a storage space included in the DRAM;

The generation module acquires the refresh unit identifier corresponding to the refresh indication signal, and further determines the refresh indication signal as the control signal of the refresh unit corresponding to the refresh unit identifier, so that the refresh indication signal can be directly used as the control signal without any processing, the accuracy of control signal acquisition is ensured, the acquired control signal has the best effect, and the use stability and reliability of the device are further ensured.

In one possible design, the control module is configured to:

acquiring the current working state of the refreshing unit;

adjusting the pre-fetching capability of the preset LLC according to the current working state and the at least one control signal;

The current working state of the refreshing unit in the DRAM is detected by the control module, the adjusted prefetching capacity is obtained by analyzing and processing the current working state and the control signal, and then the operation of prefetching data from the DRAM can be controlled according to the adjusted prefetching capacity, so that the accuracy of the device is further improved.

In one possible design, the control module is configured to:

After detecting the current working state of the refresh unit in the DRAM, the control module may perform different adjustment processing on the prefetching capability of the LLC according to different working states, specifically, enhance the prefetching capability during the refresh of the DRAM, and weaken the prefetching capability during the non-refresh period, so that excessive prefetching may be prevented, and the refresh quality and efficiency of the DRAM may be ensured.

In one possible design, the control module is configured to:

prefetching data from the DRAM is controlled by the DRAM access request.

The DRAM access request with the adjusted prefetching capacity is determined through the control module, the operation of prefetching data from the DRAM is further controlled according to the DRAM access request, the process of controlling the operation of prefetching data from the DRAM according to the adjusted prefetching capacity is effectively realized, and the accuracy degree of the device is ensured.

In a third aspect, the present application provides an apparatus for controlling prefetching data from a dynamic random access memory DRAM, comprising:

a memory;

a processor; and

a computer program;

wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method as described in the first aspect above.

In a fourth aspect, the present application provides a processor comprising:

the last level cache LLC is configured to:

acquiring at least one refresh indication signal of the DRAM;

generating at least one control signal according to the at least one refresh indication signal;

and controlling prefetching data from the DRAM according to the at least one control signal.

In one possible design, the processor further comprises:

and the memory controller is connected with the LLC and is used for realizing read-write operation of data in the DRAM connected with the processor.

In a fifth aspect, the present application provides an apparatus for controlling prefetching data from a dynamic random access memory DRAM, comprising:

The device comprises a processor, a memory, a communication interface and a bus, wherein the processor, the memory and the communication interface are communicated through the bus;

the memory is used for storing a computer program;

the communication interface is used for communicating with the DRAM;

the processor is configured to execute the program stored in the memory to perform the method as described in the first aspect above when the processing means is running.

In a sixth aspect, the present application provides a system for controlling prefetching data from a dynamic random access memory DRAM, comprising: at least one dynamic random access memory DRAM, and means for controlling prefetching data from the dynamic random access memory DRAM as described in the second aspect, the means for controlling prefetching data from the dynamic random access memory DRAM being in communication with the DRAM, the DRAM comprising one or more refresh units.

In a seventh aspect, the present application provides a computer readable storage medium comprising instructions which, when run on a computer, cause the computer to perform the method as described in the first aspect above.

In an eighth aspect, the present application provides a program product, such as a computer readable storage medium, comprising the program of the sixth aspect.

In a ninth aspect, the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the above aspects.

Therefore, in the aspects, the last level cache LLC effectively realizes the combination of the DRAM and the LLC by acquiring at least one refresh indication signal of the DRAM and generating a control signal according to the refresh indication signal, and can control the operation of prefetching data from the DRAM based on the control signal, thereby effectively solving the problem that the refresh has negative influence on the DRAM efficiency, particularly the influence of the refresh has superposition effect during multiple channels, and effectively improving the performance of the DRAM.

Drawings

FIG. 1 is a schematic diagram of a read/write operation for data in a DRAM according to the prior art;

FIG. 2 is a schematic diagram of a DRAM according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a DRAM according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a plurality of refresh channels in a DRAM according to an embodiment of the present application;

FIG. 5 is a flow chart of a method for controlling prefetching data from a DRAM according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a channel sending refresh indication signal according to an embodiment of the present disclosure;

FIG. 7 is a flow chart of the LLC generating at least one control signal according to the at least one refresh indication signal according to an embodiment of the present application;

FIG. 8 is a schematic flow chart of the LLC according to the embodiment of the present application controlling prefetching data from the DRAM according to the at least one control signal;

FIG. 9 is a schematic diagram of a flow of controlling prefetching data from the DRAM according to the adjusted prefetching capability according to the embodiment of the present application;

FIG. 10 is a schematic diagram of an apparatus for controlling prefetching data from a DRAM according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a processor according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of an apparatus for controlling prefetching data from a DRAM according to an embodiment of the present application;

fig. 13 is a schematic diagram of a second embodiment of an apparatus for controlling prefetching data from a DRAM.

Detailed Description

In the present application, "a plurality of" means two or more, and other adjectives are similar. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

For ease of understanding, several basic concepts in DRAM are described below with reference to FIGS. 2-3: memory Channel, memory block RANK, memory granule CHIP, BANK, bank_group, ROW, COLUMN, etc.

The memory CHANNEL is a DDR CHANNEL, and is a DDR controller and a memory medium corresponding to the controller. If there are multiple DDR CHANNEL channels in the CPU, these channels are typically identical and independent. By dual channel memory, it is essentially meant that the CPU has two completely independent memory controllers. Typical DDR controllers have a data bit width of 32 bits or 64 bits.

A Dual In-line Memory Module (DIMM) is commonly called a DIMM memory bank, a DIMM memory bank may be inserted into one DIMM slot on a motherboard, and a channel may correspond to one or more DIMM slots, as specifically shown In fig. 3. DIMM strips are realized by attaching a plurality of identical memory particles to the same PCB lining board.

The RANK refers to a group of memory granules that are parallel to each other so that the data bit width meets the bit width requirement of the DDR controller, and the group of memory granules is called RANK, also called P-BANK (physical BANK). The data bit width of a general memory controller is 32 bits or 64 bits, and the bit width of a single memory particle is generally 4 bits, 8 bits and 16 bits, so that a plurality of bits are required to be parallel to form the 32bit or 64bit width. For example: the data bit width of the memory controller is 64 bits, the bit width of the memory particles is 8 bits, and then 8 memory particles form a RANK; similarly, if the 64-bit data bit width is composed of 16-bit memory grains, only 4 data bits are needed. DIMMs are larger units than RANK, with 1-4 RANK per DIMM currently being used. Different ranks are connected to different chip select signals of the DDR controller.

CHIP is a single memory CHIP, commonly called memory granule, which is a basic unit for forming a memory bank: CHANNEL, DIMM, RANK, CHIP are: 1 CHANNEL may include multiple DIMMs, 1 DIMM may include multiple RANK, and 1 RANK may include multiple CHIP.

Further, when the DRAM is operating, it needs to be refreshed periodically to maintain the data stored therein unchanged. Specifically, since the DRAM is composed of a plurality of banks (banks), each Bank is a two-dimensional memory array, and is laterally called Row (Row) and vertically called Column (Column). In the refreshing process, each time a DRAM selects a Row (also referred to as a memory Row), all data of the Row is extracted into a sense amplifier (also referred to as a Row Buffer), this process is called an Active operation (Active), then the corresponding data is read and written into the Row Buffer, the data in the Row Buffer is rewritten into the memory array, which is called a precharge operation (Pre-charge), and the whole refreshing process is realized through the Active operation and the precharge operation. In addition, when the refresh operation is performed, the refresh between the memory channels is independent, as shown in fig. 4, the pulse of each channel in time sequence represents that the current channel performs the refresh operation according to the preset refresh time; for example, the channel CH0 performs the refresh operation according to the refresh time T0, the channel CH1 performs the refresh operation according to the refresh time T1, the channel CH2 performs the refresh operation according to the refresh time T2, and the channel CH3 performs the refresh operation according to the refresh time T3, wherein T0, T1, T2 and T3 are different from each other. In addition, different ranks or different Pseudo channels in the same Channel cannot be refreshed at the same time.

From the foregoing, it is clear that refresh has a negative impact on DRAM efficiency, and that the more channels, the greater the impact of refresh on efficiency. In addition, in the case of a strong memory access continuity, the above-described effect is also more serious because, in the case of a continuous address access, the access in a short time is uniformly interleaved to all channels (channel interleaving generally uses address low-order interleaving for the purpose of improving the bandwidth). Thus, as long as any channel in the system is in a refreshing state, a transient current interruption phenomenon can occur in the system, and therefore, the influence of refreshing has a superposition effect in the multi-channel.

The download/Store Queue depth of the CPU is relatively shallow, typically tens of times, where the download refers to reading data in the DRAM. Specifically, as shown in fig. 1, when the CPU 100 receives a memory access request sent by an external device, the CPU may perform read/write operations on data in the DRAM 200 through the memory controller (Memory Controller, MC) 101 according to the memory access request. Since the CPU design mechanism is usually notify in Order, that is, if a certain access request cannot be exited (i.e., DDR returns data), all subsequent access requests cannot release Queue even if completed. In combination with the timing parameters of the DDR refresh above, in a theoretical case, after the refresh, the DDR cannot return data for a certain access request, and the DDR is likely to have a situation where no request can be processed for a period of time, i.e., a usable but idle no-traffic slot occurs. As DDR channels (DDR channels) become more, the above situation is worse, resulting in a great decrease in DDR efficiency.

Therefore, there is a conflict between a long back pressure (a state in which a command cannot be processed when a refresh operation is performed) at the time of DDR refresh and a limited download/store queue depth of the CPU, which causes a loss of DDR efficiency. The industry mainly focuses on adjusting the refresh time to judge the number and type of refreshes to be processed in DDR, and the refreshes are advanced or delayed to optimize the system performance. However, the above method does not combine DDR refresh with prefatch of Last Level Cache (LLC) LLC, which is not effective.

Further, referring to fig. 5, in order to overcome the above-mentioned problems, the present application provides a method for controlling prefetching data from a DRAM, where the method may make some correlations between a Prefetch mechanism of an LLC and a refresh timing of a DDR in a communication system, so as to reduce the impact on efficiency to a great extent; for LLC, it is a cache area or a cache area in the CPU, which may be partitioned so that part or all of it may be used as a temporary storage (scratch), i.e. a temporary storage working area, which may be used to store critical data, for example: real-time codes, hash tables, statistics, counters, etc.; the prefetching mechanism of the LLC refers to taking data in the DRAM into the LLC in advance to avoid the occurrence of an inability to perform normal read-write operation on the data in the course of the DRAM being in a refresh operation, for example, in order to ensure the quality and efficiency of the read-write operation on the data in the DRAM when the DRAM performs the refresh operation; thereby realizing control of the operation of prefetching data from the DRAM. Specifically, the method comprises the following steps:

S1: LLC obtains at least one refresh indication signal of DRAM;

wherein, at least one refresh indication signal of the DRAM may be sent by one or more refresh units in the DRAM, and the one or more refresh units may be a memory space included in the DRAM for one refresh; in particular, the refresh unit may include at least one of the following refresh units: CHANNEL, dual inline memory module DIMM, memory granule group RANK, or memory granule CHIP; when the LLC acquires the refresh indication signal, the LLC can directly send a signal acquisition request to the DRAM, so that one or more refresh units in the DRAM return a refresh indication signal according to the signal acquisition request, and at the moment, the LLC can actively acquire at least one refresh indication signal; alternatively, the LLC may also directly receive the refresh indication signal actively sent by one or more refresh units in the DRAM, where the LLC may passively obtain at least one refresh indication signal. As shown in fig. 6, assuming that the refresh unit in the DRAM is a channel, this may specifically include: the first channel CH0, the second channel CH1, the third channel CH2, and the fourth channel CH3, where CH0, CH1, CH3, and CH4 may actively or passively send a refresh indication signal to the LLC, so that the LLC may acquire at least one refresh indication signal. Of course, the specific manner of acquiring the refresh indication signal is not limited to the above two modes.

S2: LLC generates at least one control signal according to the at least one refresh indication signal;

after the LLC acquires the refresh indication signal, the refresh indication signal may be analyzed and processed, and at least one control signal may be generated according to the result of the analysis and processing, specifically, reference may be made to fig. 7 to 8, and in this embodiment, the final stage cache LLC may include a refresh signal processing unit and a Prefetch unit, where the refresh signal processing unit may analyze and process the received refresh indication signal, specifically, may process the refresh indication signal one by one, or may also process the refresh indication signal integrally, and after the analysis and processing, may output an output refresh signal (refresh output signal) to the Prefetch unit, where the output refresh signal is the control signal, i.e., the Prefetch unit may acquire the control signal.

S3: the LLC controls prefetching of data from the DRAM according to the at least one control signal.

After the LLC acquires at least one control signal, the operation of prefetching data from the DRAM may be controlled according to the control signal, specifically, the prefetched data in the DRAM may be acquired, and the prefetching capability of the LLC may be adjusted in time according to the prefetched data, for example: enhancing or weakening the prefetching capability of LLC, etc.; so that the efficiency of prefetching data from the DRAM can be effectively ensured.

The method for controlling the prefetching of the data from the DRAM is provided in the embodiment, the LLC acquires at least one refresh indication signal of the DRAM and generates at least one control signal according to the refresh indication signal, so that the operation of prefetching the data from the DRAM is effectively controlled through the combination of the DRAM and the LLC, specifically, the operation of prefetching the data from the DRAM can be controlled based on the control signal, the prefetching of the data in the DRAM can be acquired, the prefetching capacity of the LLC is timely adjusted according to the prefetching data, the quality and the efficiency of the prefetching of the data from the DRAM are guaranteed, the problem that the refreshing has negative influence on the DRAM efficiency is effectively solved, and particularly, when a plurality of channels are formed, the influence of the refreshing has a superposition effect, and the performance of the DRAM is effectively improved.

Further, as for the generation mode of the control signal, one of the possible modes is: the LLC generating at least one control signal from the at least one refresh-indication signal may comprise:

s21: the LLC performs a logical operation on the at least one refresh indicator signal to generate at least one control signal.

Specifically, the logic operation performed by the LLC on the at least one refresh indicator signal may include:

S211: the LLC or-operates at least one refresh-indication signal, or,

specifically, when the LLC acquires at least one refresh indication signal, all the refresh indication signals may be ored: for example: after the LLC receives the refresh indication signals sent by CH0, CH1, CH3, and CH4, part or all of the refresh indication signals of the respective channels may be directly ored, thereby generating at least one control signal. The method for generating at least one control signal through OR operation is easy to trigger, the implementation difficulty is low, and the accuracy of the acquired control signal is generally applicable to most of prefetch operations, so that the acquired control signal has higher necessity and higher applicability.

S212: the LLC ANDs at least one refresh indication signal.

Specifically, when the LLC acquires at least one refresh indication signal, all the refresh indication signals may be and-operated: for example: after receiving the refresh indication signals sent by CH0, CH1, CH3, and CH4, a part or all of the refresh indication signals of the channels may be directly and-calculated, thereby generating at least one control signal. For the mode of generating at least one control signal through AND operation, the implementation difficulty is low, the accuracy of the acquired control signal is moderate, and the method can be suitable for partial prefetching operation, so that the acquired control signal is less in necessity and low in applicability.

It is contemplated that the LLC generating at least one control signal from the at least one refresh-indication signal may further include: performing OR operation on one part of the acquired refresh indication signals, and performing AND operation on the other part of the refresh indication signals; or, performing OR operation on one part of the acquired refresh indication signals, while the other part of the refresh indication signals are not processed; or performing AND operation on one part of the acquired refresh indication signals, while the other part of the refresh indication signals are not processed; or, the acquired refresh indication signals are subjected to grouping processing, and the refresh indication signals in the grouping processing are processed, and the specific processing mode may include at least one of the following: or operation, AND operation or no processing; or, the number of the refresh units performing the refresh operation may be obtained, and a plurality of levels of control signals may be generated according to the refresh indication signals sent by the refresh units, where the control signals are used to control the strength of the Prefetch.

By performing OR operation or AND operation on the at least one refresh indication signal, different implementation modes can be adopted according to different use requirements and use situations, so that the flexible reliability of logic operation on the refresh indication signal is effectively ensured, and the application range of the method is further improved.

In addition, as for the generation manner of the control signal, with continued reference to fig. 7, another possible manner is as follows: the LLC generating at least one control signal from the at least one refresh indication signal comprises:

s22: LLC obtains at least one refreshing unit identifier, wherein the at least one refreshing unit identifier corresponds to the at least one refreshing indication signal one by one, the refreshing unit identifier is an identifier corresponding to a refreshing unit in the DRAM, and the refreshing unit refreshes a storage space included by the DRAM once;

s23: determining the at least one refresh indication signal as the at least one control signal corresponding to the at least one refresh unit identification.

Specifically, when the control signal is generated according to the refresh indication signal, the refresh indication signal may be directly determined as the control signal of the refresh unit corresponding to the refresh unit identifier without any processing, for example: after receiving the refresh indication signals sent by CH0, CH1, CH3, and CH4, at least one refresh unit identifier may be obtained, where the at least one refresh unit identifier corresponds to the at least one refresh indication signal one-to-one, for example: the refresh unit identifiers corresponding to the refresh indication signals can be obtained respectively as follows: c0, C1, C3 and C4, namely, the memory channels need to be distinguished, so that the refresh indication signal can be determined as the control signal of the corresponding refresh unit.

The refresh indication signal is determined to be the control signal of the refresh unit corresponding to the refresh unit identification by acquiring the refresh unit identification corresponding to the refresh indication signal, so that the refresh indication signal can be directly used as the control signal without any processing, the accuracy of control signal acquisition is ensured, the acquired control signal has the best effect, and the stability and the reliability of the method are further ensured.

Further, with continued reference to fig. 8-9, controlling, by the LLC in this embodiment, prefetching data from the DRAM based on the at least one control signal may include:

s31: LLC obtains the current working state of the refreshing unit;

the current working state of the refresh unit in the DRAM may include: a refresh state and a non-refresh state; specifically, for a specific acquisition mode of the current working state, one possible mode is: the refreshing period of the refreshing unit in the DRAM can be obtained, and the current working state of the refreshing unit in the DRAM is determined through analysis and judgment of the refreshing period; another way that can be achieved is: and acquiring a data processing signal of the refreshing unit in the DRAM, and determining the current working state of the refreshing unit in the DRAM through an analysis result of the data processing signal.

S32: adjusting the preset prefetching capacity of the LLC according to the current working state and the at least one control signal;

the prefetching capability may be a capability of prefetching data of the LLC preset or preconfigured by a user; the adjusted prefetching capacity is the capacity of prefetched data obtained by adjusting the prefetching capacity; for example: the prefetch capability of the LLC is H1, and the adjusted prefetch capability is H2, so that the adjusted prefetch capability can be determined to be H1+H2, H1-H2 or other relational expressions related to H1 and H2 after the prefetch capability is adjusted.

Specifically, adjusting the preset prefetching capability of the LLC according to the current operating state and the at least one control signal may include:

s321: if the current working state is a refreshing state, enhancing the prefetching capability according to the at least one control signal; or,

s322: and if the current working state is a non-refreshing state, reducing the prefetching capability according to the at least one control signal.

Specifically, when the current working state of the refresh unit in the DRAM is determined to be the refresh state, the prefetching capability of the LLC may be enhanced according to a preset proportion parameter or a preset algorithm, where the preset proportion parameter or the preset algorithm is used to limit the enhancement degree, and one skilled in the art may set different proportion parameters or algorithms according to specific requirements; the enhanced prefetching capacity is the adjusted prefetching capacity which needs to be obtained, so that the refreshing quality and the refreshing efficiency of the DRAM are ensured; when the current working state of the refreshing unit in the DRAM is determined to be the non-refreshing state, the prefetching capability of the LLC can be reduced according to a preset proportion parameter or a preset algorithm, wherein the preset proportion parameter or the preset algorithm is used for limiting the reduction degree, a person skilled in the art can set different proportion parameters or algorithms according to specific requirements, the prefetching capability after reduction is the adjusted prefetching capability required to be obtained, and the transition prefetching of the prefetching capability Over-Prefetch can be effectively prevented.

S33: and controlling prefetching data from the DRAM according to the adjusted prefetching capacity.

Specifically, the method for controlling prefetching data from the DRAM according to the adjusted prefetching capability comprises the following steps:

s331: determining a DRAM access request of the adjusted pre-fetch capability according to the adjusted pre-fetch capability;

after determining the adjusted prefetch capability, the DRAM access request for the adjusted prefetch capability may be determined using a pre-set mapping relationship between the adjusted prefetch capability and the DRAM access request.

S332: prefetching data from the DRAM is controlled by the DRAM access request.

After the DRAM access request is acquired, the operation of prefetching data from the DRAM may be controlled based on the DRAM access request, so that the quality and efficiency of the DRAM refresh operation may be effectively ensured.

In this embodiment, the refresh unit in the DRAM can provide the LLC with the refresh indication signal, and a refresh signal processing unit is added in the LLC, where the refresh signal processing unit can process the refresh indication signal sent by each refresh unit, and uniformly perform logic processing to generate a control signal of the Prefetch unit, that is, the control signal, and after the Prefetch unit receives the control signal, the Prefetch capability can be enhanced during the refresh period of the DRAM, and weakened during the non-refresh period, so that excessive prefetching can be prevented, and the refresh quality and efficiency of the DRAM are also ensured, the practicability of the method is effectively improved, and the method is beneficial to market popularization and application.

FIG. 10 is a schematic diagram of an apparatus for controlling prefetching data from a DRAM according to an embodiment of the present application; referring to fig. 10, the present embodiment provides an apparatus for controlling prefetching data from a DRAM, comprising:

an acquisition module 1, configured to acquire at least one refresh indication signal of the DRAM;

a generating module 2, configured to generate at least one control signal according to the at least one refresh indication signal;

and the control module 3 is used for controlling the prefetching of data from the DRAM according to the at least one control signal.

Further, when the generating module 2 generates at least one control signal according to the at least one refresh indication signal, one implementation manner may be that the generating module 2 is configured to perform: and carrying out logic operation on the at least one refresh indication signal to generate the at least one control signal.

Wherein, when the generating module 2 performs a logic operation on the at least one refresh indication signal, the generating module 2 may be configured to perform:

and performing OR operation on the at least one refresh indication signal or performing AND operation on the at least one refresh indication signal.

Further, when the generating module 2 generates at least one control signal according to the at least one refresh indication signal, another implementation manner is that the generating module 2 may be configured to perform:

acquiring at least one refresh unit identifier, wherein the at least one refresh unit identifier corresponds to the at least one refresh indication signal one by one, the refresh unit identifier is an identifier corresponding to a refresh unit in the DRAM, and the refresh unit performs one-time refresh on a storage space included in the DRAM; wherein the refresh unit comprises at least one of the following refresh units: CHANNEL, dual inline memory module DIMM, memory granule group RANK, or memory granule CHIP; determining the at least one refresh indication signal as the at least one control signal corresponding to the at least one refresh unit identification.

Further, when the control module 3 controls the prefetching of data from the DRAM according to the at least one control signal, the control module 3 may be configured to perform: acquiring the current working state of the refreshing unit; adjusting the pre-fetching capability of the preset LLC according to the current working state and the at least one control signal; and controlling prefetching data from the DRAM according to the adjusted prefetching capacity.

Wherein, when the control module 3 adjusts the pre-fetching capability of the preset LLC according to the current operating state and the at least one control signal, the control module 3 may be configured to perform:

if the current working state is a refreshing state, enhancing the prefetching capability according to the at least one control signal; or if the current working state is a non-refreshing state, reducing the prefetching capability according to the at least one control signal.

Further, when the control module 3 controls prefetching data from the DRAM according to the adjusted prefetching capability, the control module 3 may be configured to perform:

determining a DRAM access request of the adjusted pre-fetch capability according to the adjusted pre-fetch capability; prefetching data from the DRAM is controlled by the DRAM access request.

The apparatus for controlling prefetching data from a DRAM in this embodiment may be used to implement the technical solutions of the embodiments shown in fig. 1 to 9 in the above-mentioned methods, and its implementation principle and technical effects are similar, and will not be described herein again.

FIG. 11 is a schematic diagram of a processor according to an embodiment of the present disclosure; referring to fig. 11, the present embodiment provides a processor, including: a last level cache LLC 302, the LLC 302 being configured to:

Acquiring at least one refresh indication signal of the DRAM; generating at least one control signal according to the at least one refresh indication signal; and controlling prefetching data from the DRAM according to the at least one control signal.

Further, the processor may further include:

and the memory controller 301 is connected with the LLC 302 and is used for implementing read-write operation on data in the DRAM connected with the processor.

The processor in this embodiment may be used to execute the technical solutions of the embodiments shown in fig. 1 to 9 in the above-mentioned methods, and the implementation principle and the technical effects are similar, and are not repeated here.

FIG. 12 is a schematic diagram of an apparatus for controlling prefetching data from a DRAM according to an embodiment of the present application; referring to fig. 12, the present embodiment provides an apparatus for controlling prefetching data from a DRAM, comprising:

a memory 402;

a processor 401; and

a computer program;

wherein the computer program is stored in the memory 402 and configured to be executed by the processor 401 for implementing the method described above.

FIG. 13 is a schematic diagram II of an apparatus for controlling prefetching data from a DRAM according to an embodiment of the present application; referring to fig. 13, another aspect of the present embodiment provides an apparatus for controlling prefetching data from a dynamic random access memory DRAM, comprising:

processor 510, memory 520, communication interface 530, and bus 540, wherein processor 510, memory 520, and communication interface 530 communicate over bus 540;

memory 520 is used to store a computer program;

the communication interface 530 is used for communication with the DRAM;

when the processing device is running, the processor 510 is configured to execute the program stored in the memory 520 to perform the method described above.

Yet another aspect of the present embodiment provides a system for controlling prefetching data from a dynamic random access memory DRAM, comprising: at least one dynamic random access memory DRAM, and means for controlling the prefetching of data from the dynamic random access memory DRAM as described above, the means for controlling the prefetching of data from the dynamic random access memory DRAM being in communication with the DRAM, the DRAM comprising one or more refresh units.

The system for controlling the prefetching of data from the DRAM in this embodiment may be used to implement the technical solutions of the embodiments shown in fig. 1 to 9 in the above-mentioned method, and its implementation principle and technical effects are similar, and will not be described here again.

Another aspect of the present embodiment provides a computer readable storage medium comprising instructions which, when run on a computer, cause the computer to perform a method as in any of the embodiments above.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, fiber optic, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means from one website, computer, server, or data center. Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc., that contain an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy Disk, a hard Disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

Claims

1. A method for controlling prefetching of data from a dynamic random access memory DRAM, comprising:

2. The method of claim 1, wherein the LLC generates at least one control signal based on the at least one refresh-indication signal, including:

3. The method of claim 2, wherein the LLC logically operates on the at least one refresh-indication signal, comprising:

the LLC ANDs the at least one refresh indication signal.

4. The method of claim 1, wherein the LLC generates at least one control signal based on the at least one refresh-indication signal, including:

5. The method of claim 4, wherein the LLC controlling prefetching data from the DRAM in accordance with the at least one control signal, comprises:

The LLC acquires the current working state of the refreshing unit;

6. The method of claim 5, wherein said adjusting the pre-set prefetching capabilities of the LLC based on the current operating state and the at least one control signal comprises:

7. The method of claim 5 or 6, wherein controlling prefetching data from the DRAM based on the adjusted prefetching capability comprises:

prefetching data from the DRAM is controlled by the DRAM access request.

8. The method of claim 5, wherein the refresh unit comprises at least one of the following refresh units:

9. An apparatus for controlling prefetching of data from a dynamic random access memory, DRAM, said apparatus being a last level cache, LLC, comprising:

10. The apparatus of claim 9, wherein the generating module is configured to:

11. The apparatus of claim 10, wherein the generating module is configured to:

or the at least one refresh indication signal, or,

and performing AND operation on the at least one refresh indication signal.

12. The apparatus of claim 9, wherein the generating module is configured to:

13. The apparatus of claim 12, wherein the control module is configured to:

acquiring the current working state of the refreshing unit;

14. The apparatus of claim 13, wherein the control module is configured to:

15. The apparatus of claim 13 or 14, wherein the control module is configured to:

prefetching data from the DRAM is controlled by the DRAM access request.

16. The apparatus of claim 13, wherein the refresh unit comprises at least one of the following refresh units:

17. A processor, comprising:

the last level cache LLC is configured to:

acquiring at least one refresh indication signal of the DRAM;

18. The processor of claim 17, further comprising:

19. A system for controlling prefetching of data from a dynamic random access memory DRAM, comprising: at least one dynamic random access memory DRAM, and an apparatus for controlling prefetching data from a dynamic random access memory DRAM according to any of claims 9-16, said apparatus in communication with said DRAM, said DRAM comprising one or more refresh units.