CN112563189A - Manufacturing method of compressive stress GOI - Google Patents
Manufacturing method of compressive stress GOI Download PDFInfo
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- CN112563189A CN112563189A CN202011269591.4A CN202011269591A CN112563189A CN 112563189 A CN112563189 A CN 112563189A CN 202011269591 A CN202011269591 A CN 202011269591A CN 112563189 A CN112563189 A CN 112563189A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 43
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 27
- 230000007547 defect Effects 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000005498 polishing Methods 0.000 claims abstract description 9
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000000407 epitaxy Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000002360 preparation method Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 239000013078 crystal Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 6
- 238000012876 topography Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
本发明涉及一种压应力GOI的制作方法。一种压应力GOI的制作方法，包括：步骤a：在第一衬底上形成氧化硅层，然后对所述氧化硅层图形化刻蚀，形成多个沟道，并且所述沟道穿透所述氧化硅层；步骤b：在图形化的所述氧化硅层表面选择性外延生长第二锗层，然后化学机械抛光；步骤c：重复所述步骤a至b零次或至少一次，然后以最后的锗层为键合界面与第二衬底键合，之后刻蚀至仅保留所述第二衬底和所述最后的锗层，平坦化。本发明利用沟道可有效抑制锗Ge晶格表面缺陷而带来的界面缺陷，重复沟道形成和选择性外延Ge的方法，还可以将Ge的缺陷密度最小化。
The invention relates to a preparation method of compressive stress GOI. A method for manufacturing a compressive stress GOI, comprising: step a: forming a silicon oxide layer on a first substrate, and then patterning and etching the silicon oxide layer to form a plurality of channels, and the channels penetrate the silicon oxide layer; step b: selectively epitaxially growing a second germanium layer on the surface of the patterned silicon oxide layer, followed by chemical mechanical polishing; step c: repeating the steps a to b zero or at least once, and then The last germanium layer is used as a bonding interface to bond with the second substrate, and then etching is performed until only the second substrate and the last germanium layer are left, and then planarized. The invention utilizes the channel to effectively suppress the interface defects caused by the surface defects of the germanium-Ge crystal lattice, repeats the method of channel formation and selective epitaxy of Ge, and can also minimize the defect density of Ge.
Description
Technical Field
The invention relates to the field of semiconductor production processes, in particular to a manufacturing method of compressive stress GOI.
Background
Germanium-On-Insulator (GOI) combines the advantages of Ge and SOI structures, and has become an ideal material for fabricating p-channel MOSFETs and MSM (Metal-Semiconductor-Metal) photodetectors. GOI is structurally similar to SOI with the introduction of a buried oxide layer between the top Ge and the backing substrate. Due to the introduction of the oxide layer, the GOI has the advantages of bulk germanium, the oxide layer can play a role in dielectric isolation of the device, and parasitic capacitance of the device can be reduced.
The manufacturing method of the traditional GOI comprises the following steps: the Ge film is directly grown on the substrate, the lattice mismatch is very large (up to 4.2 percent), the defects are many, and the prepared photoelectric device has large dark current and large noise. And the lattice mismatch is large, the defect distribution of the prepared 8-inch Ge epitaxial layer is wide, the preparation of large-scale photoelectric devices cannot be met, and the yield of the devices is low.
The invention is therefore proposed.
Disclosure of Invention
The invention mainly aims to provide a manufacturing method of compressive stress GOI, which utilizes a channel to effectively inhibit interface defects caused by germanium Ge crystal lattice surface defects, repeats a channel forming and selective Ge epitaxial method and can also minimize the Ge defect density.
In order to achieve the above object, the present invention provides the following technical solutions.
A manufacturing method of compressive stress GOI comprises the following steps:
step a: forming a silicon oxide layer on a first substrate, then carrying out patterned etching on the silicon oxide layer to form a plurality of channels, wherein the channels penetrate through the silicon oxide layer;
step b: selectively and epitaxially growing a second germanium layer on the surface of the patterned silicon oxide layer, and then carrying out chemical mechanical polishing;
step c: repeating the steps a to b for zero times or at least one time, then bonding with a second substrate by taking the final germanium layer as a bonding interface, etching until only the second substrate and the final germanium layer are remained, and flattening; the second substrate is a silicon wafer deposited with a buried oxide layer, and the buried oxide layer is used as a bonding interface during bonding;
if the steps a to b are repeated zero times in the step c, before the step a of forming the silicon oxide layer, the method further comprises: a first layer of germanium is first deposited on a first substrate and chemically mechanically polished until the first layer of germanium is in a relaxed state.
Compared with the prior art, the invention achieves the following technical effects:
(1) the silicon oxide is used for forming a channel, and the channel can effectively inhibit interface defects caused by germanium Ge crystal lattice surface defects, so that a compressive stress type GOI structure is obtained, and the yield of devices is improved;
(2) repeating the channel formation and selective epitaxy of Ge multiple times may also minimize the defect density of Ge.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIGS. 1 to 6 are schematic diagrams of steps in a GOI structure manufacturing process according to the present invention;
FIG. 7 is a topographical view of another GOI structure provided in the present invention during fabrication;
FIGS. 8-15 are topographical views of various steps in another GOI structure fabrication process provided by the present invention;
FIG. 16 is a topographical view of another GOI structure provided by the present invention during fabrication.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The invention inhibits interface defects caused by germanium Ge crystal lattice surface defects by Selectively Epitaxially Growing (SEG) germanium on a channel, and the specific process is as follows:
step a: forming a silicon oxide layer on a first substrate, then carrying out patterned etching on the silicon oxide layer to form a plurality of channels, wherein the channels penetrate through the silicon oxide layer;
step b: selectively and epitaxially growing a second germanium layer on the surface of the patterned silicon oxide layer, and then carrying out chemical mechanical polishing;
step c: repeating the steps a to b for zero times or at least one time, then bonding with a second substrate by taking the final germanium layer as a bonding interface, etching until only the second substrate and the final germanium layer are remained, and flattening; the second substrate is a silicon wafer with a front surface deposited with a buried oxide layer, and the buried oxide layer is used as a bonding interface during bonding;
if the steps a to b are repeated zero times in the step c, before the step a of forming the silicon oxide layer, the method further comprises: a first layer of germanium is first deposited on a first substrate and chemically mechanically polished until the first layer of germanium is in a relaxed state.
In the above method, the first substrate may be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as silicon-on-insulator (SOI), silicon wafer, germanium, silicon-germanium, gallium arsenide, or germanium-on-insulator; since the first substrate is used as a sacrificial layer, a silicon wafer having high cost performance is preferably selected.
The silicon oxide layer to be patterned may be formed by a thermal oxidation (dry or wet oxygen) process, chemical vapor deposition, atomic layer deposition, or the like.
The patterning etching means of the silicon oxide layer may be dry method, wet method or plasma, etc., and is performed in combination with a photoresist mask, and the plurality of trenches are preferably arranged regularly, for example, symmetrically at equal intervals, etc. The width between the channels is adjusted as desired.
The goal of chemical mechanical polishing is primarily to bring the germanium layer to a relaxed state, typically within 9 seconds.
The buried oxide layer in the second substrate is silicon oxide SiO2Etc. insulating material.
The number of times said steps a to b are repeated in step c is generally determined according to the following principle: repeating until the defect density of the last germanium layer is no longer reduced. In the process of repeating the steps a to b, the channel formed in the step a and the channel formed in the previous step a are arranged in a staggered mode, so that the defect in the channel can be prevented from extending to the bottom of the upper epitaxial layer, and the quality of the upper germanium film can be greatly improved.
In addition, the addition of the first germanium layer is more beneficial to inhibiting interface defects caused by surface defects of germanium Ge crystal lattices. The first germanium layer may be formed by any means including, but not limited to, typical global epitaxy and selective epitaxy.
One embodiment of the present invention is as follows.
Example 1
The process flow of the morphology change shown in fig. 1 to 6 is as follows:
in a first step, a first germanium layer 102 is deposited on a silicon wafer 101 and then CMP is performed until it is in a relaxed state, as shown in the topography of fig. 1.
Secondly, a silicon oxide layer 103 is deposited by PECVD means, as shown in the figure 2.
Third, the silicon oxide layer is patterned to form a plurality of trenches 104, as shown in fig. 3.
Fourth, second germanium layer 105 is selectively epitaxially grown on the patterned silicon oxide layer surface, followed by CMP, as shown in the topography of fig. 4.
And fifthly, selecting another silicon wafer with a silicon oxide layer on the surface as a second substrate 106, bonding the silicon oxide layer with the semiconductor structure formed in the previous step by using the silicon oxide layer as a bonding interface, and taking the second germanium layer of the semiconductor structure in the fourth step as a bonding interface, wherein the shape is shown in fig. 5.
Sixthly, etching to remove the sacrificial layer: etching to leave only the second substrate and the final germanium layer, and planarizing to obtain the GOI structure, such as the topography shown in fig. 6.
It is also possible to repeat the second through fourth steps one or more times before the fifth bonding step until the defect density of the final germanium layer is no longer reduced, and the invention also includes these embodiments with a preferred staggered arrangement between the channels of adjacent layers. For example, when the process is repeated 1 time, the profile shown in fig. 7 is formed, and then the sacrificial layer is bonded to the second substrate and removed.
Another embodiment of the present invention is as follows.
Example 2
The process flow for the profile variation shown in fig. 8 to 15 is as follows:
in the first step, a silicon oxide layer 202 is deposited on a silicon wafer 201 by PECVD, followed by CMP, as shown in fig. 8.
In the second step, the silicon oxide layer is patterned to form a plurality of first trenches 203, as shown in fig. 9.
Third, a first layer of germanium 204 is selectively epitaxially grown on the patterned silicon oxide layer and then CMP is performed until it is in a relaxed state, as shown in FIG. 10.
And fourthly, repeating the first step to the third step, and sequentially forming a second layer of silicon oxide 205 (with the morphology shown in FIG. 11), forming a second layer of channels 206 (with the morphology shown in FIG. 12, the second layer of channels and the first layer of channels are arranged in a staggered mode), and extending a second layer of germanium 207 (with the morphology shown in FIG. 13).
And fifthly, selecting another silicon wafer with a silicon oxide layer on the surface as a second substrate 208, bonding the silicon oxide layer with the semiconductor structure formed in the previous step by using the silicon oxide layer as a bonding interface, and taking the final germanium layer in the semiconductor structure in the fourth step as the bonding interface, wherein the shape is shown in fig. 14.
Sixthly, etching to remove the sacrificial layer: etching to leave only the second substrate and the final germanium layer and planarizing to obtain the GOI structure, the topography shown in fig. 15.
The invention may also include in the fourth step, from the first step to the third step, a plurality of times until the defect density of the final germanium layer is no longer reduced, these embodiments being included in the invention, and preferably with a staggered arrangement between the channels of adjacent layers. For example, when the process is repeated 1 time, the profile shown in fig. 16 is formed, and then the sacrificial layer is bonded to the second substrate and removed.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113314395A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314396A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314394A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157432A (en) * | 2011-01-24 | 2011-08-17 | 清华大学 | GeOI structure and formation method thereof |
| CN102201364A (en) * | 2011-05-26 | 2011-09-28 | 北京大学 | Method for preparing germanium-on-insulator (GeOI) substrate |
| US20170271201A1 (en) * | 2014-05-23 | 2017-09-21 | Massachusetts Institute Of Technology | Method of manufacturing a germanium-on-insulator substrate |
| CN111668090A (en) * | 2020-07-31 | 2020-09-15 | 广东省大湾区集成电路与系统应用研究院 | A kind of semiconductor structure and its manufacturing method |
| CN111681951A (en) * | 2020-07-31 | 2020-09-18 | 广东省大湾区集成电路与系统应用研究院 | A kind of semiconductor structure and its manufacturing method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157432A (en) * | 2011-01-24 | 2011-08-17 | 清华大学 | GeOI structure and formation method thereof |
| CN102201364A (en) * | 2011-05-26 | 2011-09-28 | 北京大学 | Method for preparing germanium-on-insulator (GeOI) substrate |
| US20170271201A1 (en) * | 2014-05-23 | 2017-09-21 | Massachusetts Institute Of Technology | Method of manufacturing a germanium-on-insulator substrate |
| CN111668090A (en) * | 2020-07-31 | 2020-09-15 | 广东省大湾区集成电路与系统应用研究院 | A kind of semiconductor structure and its manufacturing method |
| CN111681951A (en) * | 2020-07-31 | 2020-09-18 | 广东省大湾区集成电路与系统应用研究院 | A kind of semiconductor structure and its manufacturing method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113314395A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314396A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314394A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
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Application publication date: 20210326 |