CN112563131B - A method for preparing a metal gate device - Google Patents
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- CN112563131B CN112563131B CN202011461041.2A CN202011461041A CN112563131B CN 112563131 B CN112563131 B CN 112563131B CN 202011461041 A CN202011461041 A CN 202011461041A CN 112563131 B CN112563131 B CN 112563131B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
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- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
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Abstract
The invention provides a preparation method of a metal gate device, which comprises the steps of forming a first opening in a pseudo gate layer of a second region, wherein an extension line of a side wall of the first opening is aligned with a crossing line of the first region and the second region; forming a first sacrificial layer on the dummy gate layer and a second sacrificial layer filling the first opening; etching the first sacrificial layer and the dummy gate layer of the first region to form a second opening, wherein the side wall of the second opening exposes the second sacrificial layer; a first gate structure is formed within the second opening. According to the invention, the second sacrificial layer is formed at the junction of the first region and the second region and is used as the side wall barrier layer, so that etching defects are prevented from being formed on the side wall of the pseudo gate layer of the second region in the process of removing the pseudo gate layer of the first region by adopting a wet etching process, and meanwhile, the damage of the dry etching process to the gate dielectric layer is also prevented, so that the method has remarkable significance.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a preparation method of a metal gate device.
Background
For half a century, the number of transistors that can be accommodated in an integrated circuit has doubled every 18 months, driven by moore's law, with a consequent reduction in transistor size. With the continuous reduction of the feature size of the transistor in the CMOS circuit, the thickness of the gate dielectric SiO 2 is also continuously reduced, the insulating layer SiO 2 in the transistor reaches the physical limit of about 10A, siO 2 below 2nm is no longer an ideal insulator, obvious tunneling leakage current can occur, the leakage current can exponentially rise along with the reduction of the thickness, and the leakage current of SiO 2 below 1nm can be unacceptably High, so that the High-K/METAL GATE (HKMG) technology is started in the High-performance process.
The HKMG technology refers to a high-K (high-K) gate dielectric + METAL GATE (metal gate) electrode stack technology, wherein the high-K technology is a high-K gate dielectric technology, and by adopting a high-K dielectric instead of SiO 2 as a gate dielectric layer, the K value of the high-K dielectric is about 6 times higher than that of SiO 2, and under the same voltage and electric field strength, the physical thickness of the dielectric can be 6 times that of SiO 2 as a dielectric layer, thereby reducing the process difficulty of the high-quality dielectric layer and reducing the electric leakage caused by quantum tunneling effect, and further greatly reducing the gate leakage of the semiconductor device.
The METAL GATE technology refers to a metal gate technology, since the work function of the high-k gate dielectric material is not matched with that of the traditional polysilicon gate material, if the polysilicon gate is used continuously, the gate fermi level pinning phenomenon occurs, so that the work function of the gate material is not adjustable, and a new gate material must be replaced, and replacing the polysilicon with a metal electrode is an ideal solution.
The conventional metal gate forming process includes the process steps of depositing and removing the pseudo gate layer, forming the metal gate and the like, the pseudo gate layer needs to be removed before the metal gate is prepared, and the conventional pseudo gate layer removing method includes a dry etching method, a wet etching method or a dry humidifying method combination mode, but all the three methods have respective defects in the implementation process.
Fig. 1 is a cross-sectional view of a PMOS region after removal of a dummy gate layer using a dry etching process, where a dry etching plasma causes damage to the gate oxide layer over the active region, thereby causing degradation of device characteristics and reliability failure.
FIG. 2 is a cross-sectional view of a PMOS region after removal of a dummy gate layer by a wet etching process, wherein the dummy gate layer in the NMOS region is simultaneously etched due to the isotropic properties of the wet etching to form an arc-shaped defect of the NMOS dummy gate layer, which causes subsequent intrusion of a PMOS metal gate into the NMOS region, resulting in failure of the MOS device; meanwhile, the arc-shaped side wall of the pseudo gate layer causes discontinuous deposition of a subsequent metal gate barrier layer and diffusion of metal elements, and the degradation of device characteristics and reliability failure can be caused.
Fig. 3 is a cross-sectional view of a PMOS region after removing a dummy gate layer by a dry process and then a wet process, where the process can avoid damage to the gate oxide layer by dry etching plasma, but the wet process may cause internal cutting morphology at the bottom of the dummy gate layer, thereby causing discontinuous deposition of a barrier layer of a subsequent metal gate and diffusion of metal elements, and eventually causing degradation of device characteristics and reliability failure.
Therefore, a method for forming a metal gate device is needed, which can avoid damaging a gate oxide layer when removing a dummy gate layer in a PMOS region, and simultaneously prevent a PMOS metal gate from invading an NMOS region and ensure the continuity of a metal gate barrier layer deposited later, so as to improve the performance and reliability of the device.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a preparation method of a metal gate device, which comprises the following steps:
providing a substrate, wherein the substrate comprises a first region and a second region adjacent to the first region;
Forming a shallow trench isolation structure in the substrate;
forming a gate dielectric layer covering the shallow trench isolation structure on the substrate;
forming a pseudo gate layer on the gate dielectric layer;
Forming a first opening in the dummy gate layer of the second region, wherein an extension line of a side wall of the first opening is aligned with an intersection line of the first region and the second region;
Forming a first sacrificial layer on the dummy gate layer and a second sacrificial layer filling the first opening;
Etching the first sacrificial layer and the dummy gate layer of the first region to form a second opening, wherein the side wall of the second opening exposes the second sacrificial layer;
forming a first gate structure in the second opening, wherein the top surface of the first gate structure is flush with the surface of the first sacrificial layer;
Removing the second sacrificial layer and the first sacrificial layer of the second region;
Etching the pseudo gate layer of the second region to form a third opening, wherein the side wall of the third opening exposes the side wall of the first gate structure;
a second gate structure is formed within the third opening, the second gate structure being adjacent to the first gate structure, and a top surface of the second gate structure being level with a top surface of the first gate structure.
Preferably, the material of the dummy gate layer includes polysilicon, and the material of the first sacrificial layer includes one or more of silicon nitride, silicon oxynitride, titanium nitride, and tantalum nitride.
Preferably, the material of the second sacrificial layer includes one or more of silicon nitride, silicon oxynitride, titanium nitride, and tantalum nitride.
Preferably, the gate dielectric layer comprises a gate oxide layer and a barrier layer positioned on the gate oxide layer, and the material of the gate oxide layer comprises one or more combinations of silicon dioxide, silicon oxynitride, hafnium oxide and aluminum oxide.
Preferably, the first opening is formed using a first etching process, which includes anisotropic dry etching.
Preferably, the first sacrificial layer of the first region is etched using a second etching process, the second etching process comprising one or a combination of two of dry etching or wet etching.
Preferably, the dummy gate layer of the first region is etched using a third etching process, the third etching process including wet etching.
Preferably, the first gate structure includes a first diffusion barrier layer located at a sidewall and a bottom of the second opening, a first work function layer located on the first diffusion barrier layer, and a first electrode layer located on the first work function layer.
Preferably, the second sacrificial layer and the first sacrificial layer of the second region are removed using a fourth etching process, which includes wet etching.
Preferably, the first region is an NMOS region, and the second region is a PMOS region; or, the first region is a PMOS region, and the second region is an NMOS region.
According to the technical scheme, the invention provides a preparation method of a metal gate device, a first opening is formed in a pseudo gate layer of a second region, and an extension line of a side wall of the first opening is aligned with a junction line of the first region and the second region; forming a first sacrificial layer on the dummy gate layer and a second sacrificial layer filling the first opening; etching the first sacrificial layer and the dummy gate layer of the first region to form a second opening, wherein the side wall of the second opening exposes the second sacrificial layer; forming a first gate structure in the second opening, wherein the top surface of the first gate structure is flush with the surface of the first sacrificial layer; removing the second sacrificial layer and the first sacrificial layer of the second region; etching the pseudo gate layer of the second region to form a third opening, wherein the side wall of the third opening exposes the side wall of the first gate structure; a second gate structure is formed within the third opening, the second gate structure being adjacent to the first gate structure, and a top surface of the second gate structure being level with a top surface of the first gate structure.
According to the invention, the second sacrificial layer is formed at the junction of the first region and the second region and is used as the side wall barrier layer, so that in the process of removing the pseudo gate layer of the first region by adopting the wet etching process, the formation of etching defects on the side wall of the pseudo gate layer of the second region caused by isotropic etching is avoided, and meanwhile, the damage of the dry etching process to the gate dielectric layer is avoided because of adopting the wet etching process. In addition, after the second sacrificial layer is removed, the side wall of the pseudo gate layer of the second region is steep, the first electrode layer of the first region is prevented from invading the second region, the continuity of the side wall of the subsequently deposited first diffusion barrier layer is ensured, the purpose of improving the performance and the reliability of the device is achieved, and the method has obvious significance.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a cross-sectional view of a device after removal of a dummy gate layer in a PMOS region using a dry etch process
FIG. 2 is a cross-sectional view of a device after removal of a dummy gate layer in a PMOS region using a wet etch process
FIG. 3 is a cross-sectional view of a device after removing the dummy gate layer in the PMOS region by a dry-then-wet process
Fig. 4 to 14 are schematic structural views showing a process of manufacturing a metal gate device according to an embodiment of the present invention
Detailed Description
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.
In the following detailed description of the embodiments of the present invention, the structures of the present invention are not drawn to a general scale, and the structures in the drawings are partially enlarged, deformed, and simplified, so that the present invention should not be construed as being limited thereto.
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the following is a schematic structural diagram of a manufacturing process of a metal gate device according to an embodiment of the present invention, with reference to fig. 4 to 14.
Referring to fig. 4, a substrate is provided, the substrate including a first region and a second region adjacent to the first region.
In this embodiment, a substrate 100 is provided, the substrate 100 including a first region I and a second region II adjacent to the first region I. The substrate 100 is one of a silicon substrate, a silicon-on-insulator substrate, and a silicon germanium substrate, and the first region I and the second region II are adjacent. In the subsequent process, NMOS transistors are formed in the first region I, PMOS transistors are formed in the second region II, and in other embodiments, PMOS transistors are formed in the first region I, NMOS transistors are formed in the second region II, and the number and location of the first and second regions I and II should not excessively limit the scope of the present invention. In this embodiment, taking a MOS device structure using a silicon substrate and a forming method as an example, a process flow cross-sectional diagram only describes a process related to the present invention, and conventional process flows such as well implantation, source-drain implantation, and sidewall etching related to the remaining devices are not shown in the flowchart.
Referring to fig. 5, shallow trench isolation structures 120 are formed in the substrate 100.
In this embodiment, the shallow trench isolation structure 120 includes a first trench isolation region located in the first region I and a second trench isolation region located in the second region II adjacent to the first trench isolation region. In one embodiment, the shallow trench isolation structure 120 is used to electrically isolate the polysilicon resistor subsequently formed on the surface of the shallow trench isolation structure from the substrate 100 and other devices. In other embodiments, the shallow trench isolation structure 120 is further formed around the substrate of the first region i, for electrically isolating different MOS transistors.
Referring to fig. 6, a gate dielectric layer 130 is formed on the substrate 100 to cover the shallow trench isolation structure 120.
In this embodiment, the gate dielectric layer 130 is a composite layer, and the composite layer includes a gate oxide layer (not shown) and a barrier layer (not shown) located on the gate oxide layer, where the material of the gate oxide layer includes one or more combinations of silicon dioxide, silicon oxynitride, hafnium oxide, and aluminum oxide. In an embodiment, the substrate 100 is a silicon substrate, the gate oxide layer is made of silicon dioxide, and the gate oxide layer is formed on the surface of the silicon substrate by a thermal oxidation process. In another embodiment, the gate dielectric layer 130 is made of a high-K gate dielectric material, where the high-K gate dielectric material includes one or more of hafnium oxide (HfO 2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and the like. The formation process of the gate dielectric layer 130 includes one or two of atomic layer deposition process and magnetron sputtering.
Referring to fig. 7, a dummy gate layer 140 is formed on the gate dielectric layer 130.
In this embodiment, the material of the dummy gate layer 140 includes polysilicon. The forming process of the dummy gate layer 140 includes one of a chemical vapor deposition process (CVD), a physical vapor deposition Process (PVD), or an epitaxial growth process. The process steps of forming the dummy gate layer 140 include: a polysilicon layer is formed on the substrate 100, and the polysilicon layer is etched, leaving only the dummy gate layer 140 over the first region i and the second region ii.
Referring to fig. 8, a first opening 101 is formed in the dummy gate layer 140 of the second region II, and an extension line of a sidewall of the first opening 101 is aligned with a junction line of the first region I and the second region II.
In this embodiment, a photoresist is coated on the dummy gate layer 140 of the second region II, then a pattern and a position of the first opening 101 are defined on the dummy gate layer 140 of the second region II by a photolithography process, then the first opening 101 is formed by a first etching process, and finally the photoresist is removed. The first etching process includes anisotropic dry etching. The extension line of the side wall of the first opening 101 is aligned with the intersection line of the first region I and the second region II, so that the extension line of the side wall of the second sacrificial layer that subsequently fills the first opening 101 is aligned with the intersection line of the first region I and the second region II.
Referring to fig. 9, a first sacrificial layer 151 and a second sacrificial layer 152 filling the first opening 101 (not shown) are formed on the dummy gate layer 140.
The material of the first sacrificial layer 151 includes one or more of silicon nitride, silicon oxynitride, titanium nitride, and tantalum nitride. The material of the second sacrificial layer 152 includes one or more of silicon nitride, silicon oxynitride, titanium nitride, and tantalum nitride. In this embodiment, the second sacrificial layer 152 is formed at the junction of the PMOS region and the NMOS region, so that in the subsequent process of removing the dummy gate layer 140 by using a wet etching process, an etching angle defect generated by isotropic etching is avoided, and damage to the gate dielectric layer 130 by the etching process is also avoided.
In this embodiment, the first sacrificial layer 151 and the second sacrificial layer 152 are formed simultaneously by using a deposition process, and the materials of the first sacrificial layer 151 and the second sacrificial layer 152 that are formed simultaneously are the same. In another embodiment, the second sacrificial layer 152 for filling the first opening is formed first, then the surface of the dummy gate layer 140 is exposed by adopting a grinding process, and then the first sacrificial layer 151 is formed on the dummy gate layer 140, so that on one hand, the filling rate of the first opening 101 is ensured, no void or other defect is ensured, and meanwhile, the flatness of the first sacrificial layer 151 is ensured, and the difficulty of the subsequent etching process is reduced.
Referring to fig. 10, the first sacrificial layer 151 and the dummy gate layer 140 of the first region I are etched to form a second opening (not shown), and the sidewall of the second opening exposes the second sacrificial layer 152.
The first sacrificial layer 151 of the first region I is etched using a second etching process including one or a combination of two of dry etching and wet etching. The dummy gate layer 140 of the first region I is etched using a third etching process including wet etching. The second sacrificial layer 152 forms a sidewall barrier of the dummy gate layer 140 of the second region II, and prevents the first electrode layer of the first region from invading the second region and ensures the continuity of the sidewall of the subsequently deposited first diffusion barrier when the subsequent second opening forms the first gate structure.
Referring to fig. 11, a first gate structure (not shown) is formed in the second opening, and a top surface of the first gate structure is level with a surface of the first sacrificial layer 151.
The first gate structure includes a first diffusion barrier layer 170 located at the sidewall and bottom of the second opening, a first work function layer 171 located on the first diffusion barrier layer 170, and a first electrode layer 172 located on the first work function layer 171. In this embodiment, the material of the first diffusion barrier layer 170 includes one or more of hafnium oxide (HfO 2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), etc., the material of the first work function layer 171 is one or more of Ti, ta, tiN, taN, tiAl, taC, taSiN, and the material of the first electrode layer 172 is one or more of Al, cu, ag, au, pt, ni. The first diffusion barrier layer 170 is used to block diffusion of the material of the first electrode layer 172. The work function of the first gate structure may be changed by adjusting the material and thickness of the first work function layer 171.
Referring to fig. 12, the second sacrificial layer 152 and the first sacrificial layer 151 of the second region II are removed.
The second sacrificial layer 152 and the first sacrificial layer 151 of the second region II are removed using a fourth etching process including one or a combination of two of wet etching and dry etching. In the embodiment of the present invention, the materials of the first sacrificial layer 151 and the second sacrificial layer 152 are the same, so the fourth etching process is adopted to remove the second sacrificial layer 152 and the first sacrificial layer 151 of the second region II simultaneously, and in order to avoid etching residues in the actual process, wet etching is firstly adopted to remove the second sacrificial layer 152 and the first sacrificial layer 151 of the second region II, and then further etching is performed, so that the second sacrificial layer 152 and the first sacrificial layer 151 can be completely removed. In another embodiment, the second sacrificial layer 152 is removed by wet etching, and then the first sacrificial layer 151 of the second region II is removed by wet etching.
Referring to fig. 13, the dummy gate layer 140 of the second region II is etched to form a third opening (not shown), and a sidewall of the third opening exposes a sidewall of the first gate structure 161.
The process of etching the dummy gate layer 140 of the second region II includes one or a combination of two of a dry etching process and a wet etching process. In this embodiment, the dummy gate layer 140 of the second region II is wet etched using a tetramethylammonium hydroxide (TMAH) solution to form a third opening.
Referring to fig. 14, a second gate structure is formed in the third opening, the second gate structure is adjacent to the first gate structure, and a top surface of the second gate structure is level with a top surface of the first gate structure.
The second gate structure includes a second diffusion barrier layer 180 located at the sidewall and bottom of the third opening, a second work function layer 181 located on the second diffusion barrier layer 180, and a second electrode layer 182 located on the second work function layer 181. In this embodiment, the material of the second diffusion barrier layer 180 includes one or more of hafnium oxide (HfO 2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), etc., the material of the first work function layer 181 is one or more of Ti, ta, tiN, taN, tiAl, taC, taSiN, and the material of the second electrode layer 182 is one or more of Al, cu, ag, au, pt, ni. The second diffusion barrier 180 is used to block diffusion of the material of the first electrode layer 182. The work function of the first gate structure may be changed by adjusting the material and thickness of the second work function layer 181.
Compared with the prior art, the invention provides a preparation method of a metal gate device, which is characterized in that a first opening is formed in a pseudo gate layer of a second region, and an extension line of a side wall of the first opening is aligned with a crossing line of the first region and the second region; forming a first sacrificial layer on the dummy gate layer and a second sacrificial layer filling the first opening; etching the first sacrificial layer and the dummy gate layer of the first region to form a second opening, wherein the side wall of the second opening exposes the second sacrificial layer; forming a first gate structure in the second opening, wherein the top surface of the first gate structure is flush with the surface of the first sacrificial layer; removing the second sacrificial layer and the first sacrificial layer of the second region; etching the pseudo gate layer of the second region to form a third opening, wherein the side wall of the third opening exposes the side wall of the first gate structure; a second gate structure is formed within the third opening, the second gate structure being adjacent to the first gate structure, and a top surface of the second gate structure being level with a top surface of the first gate structure.
According to the invention, the second sacrificial layer is formed at the junction of the first region and the second region and is used as the side wall barrier layer, so that in the process of removing the pseudo gate layer of the first region by adopting the wet etching process, the formation of etching defects on the side wall of the pseudo gate layer of the second region caused by isotropic etching is avoided, and meanwhile, the damage of the dry etching process to the gate dielectric layer is avoided because of adopting the wet etching process. In addition, after the second sacrificial layer is removed, the side wall of the pseudo gate layer of the second region is steep, the first electrode layer of the first region is prevented from invading the second region, the continuity of the side wall of the subsequently deposited first diffusion barrier layer is ensured, the purpose of improving the performance and the reliability of the device is achieved, and the method has obvious significance.
The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the equivalent structures of the present invention described in the specification and the drawings are included in the scope of the invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
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