CN112560372B - Chip prototype verification method, device, equipment and medium - Google Patents
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Abstract
The application discloses a chip prototype verification method, a device, equipment and a medium, comprising the following steps: acquiring configuration information of a test case, wherein the configuration information comprises a register name; register address information corresponding to the register name is obtained by utilizing the register name and a preset mapping relation; accessing a register of a design to be tested by using the register address information, and configuring based on the configuration information so as to execute the test case on the design to be tested; acquiring an actual execution result of the test case on the design to be tested; determining an expected execution result by using a preset prediction model and the configuration information; and comparing the actual execution result with the expected execution result, and judging whether the test case passes or not. Therefore, the requirements for verifying reusability and maintainability can be met, and the verification cost is reduced.
Description
Technical Field
The present application relates to the field of chip verification technologies, and in particular, to a method, an apparatus, a device, and a medium for verifying a chip prototype.
Background
As the complexity of large scale integrated circuit design increases, chip verification faces a significant capital and time challenge. After a hardware manufacturer releases a Field Programmable Gate Array (FPGA), a developer can verify a design by implementing the design on the FPGA and checking functions of the FPGA, and the solution of the FPGA prototype verification is brought forward. By using the solution of the FPGA prototype verification, a chip and system developer can perform function and performance verification on the design before tape-out, and verify whether the chip and system performance under the real software application condition meets the requirements of an actual application scene. Because the FPGA has the characteristic that an internal circuit is reconfigurable, the logic design of a chip can be mapped on the FPGA with little cost. Meanwhile, the running speed of the FPGA prototype verification is usually a great advantage of several orders of magnitude compared with the speed of the EDA simulation, and the FPGA prototype verification has outstanding advantages in the aspects of performance test, reliability test and the like because the inherent characteristics of the FPGA allow the design to run on the FPGA for a long time.
Currently, FPGA prototyping has been the mainstream method of current prototyping. However, in the field of chip prototype verification, due to the diversity of various chip test scenarios, the flexibility of chip test means and the complexity of chip functions, in the engineering practice of building verification environments for different types of chips and even different test scenarios of the same chip, prototype verification engineers often use various different methods to realize verification environments and meet verification requirements, and an automated verification software framework with better performance in reusability and maintainability is lacking.
Disclosure of Invention
In view of this, an object of the present application is to provide a method, an apparatus, a device and a medium for verifying a chip prototype, which can meet the requirements of verifying reusability and maintainability, thereby reducing verification cost. The specific scheme is as follows:
in a first aspect, the present application discloses a chip prototype verification method, including:
acquiring configuration information of a test case, wherein the configuration information comprises a register name;
acquiring register address information corresponding to the register name by using the register name and a preset mapping relation;
accessing a register of a design to be tested by using the register address information, and configuring based on the configuration information so as to execute the test case on the design to be tested;
acquiring an actual execution result of the test case on the design to be tested;
determining an expected execution result by utilizing a preset prediction model and the configuration information;
and comparing the actual execution result with the expected execution result, and judging whether the test case passes or not.
Optionally, the method further includes:
and analyzing the register form of the chip, extracting the register name and the register address information, and constructing the preset mapping relation.
Optionally, the obtaining an actual execution result of the test case on the design to be tested includes:
and reading the result of the state latch register of the design to be tested based on a first preset data structure to obtain the actual execution result.
Optionally, the determining an expected execution result by using the preset prediction model and the configuration information includes:
and outputting a corresponding execution result by using the prediction model and the configuration information, and converting the execution result into a second preset data structure to obtain the expected execution result.
Optionally, the comparing the actual execution result with the expected execution result, and determining whether the test case passes or not, includes:
and traversing the first preset data structure and the second data structure, comparing the actual execution result with the expected execution result, and judging whether the test case passes or not.
Optionally, the method further includes:
and in the execution process of the test case, automatically collecting the coverage condition of the test point in the test case.
Optionally, in the execution process of the test case, automatically collecting the coverage condition of the test point in the test case includes:
setting a test point dictionary, wherein the test point dictionary comprises preset value ranges corresponding to the test points;
when configuration is carried out based on the configuration information, a register configuration value in the configuration information is used for matching with the test point dictionary, if a value consistent with the register configuration value is matched in the preset value field, test point coverage information in the test point dictionary is updated, and/or the actual execution result corresponding to the test point passing the test in the test case is used for matching with the test point dictionary, so that the test point coverage information is updated.
In a second aspect, the present application discloses a chip prototype verification apparatus, comprising:
the test case testing system comprises a configuration information acquisition module, a test case testing module and a test case testing module, wherein the configuration information acquisition module is used for acquiring configuration information of a test case, and the configuration information comprises a register name;
the register address acquisition module is used for acquiring register address information corresponding to the register name by using the register name and a preset mapping relation;
the design to be tested configuration module is used for accessing a register of the design to be tested by utilizing the register address information and configuring based on the configuration information so as to execute the test case on the design to be tested;
the actual execution result acquisition module is used for acquiring the actual execution result of the test case on the design to be tested;
the expected execution result determining module is used for determining an expected execution result by utilizing a preset prediction model and the configuration information;
and the execution result checking module is used for comparing the actual execution result with the expected execution result and judging whether the test case passes or not.
In a third aspect, the present application discloses an electronic device, comprising:
a memory for storing a computer program;
and the processor is used for executing the computer program to realize the chip prototype verification method.
In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program, which when executed by a processor implements the chip prototype verification method described above.
It can be seen that the configuration information of test case is obtained to this application, wherein, configuration information includes the register name, then utilizes register name and preset mapping relation obtain the register address information that the register name corresponds, later utilize register address information visits the register of the design that awaits measuring, based on configuration information configures in order to be in the design that awaits measuring is gone up and is executed the test case, then obtains the test case is in actual execution result on the design that awaits measuring to utilize predetermine predictive model and configuration information confirm expected execution result, compare at last actual execution result with expected execution result, judge whether the test case passes through. That is, according to the method and the device, the corresponding register address is obtained by using the register name and the preset mapping relation instead of directly using the register address for access, so that the problems of low verification reusability and maintainability caused by register address change in the iterative process of the chip are solved, the requirements of verification reusability and maintainability can be met, and the verification cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only the embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flow chart of a chip prototype verification method disclosed in the present application;
FIG. 2 is a flow chart of a specific chip prototype verification method disclosed herein;
FIG. 3 is a schematic diagram of a specific chip prototype verification apparatus according to the present disclosure;
FIG. 4 is a schematic diagram of a specific chip verification platform disclosed herein;
fig. 5 is a block diagram of an electronic device disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Currently, FPGA prototype verification is the mainstream method of prototype verification. However, in the field of chip prototype verification, due to the diversity of various chip test scenarios, the flexibility of chip test means and the complexity of chip functions, in the engineering practice of building verification environments for different types of chips and even different test scenarios of the same chip, prototype verification engineers often use various different methods to realize verification environments and meet verification requirements, and an automated verification software framework with better performance in reusability and maintainability is lacking. Therefore, the chip prototype verification scheme can meet the requirements of verifying reusability and maintainability, and therefore verification cost is reduced.
Referring to fig. 1, an embodiment of the present application discloses a chip prototype verification method, including:
step S11: acquiring configuration information of a test case, wherein the configuration information comprises a register name.
Step S12: and acquiring register address information corresponding to the register name by using the register name and a preset mapping relation.
In a specific implementation manner, the register form of the chip may be analyzed, register name and register address information are extracted, and the preset mapping relationship is constructed. The register address information comprises a base address and an offset address of a register.
Specifically, the present embodiment may construct a preset register dictionary data structure to construct the preset mapping relationship, where the preset register dictionary data structure includes information such as a register name, a base address, an offset address, a name of each bit field in the register, and a position of each bit field in the register. As shown below, a specific diagram of a preset register dictionary data structure disclosed in this embodiment is shown.
It should be noted that, in the process of iterating the chip version, the register address usually changes, but the register name does not change, and since the register form of the chip item is written according to a fixed rule, this embodiment can extract information such as the name, the base address, the offset address, the name of each bit field in the register, and the position of each bit field in the register by analyzing the writing rule of the register form. The specific development process can use Python language, and in order to conveniently extract various information in the register form, an openpyxl open source library is used.
Step S13: accessing a register of a design under test with the register address information, and performing configuration based on the configuration information to execute the test case on the Design Under Test (DUT).
It should be noted that, based on the mapping relationship between the register name and the register address, the register address information corresponding to the register name may be determined, and then, based on the register address information, an API interface provided by the prototype verification underlying system and accessing the register according to the register absolute address is called to access the actual register corresponding to the register name. The absolute address of the register is the base address and the offset address of the register.
The flow of writing each bit field of the register is as follows: (1) an incoming register name, a bit field name, a write value; (2) searching information such as bit width, base address, offset address and the like of the bit field in a preset register dictionary data structure; (3) calling API by using base address and offset address to read back and store the value of the register; (4) the value of the written bit field is combined with the values of the other bit fields in the saved register, and then the underlying API is called again to rewrite the values in the register. The flow of reading each bit field of the register is as follows: (1) transmitting a register name and a bit field name; (2) searching information such as bit width, base address, offset address and the like of the bit field in a preset register dictionary data structure; (3) calling API by using base address and offset address to read back and store the value of the register; (4) and separating the corresponding value of the bit field from the register value according to the position of the bit field.
That is, in this embodiment, the configuration information register name, the bit field name, and the configuration value are write values. In a specific implementation manner, register address information including a base address and an offset address is found by using the register name and the preset register dictionary data structure, a corresponding API interface is called based on the register address information to access a register corresponding to the register name, and a configuration value is written into the register. Specifically, the register value of the register is read, the configuration value is combined with the values of the other bit fields in the register to obtain a new value, and then the new value is written into the register.
Step S14: and acquiring an actual execution result of the test case on the design to be tested.
In a specific embodiment, the result of the state latch register of the design to be tested may be read based on a first preset data structure to obtain the actual execution result.
It should be noted that after the test case configuration flow is executed, the result of the status latch register of the DUT needs to be read, and whether the reported result meets expectations is determined, and at this time, a reusable and easily maintainable batch read register reporting result is needed. Therefore, all the reporting information that needs to be concerned can be represented by defining a data structure, and the first preset data structure, that is, the reporting information dictionary, can be as follows:
in a specific embodiment, after the state extraction mechanism is triggered, the data structure may be traversed to extract the register name and the bit domain name, and all the concerned state reporting results may be obtained by using the register access method, and the state results are marked back to the report _ value entry of the reported information dictionary.
Step S15: and determining an expected execution result by using a preset prediction model and the configuration information.
In a specific embodiment, the predicted model and the configuration information may be utilized to output a corresponding execution result, and the execution result may be converted into a second preset data structure to obtain the expected execution result. The specific structure is as follows:
step S16: and comparing the actual execution result with the expected execution result, and judging whether the test case passes or not.
In a specific embodiment, the first preset data structure and the second data structure are traversed, the actual execution result and the expected execution result are compared, and whether the test case passes or not is judged.
It should be noted that the names and the numbers of reporting points in the expected execution result and the actual execution result are completely consistent, and the difference between the expected execution result and the actual execution result is that the reporting point of the expected execution result contains an expected value item, and the reporting point of the actual execution result contains a reporting value item. The embodiment may use the preset check code to automatically traverse the expected value and the actual value in the two data structures and determine whether the expected value and the actual value are consistent, and report the difference between the expected response and the actual DUT response to determine whether the use case passes, and the partial code is as follows:
it should be noted that the present embodiment improves the reusability and maintainability of the verification component by defining the data structure format of the expected response and the actual response.
It can be seen that, the configuration information of the test case is obtained in the embodiment of the present application, wherein the configuration information includes a register name, then the register name and a preset mapping relation are used to obtain register address information corresponding to the register name, then the register address information is used to access a register of a design to be tested, the configuration is performed based on the configuration information, so that the test case is executed on the design to be tested, then the actual execution result of the test case on the design to be tested is obtained, a preset prediction model is used, an expected execution result is determined according to the configuration information, and finally the actual execution result is compared with the expected execution result to judge whether the test case passes or not. That is, according to the method and the device, the corresponding register address is obtained by using the register name and the preset mapping relation instead of directly using the register address for access, so that the problems of low verification reusability and maintainability caused by register address change in the iterative process of the chip are solved, the requirements of verification reusability and maintainability can be met, and the verification cost is reduced.
Referring to fig. 2, the embodiment of the present application discloses a specific chip prototype verification method, which includes:
step S21: acquiring configuration information of a test case, wherein the configuration information comprises a register name.
Step S22: and acquiring register address information corresponding to the register name by using the register name and a preset mapping relation.
Step S23: and accessing a register of the design to be tested by utilizing the register address information, and configuring based on the configuration information so as to execute the test case on the design to be tested.
Step S24: and acquiring an actual execution result of the test case on the design to be tested.
Step S25: and determining an expected execution result by using a preset prediction model and the configuration information.
Step S26: and comparing the actual execution result with the expected execution result, and judging whether the test case passes or not.
Step S27: and automatically collecting the coverage condition of the test points in the test case in the execution process of the test case.
In a specific implementation manner, a test point dictionary may be set, where the test point dictionary includes preset value ranges corresponding to the test points; when configuration is carried out based on the configuration information, a register configuration value in the configuration information is used for matching with the test point dictionary, if a value consistent with the register configuration value is matched in the preset value field, test point coverage information in the test point dictionary is updated, and/or the actual execution result corresponding to the test point passing the test in the test case is used for matching with the test point dictionary, so that the test point coverage information is updated.
Specifically, the test point dictionary comprises register names, bit domain names and preset value ranges corresponding to the test points, and the initialization stage comprises the steps of updating the test point coverage information in the test point dictionary, wherein the uncovered value range in the test point dictionary is the preset value range, and the covered value range in the test point dictionary is empty.
Specifically, the test point may be associated with each bit field in the register according to a defined function test point, and the test point may be stored by using a dictionary data structure of Python, where the test point dictionary may be as follows:
in the above example, the value range to be covered by each functional test point is defined, the value range of the currently covered test point is initialized to be empty, and the value range of the currently uncovered test point is initialized to be the same as the value range to be covered. The test point dictionary in the above example is traversed synchronously each time the register name and register bit domain name configuration is used, if the configuration value of the accessed bit field is found to match a certain defined function test point in the dictionary, the state of the dictionary is updated, the configuration value is added to the covered value item of the corresponding test point, and the value is removed from the uncovered value item. In this way, after a certain test case is executed and passes, the states of all concerned test points are updated to the result of the execution of the test case. Every time the test case is executed, the test case is updated according to the content configured by the current case on the basis of the coverage condition after the previous case is executed. After all the test cases are executed, the final coverage condition is reported to measure the achievement condition of the verification target.
Referring to fig. 3, an embodiment of the present application discloses a chip prototype verification apparatus, including:
the configuration information acquiring module 11 is configured to acquire configuration information of a test case, where the configuration information includes a register name;
a register address obtaining module 12, configured to obtain, by using the register name and a preset mapping relationship, register address information corresponding to the register name;
a design to be tested configuration module 13, configured to access a register of the design to be tested by using the register address information, and perform configuration based on the configuration information, so as to execute the test case on the design to be tested;
an actual execution result obtaining module 14, configured to obtain an actual execution result of the test case on the design to be tested;
an expected execution result determining module 15, configured to determine an expected execution result by using a preset prediction model and the configuration information;
and the execution result checking module 16 is configured to compare the actual execution result with the expected execution result, and determine whether the test case passes through.
It can be seen that the configuration information of the test case is obtained in the embodiment of the present application, wherein the configuration information includes a register name, and then the register name and the preset mapping relation are used to obtain the register address information corresponding to the register name, and then the register address information is used to access the register of the design to be tested, and the configuration is performed based on the configuration information, so that the test case is executed on the design to be tested, and then the test case is obtained on the actual execution result on the design to be tested, and the preset prediction model and the configuration information are used to determine the expected execution result, and finally the actual execution result and the expected execution result are compared to judge whether the test case passes or not. That is, in the embodiment of the present application, the register address corresponding to the register name and the preset mapping relationship is obtained, instead of directly accessing the register address, so that the problems of low verification reusability and low maintainability caused by register address change in the chip iteration process are solved, the requirements for verification reusability and maintainability can be met, and the verification cost is reduced.
The device also comprises a mapping relation construction module which is used for analyzing the register form of the chip, extracting the register name and the register address information and constructing the preset mapping relation.
The actual execution result obtaining module 14 is specifically configured to read a result of the state latch register of the design to be tested based on a first preset data structure, so as to obtain the actual execution result.
The expected execution result determining module 15 is specifically configured to output a corresponding execution result by using the prediction model and the configuration information, and convert the execution result into a second preset data structure to obtain the expected execution result.
Correspondingly, the execution result checking module 16 is specifically configured to traverse the first preset data structure and the second data structure, compare the actual execution result with the expected execution result, and determine whether the test case passes through.
The device also comprises a test coverage condition collection module which is used for automatically collecting the coverage condition of the test points in the test case in the execution process of the test case.
In a specific embodiment, the test coverage condition collection module is specifically configured to set a test point dictionary, where the test point dictionary includes preset value ranges corresponding to the test points; when configuration is carried out based on the configuration information, a register configuration value in the configuration information is used for matching with the test point dictionary, if a value consistent with the register configuration value is matched in the preset value field, test point coverage information in the test point dictionary is updated, and/or the actual execution result corresponding to the test point passing the test in the test case is used for matching with the test point dictionary, so that the test point coverage information is updated.
For example, referring to fig. 4, fig. 4 is a schematic structural diagram of a specific chip verification platform disclosed in this embodiment. Specifically, the test case may be developed based on Python language, and the configuration information of the test case is first obtained, and then sent to the control plane driver, the control plane driver accesses the register of the DUT to perform configuration related to the test scenario, and at the same time, the configuration information is sent to the prediction model to generate an expected result. After the test scenario execution is complete, the values of the status registers are automatically retrieved from the DUT based on the defined information, while the expected results are converted into the defined data structure. Finally, the difference between the expected DUT response and the actual DUT response is compared in the checker to determine if the use case passes. Therefore, the execution process of the prototype verification case is abstracted into four stages of excitation, expected response generation, design response extraction to be tested and inspection, automatic methods are provided for each test stage, and after a verification engineer develops a prototype verification environment based on the methods, the test excitation can be automatically applied, the design response extraction to be tested, the design response inspection to be tested and the judgment of whether the test case passes or not can be automatically carried out. Meanwhile, when the interfaces of different modules are defined, the interfaces of the verification assembly are standardized by specifying the data structure transmitted by the interfaces, the reusability and the expandability are improved, and the interfaces of different projects and different modules of the projects can be conveniently reused.
Referring to fig. 5, an embodiment of the present application discloses an electronic device, which includes a processor 21 and a memory 22; wherein, the memory 22 is used for saving computer programs; the processor 21 is configured to execute the computer program to implement the chip prototype verification method disclosed in the foregoing embodiments.
For the specific process of the chip prototype verification method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.
Further, the present application also discloses a computer-readable storage medium for storing a computer program, wherein the computer program is executed by a processor to implement the chip prototype verification method disclosed in the foregoing embodiments.
For the specific process of the chip prototype verification method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The method, the apparatus, the device and the medium for verifying the prototype of the chip provided by the present application are introduced in detail, and a specific example is applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A method for verifying a chip prototype, comprising:
acquiring configuration information of a test case, wherein the configuration information comprises a register name;
register address information corresponding to the register name is obtained by utilizing the register name and a preset mapping relation;
accessing a register of a design to be tested by utilizing the register address information, and configuring based on the configuration information so as to execute the test case on the design to be tested;
acquiring an actual execution result of the test case on the design to be tested;
determining an expected execution result by utilizing a preset prediction model and the configuration information;
and comparing the actual execution result with the expected execution result, and judging whether the test case passes or not.
2. The chip prototype verification method according to claim 1, further comprising:
and analyzing the register form of the chip, extracting the register name and the register address information, and constructing the preset mapping relation.
3. The chip prototype verification method according to claim 1, wherein the obtaining of the actual execution result of the test case on the design under test comprises:
and reading the result of the state latch register of the design to be tested based on a first preset data structure to obtain the actual execution result.
4. The chip prototype verification method according to claim 3, wherein the determining an expected execution result using a preset prediction model and the configuration information comprises:
and outputting a corresponding execution result by using the prediction model and the configuration information, and converting the execution result into a second preset data structure to obtain the expected execution result.
5. The chip prototype verification method according to claim 4, wherein the comparing the actual execution result with the expected execution result to determine whether the test case passes comprises:
and traversing the first preset data structure and the second preset data structure, comparing the actual execution result with the expected execution result, and judging whether the test case passes or not.
6. The chip prototype verification method according to any one of claims 1 to 5, further comprising:
and automatically collecting the coverage condition of the test points in the test case in the execution process of the test case.
7. The chip prototype verification method according to claim 6, wherein automatically collecting coverage of test points in the test case during the execution of the test case comprises:
setting a test point dictionary, wherein the test point dictionary comprises preset value ranges corresponding to the test points;
when configuration is carried out based on the configuration information, a register configuration value in the configuration information is used for matching with the test point dictionary, if a value consistent with the register configuration value is matched in the preset value field, test point coverage information in the test point dictionary is updated, and/or the actual execution result corresponding to the test point passing the test in the test case is used for matching with the test point dictionary, so that the test point coverage information is updated.
8. A chip prototype verification apparatus, comprising:
the device comprises a configuration information acquisition module, a test case configuration module and a test case configuration module, wherein the configuration information acquisition module is used for acquiring the configuration information of a test case, and the configuration information comprises a register name;
the register address acquisition module is used for acquiring register address information corresponding to the register name by using the register name and a preset mapping relation;
the design to be tested configuration module is used for accessing a register of the design to be tested by utilizing the register address information and configuring based on the configuration information so as to execute the test case on the design to be tested;
the actual execution result acquisition module is used for acquiring the actual execution result of the test case on the design to be tested;
the expected execution result determining module is used for determining an expected execution result by utilizing a preset prediction model and the configuration information;
and the execution result checking module is used for comparing the actual execution result with the expected execution result and judging whether the test case passes or not.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the chip prototype verification method according to any one of claims 1 to 7.
10. A computer-readable storage medium for storing a computer program which, when executed by a processor, implements the chip prototype verification method according to any one of claims 1 to 7.
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| CN202011357846.2A CN112560372B (en) | 2020-11-27 | 2020-11-27 | Chip prototype verification method, device, equipment and medium |
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| CN202011357846.2A CN112560372B (en) | 2020-11-27 | 2020-11-27 | Chip prototype verification method, device, equipment and medium |
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| CN113806234A (en) * | 2021-10-11 | 2021-12-17 | 芯河半导体科技(无锡)有限公司 | Chip register extraction and test method |
| CN118228649B (en) * | 2024-05-23 | 2024-08-06 | 深圳鲲云信息科技有限公司 | Method and device for verifying test completeness of chip, electronic equipment and storage medium |
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