CN112559429B - System and method for monitoring data based on USB - Google Patents

Abstract

The invention relates to a system and a method for monitoring data based on USB, belonging to the technical field of electronics and communication. Under the condition of not interfering the data flow between the original USB master and slave devices, the invention extracts the signal on the USB data differential line directly from the middle lead of the USB bus connected with the master and slave devices; the differential signal is received through a special USB2.0 PHY chip, restored into a level signal, further converted into parallel data and sent to an FPGA; and the specially designed FPGA internal logic circuit analyzes and processes the data packet, and the master-slave equipment after unpacking and integrating transmits data and outputs the data through an 8-bit parallel bus. According to the invention, the USB PHY is used for non-invasively intercepting signals and the FPGA is used for processing data packets, so that data transmitted between the USB master device and the USB slave device can be directly output through the parallel IO port without other special equipment (such as a PC).

Description

A USB data listening system and method

Technical field

The invention relates to a USB data interception system and method, which belongs to the field of electronics and communication technology. In particular, it provides a method for real-time processing of intercepted image data based on a microcontroller, CPLD or FPGA backplane.

Background technique

With the continuous development and popularization of digital products, data exchanges between devices have become more frequent and high-speed, and the USB protocol has become one of the mainstream protocols for data transmission between various devices. Devices that support the USB protocol are not only common in our daily lives, but also very common in scientific research. For example, various external detection devices, instruments, telescopes, various signal analyzers, etc. are all equipped with USB-compliant devices. Standard interface. The USB bus is one of the common external bus standards and is used for data exchange and communication between the host and the device in the USB bus model. The USB interface has become one of the mainstream trends in modern data transmission due to its advantages of high speed, stability, plug-and-play, unified interface specifications, and ease of use. There are three USB interface standards: USB 1.1, USB 2.0 and USB 3.0. Although there are many devices with USB 3.0 interfaces, the market share of USB 2.0 devices is currently higher than 3.0.

USB is a convenient, point-to-point data transmission method, but this protocol does not support data transmission between three devices. If you need to implement real-time listening and collection functions of data on the USB 2.0 bus, you need to develop a specific device or system to complete this task. USB protocol analyzers currently on the market can realize computer-based data monitoring and analysis functions. In a few documents, the intercepted data is finally uploaded to the PC. However, the monitoring and collection of real-time sending and receiving data of the USB interface implemented through software on the computer does not have good portability and versatility. Different computers require multiple configurations and debugging; and it is separated from the assistance of the host computer software. will not work properly. Currently, there is no system that listens and collects data in both directions on the USB 2.0 bus in real time, processes and combines it into a USB transaction and sends it to the backplane circuit for use by the backplane circuit.

Contents of the invention

The technical problem to be solved by the present invention is: the present invention provides a USB data listening system and method. The system uses a USB interface chip to listen to bus bidirectional data, and uses FPGA to combine the data into USB transactions and send them to the backplane circuit.

The technical solution of the present invention is: a USB data listening system, including an FPGA module 1, a USB interface chip module 2, an IO expansion port module 3, a USB interface A11, and a USB interface B12;

The USB interface chip module 2 connects the master device 9 and the slave device 10 non-invasively through the USB bus of USB interface A11 and USB interface B12; the USB interface chip module 2 is also connected to the FPGA module 1, and the FPGA module 1 includes a ULPI interface module 4. Packet decomposition module 5, transaction combination module 6, transmission module 7, clock module 8; clock module 8 is respectively connected with USB interface chip module 2, ULPI interface module 4, packet decomposition module 5, transaction combination module 6, and transmission module 7 Connection; the IO expansion port module 3 is connected to the transmission module 7 of the FPGA module 1; the IO expansion port module 3 is connected to the baseboard circuit.

As a further solution of the present invention, the ULPI interface module 4 is a ULPI PHY interface module, which establishes protocol layer contact with the USB interface chip module 2, and outputs complete data to the packet decomposition module 5; the packet decomposition module 5 is used to decompose the USB The data packet is cached in RAM, and the packet information is stored in the FIFO cache; the transaction combination module 6 is used for USB transaction processing, combining several associated token packets, data packets, and handshake packets into a USB transaction and providing the EN signal ; The clock module 8 is input by the USB interface chip module 2 and controls the clocks of the ULPI interface module 4, packet decomposition module 5, transaction combination module 6, and transmission module 7; the transmission module 7 is used to provide the combined USB transactions to the base board The circuit's synchronous clock and EN signal combination is output to the backplane circuit through IO expansion port module 3. When the EN signal is high, one byte in the USB transaction will be output in each synchronous clock cycle.

A USB data listening method, the method includes:

The USB interface chip module 2 non-intrusively intercepts the signals between the master device 9 and the slave device 10 through the USB bus of the USB interface A11 and the USB interface B12 and sends it to the FPGA module 1 for processing. The FPGA module 1 combines the processed data into A USB transaction is output from IO expansion port module 3 to the backplane circuit; the backplane circuit filters the required data for use based on the header file of the transaction.

As a further solution of the present invention, when each USB transaction is output, the first 4 bytes are the transaction information header, and the 4-byte transaction information header format is:

The first byte: tid[7:0], indicating the type of transaction;

The second byte: addr[6:0], indicating the device address corresponding to the transaction;

The third byte: the lower 4 bits are ep[3:0], indicating the endpoint number corresponding to the transaction, and the upper 4 bits are len[3:0];

The fourth byte: len[11:4], len[11:0] indicates the data length corresponding to the transaction;

Followed by 0 to 1024 bytes of transaction data.

The working principle of the present invention is:

Based on the USB data listening system and method, the baseboard 5V power supply is used. Since each module uses different voltages, 2-way AMS1117 low-voltage drop linear power supply chips are used to generate 3.3V and 1.2V respectively for overall use.

The USB interface A11 is used to connect the master device 9 that performs USB communication, and the USB interface B12 is used to connect the slave device 10 that performs USB communication. The DM and DP of the two USB interfaces are directly connected to the USB interface chip module 2, and a 1kΩ protection resistor is added to connect to the FPGA; VBUS is connected to the FPGA module 1 with a 100kΩ resistor, and a 100kΩ pull-down resistor is added.

The chip used in the USB interface chip module 2 is USB3300 encapsulated based on UTMI+ level 3 and the interface is the ULPI interface; ULPI uses 12 pins to connect the complete OTG host/device PHY to the system-level chip. An 8-bit bidirectional data bus, clocked at 60MHz, allows FPGA module 1 to access this internal register array and transmit USB packets to the physical layer. The remaining 3 pins are used to control data flow and arbitrate the data bus. The direction of the 8-bit data bus is controlled by the DIR output of ULPI interface module 4. The other output, NXT, is used to control the flow of data to and from the device. Finally, the STP input to ULPI interface module 4 terminates the transfer and is used to initiate and resume from the suspend state.

The USB3300 uses an internal crystal driver and phase-locked loop subsystem to provide a noise-free, stable 480MHz reference clock that is used by the PHY during transmit and receive. The USB3300 requires a stable, noise-free 24MHz crystal or clock as a frequency reference. The USB3300 can use a crystal or an external clock oscillator as the 24MHz reference. The crystal is connected to the USB3300 pins. Once the 480MHz phase locked loop is locked to the correct frequency, it drives the CLKOUT pin with the 60MHz clock. The chip's ULPI interface signal level is 3.3V. Works in high-speed 480Mbps speed mode.

DIR is Direction, used to control the transmission direction of the data bus; when the USB interface chip transmits data to the FPGA, the driver DIR is high; when there is no data transmission, the driver is low and monitors the control signal on the FPGA side; at the same time, the USB interface chip will Drive DIR high when data cannot be received. NXT is Next. The USB interface chip will control this signal when transmitting data; when the FPGA sends data to the USB interface chip, the USB interface chip will immediately pull NXT high when receiving the data; then the FPGA will send the next word in the next clock cycle. The program is put on the data bus; correspondingly, when the USB interface chip is sending data to the FPGA, NXT means that there are new bytes of data to be sent to the FPGA at this time. STP means Stop. When the FPGA sets STP valid, it stops the current data flow on the bus within one clock cycle; if the FPGA is transmitting data to the USB interface chip, STP will remain the last bit of data in each data packet.

The ULPI interface supports two basic operating modes: synchronous mode and low power mode. Synchronous mode, all signals vary relative to the 60MHz clock. In low-power mode, the clock is turned off in the pause state, and the next two bits of the data bus contain the line status [1:0] signal. ULPI adds a low-power mode, an interrupt output that allows the link to receive asynchronous interrupts when the OTG comparator or ID pin changes state. In synchronous mode, data is transferred on the rising edge of CLKOUT. The direction of the data bus is determined by the state of DIR. When DIR is high, the PHY is driving Data[7:0]. When DIR is low, the link is driving data[7:0]. Because USB uses bit-stuffing encoding, some method is needed to allow the PHY to limit the data transferred over USB. The ULPI signal NXT is used to request the link layer to place the next byte on the data bus. When the link addresses the PHY, a single ULPI protocol block decodes the ULPI 8-bit bidirectional bus. The link must use the DIR output to determine the direction of the ULPI data bus. USB3300 is the "bus arbitrator". The ULPI protocol block routes data/commands to the transmitter or the ULPI register array.

The USB interface chip module 2 restores the data differential signal to a level signal and needs to decode the NRZI code stream, and then identify the stuffing bits. The data is converted into data with a bit width of 8 bits and sent to the FPGA module 1 through D0~D7 of the USB interface chip module 2.

The core chip used in the FPGA module 1 is the XC6SLX9-2TQG144C chip of Xilinx's Spartan6 series, which is connected to the FPGA chip with the FPGA peripheral circuit. For example, the FPGA configuration chip SPI-Flash is used to store the FPGA configuration bit stream; the power supply circuit mainly provides the required +5V, +3.3V and +1.2V voltages to the FPGA chip and SPI-Flash; the clock uses the USB interface chip module 2 output The 60MHz clock serves as the system clock of the module. Two indicator lights are configured. The LED_1 power supply lights up the red indicator light to remind the power supply to be turned on. LED_2 transaction indicator light, every time a valid USB transaction is output, the blue indicator light lights up once. One end of the FPGA module 1 is connected to the IO expansion port module 3, and the other end is connected to the USB interface chip module 2. Connect this device to the baseboard, and after powering on the baseboard, the baseboard provides 5V voltage and reset signal. The ULPI interface module 4 in the FPGA module 1 writes the initial control command TX CMD to the register of the USB interface chip module 2. The USB interface A11 is connected to the master device 9 that performs USB communication, and the USB interface B12 is used to connect the slave device 10 that performs USB communication. The USB interface chip module 2 begins to listen to the differential circuit on the bus, and restores the differential signal into a level signal and transmits it to the FPGA module 1. The ULPI interface module 4 is a ULPI PHY interface module, establishes protocol layer contact with the USB interface chip module 2, and outputs complete data to the packet decomposition module 5. The packet decomposition module 5 caches the USB data packets into RAM and stores the packet information in the FIFO for cache. The transaction combination module 6 is used for USB transaction processing, combining several associated token packets, data packets, and handshake packets into a USB transaction and providing the EN signal; the clock module 8 is input by the USB interface chip module 2 and uses the basic clock The management module (DCM) is closely integrated with the global clock distribution network inside the FPGA, which can be used to divide and multiply frequencies, eliminate clock delay differences, and control the ULPI interface module 4, packet decomposition module 5, transaction combination module 6, and transmission module 7 clock and output the clock signal. The phase of the output clock signal can be adjusted to optimize the timing of the signal output to the backplane. The transmission module 7 is used to output the combined USB transaction, the synchronization clock and the EN signal provided to the backplane to the backplane through the IO expansion port module 3. When the EN signal is high, there will be one byte for each synchronization clock cycle. USB transaction output.

The working process of the present invention is:

Connect this device to the baseboard, and after powering on the baseboard, the baseboard provides 5V voltage and reset signal. Use 2-way LDO low-voltage drop linear power supply chips to generate 3.3V and 1.2V voltages for device use. After reset, the ULPI interface module 4 in the FPGA module 1 writes the initial control command TX CMD to the register of the USB interface chip module 2. To write to the register, ULPI interface module 4 in FPGA module 1 waits until DIR is low and, on the first clock cycle, drives TXD CMD on the data bus. In the third clock cycle, USB interface chip module 2 will drive NXT high. On the next rising clock edge, ULPI interface module 4 will write the register data. In the fifth clock cycle, the USB interface chip module 2 will accept the register data, and the ULPI interface module 4 will drive idle on the bus and drive STP high to send the signal of the end of the data packet. Finally, in the sixth clock cycle, USB interface chip module 2 will latch the data into the register and drive NXT low. ULPI interface module 4 will pull STP low. NXT is used to control when ULPI interface module 4 drives register data on the bus. Since the USB interface chip module 2 receives data from the ULPI interface module 4, DIR is low during the entire transaction. STP is used to end the transaction, and the data is registered after STP is low. After the write operation is completed, the ULPI interface module 4 must drive ULPI idle 00h on the data bus, otherwise the USB interface chip module 2 can decode the bus value into an ULPI command.

The USB interface A11 is connected to the master device 9 for USB communication, and the USB interface B12 is connected to the slave device 10 for USB communication. The USB interface chip module 2 begins to listen to the differential circuit on the bus, and restores the differential signal into a level signal and transmits it to the FPGA. During transmission, the USB interface chip module 2 will use NXT to control the data flow rate entering the USB interface chip module 2. If the USB interface chip module 2 pipe is full or bit stuffing causes the data pipe to be overfilled, NXT is invalid (low level), and ULPI interface module 4 will retain the value on the data until NXT is valid (high level). When STP is valid and NXT is invalid in ULPI interface module 4, USB transmission ends. Since USB interface chip module 2 expects to get another byte from ULPI interface module 4 in this state, ULPI interface module 4 cannot have an STP valid signal with NXT invalid,

Once the USB interface chip module 2 completes the transmission, the DP/DM line returns to the idle state and the RXD CMD returns to the link so that the internal packet timing can be updated through the line status.

At full speed or low speed, once STP is active, each FS/LS bit transition will generate an RXD CMD because the bit time is relatively slow.

The USB interface chip module 2 asserts DIR so that the USB interface chip module 2 controls the data bus from the ULPI interface module 4 . The validity of DIR and NXT in the same cycle contains additional information about the validity of Rxactive. When NXT is invalid and DIR is valid, RXD CMD data is transmitted to FPGA module 1. After the last byte of the USB received data packet is transmitted to the USB interface chip module 2, the line status will return to the idle state.

ULPI full speed receiver operates according to UTMI/ULPI specifications. At full speed, the NXT signal will only be valid when the data bus has valid receive data bytes. When NXT is low and DIR is high, the RXD command is driven on the data bus.

At full speed, USB interface chip module 2 will not send an Rxactive invalid signal in RXDCMD before the DP/DM line state transitions to the idle state. This prevents FPGA module 1 from violating the minimum change time of two full-speed bit times.

When the ULPI interface module 4 transmits the packet start signal to the packet decomposition module 5, the 8-bit parallel data is stored in the 8-bit wide RAM. Each time a byte is stored, the length of the packet can be obtained by counting once. Store the first three groups of 8-bit data into three registers with a width of 8. When a complete packet transmission is completed, the information of each packet is combined into one data and stored in the FIFO cache. If the length of the packet is three and the first group of data is the PID (packet identification field) of the token packet, it is judged that the packet is a token packet, and the first three groups of 8-bit data saved in the register are stored in a width of 64 bits The first 24 bits in the FIFO are cached. The first 1 to 8 bits are the PID of this packet, the 9 to 15 bits are the device address, the 16 to 19 bits are the endpoint data of the device, and the remaining 5 bits are the CRC check bits. If the length of the packet is greater than 3 and the first set of data is the PID of the data packet, the packet is judged to be a data packet. Save the first set of data (PID) to bits 1 to 8 in the 64-bit FIFO; reduce the length of this packet by three (removing the one-byte PID and two-byte CRC check bits) to obtain the length of this packet data. length) is saved to 25 to 36 bits in the 64-bit FIFO; add one to the first address of this data packet in RAM (the first byte is the PID, the second byte from the second byte onwards is the data of this packet, and the last two Bytes are the CRC of this packet) and are saved to bits 37~48 in the 64-bit FIFO. If the length of the packet is one and the first set of data is the PID of the handshake packet, it is judged that the packet is a handshake packet, and the first set of data (PID) is saved to the first bit of the 64-bit FIFO. The purpose of storing these data in the FIFO cache is to facilitate subsequent processing by the transaction combination module 6.

In the transaction combination module 6, after the data of the previous transaction is processed and transmitted to the backplane, if there is data in the FIFO, the first 8 bits of the 64-bit data in the FIFO are judged, and the first 8 bits are the PID (Packet Identification Code) . If it is the PID of the token packet, put the PID data into the token packet PID register, put the address in the 64-bit data into the address register, and put the endpoint data into the endpoint register. If it is the PID of the data packet, put the PID data into the data packet PID register, put the data length in the 64-bit data into the data length register, and put the address of the data in RAM into the data RAM address register. If it is the PID of the handshake packet, put the PID data into the handshake packet PID register. According to the three PID registers, it is possible to determine what transaction is transmitted this time, and name this transaction into a corresponding 8-bit transaction identifier (TID) code, and combine the address, endpoint, and length of this transaction into A transaction header. The transmission module 7 is used to output the combined USB transaction, the synchronous clock and the EN signal provided to the base plate to the base plate through the IO expansion port module 3. When the EN signal is high, the USB transaction will be output in each synchronous clock cycle. A byte of , the first 4 bytes are the transaction information header, and the 4-byte transaction information header format is:

The first byte: tid[7:0], indicating the type of transaction;

The second byte: addr[6:0], indicating the device address corresponding to the transaction;

The third byte: the lower 4 bits are ep[3:0], indicating the endpoint number corresponding to the transaction, and the upper 4 bits are len[3:0];

The fourth byte: len[11:4], len[11:0] indicates the data length corresponding to the transaction;

This is followed by the corresponding length of transaction data read through the data RAM address register. And clear the address, endpoint, PID and other registers to zero.

After the data is output to the base plate, the base plate can filter the required information based on the header information. This design is specially used to filter image information.

The beneficial effects of the present invention are:

1. When image data is communicated from a USB master-slave device, if the data needs to be analyzed, processed, or temporarily stored based on a microcontroller, CPLD or FPGA backplane, this system can be connected to the backplane system. It eliminates the need to transfer the circuit from the PC to the backplane, which increases the speed and reduces the waste of manpower.

2. The present invention can perform non-intrusive real-time listening of USB data on the USB bus after connecting to the USB transmission line without using a PC and transmit it to the base board for use.

3. The equipment of the present invention is simple and easy to use, has low cost, is small in area and easy to carry, and has strong practicability.

4. The present invention can also listen to other data, and only needs to be slightly modified in the code.

5. The present invention integrates several packages into one transaction, discards useless data, and classifies all transactions. The backplane circuit can clearly obtain the type of the transaction, the device address corresponding to the transaction, and the endpoint number corresponding to the transaction. , the data length corresponding to the transaction. The baseboard circuit can obtain the data you want based on these conditions, and easily get the results you want.

Description of the drawings

Figure 1 is a functional block diagram of the present invention;

Figure 2 is a circuit diagram for bidirectional communication of DATA data from the USB interface chip of the present invention to the FPGA chip;

Figure 3 is a flow chart of data transmission of the packet decomposition module and transaction combination module of the present invention;

Figure 4 is a base board receiving state machine that transmits to the base board according to the present invention.

Each label in Figure 1: 1-FPGA module, 2-USB interface chip module, 3-IO expansion port module, 4-ULPI interface module, 5-packet decomposition module, 6-transaction combination module, 7-transmission module, 8- Clock module, 9-master device, 10-slave device, 11-USB interface A, 12-USB interface B.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

Embodiment 1: As shown in Figure 1-4, a USB data listening system includes FPGA module 1, USB interface chip module 2, IO expansion port module 3, USB interface A11, and USB interface B12;

The USB interface chip module 2 connects the master device 9 and the slave device 10 non-invasively through the USB bus of USB interface A11 and USB interface B12; the USB interface chip module 2 is also connected to the FPGA module 1, and the FPGA module 1 includes a ULPI interface module 4. Packet decomposition module 5, transaction combination module 6, transmission module 7, clock module 8; clock module 8 is respectively connected with USB interface chip module 2, ULPI interface module 4, packet decomposition module 5, transaction combination module 6, and transmission module 7 Connection; the IO expansion port module 3 is connected to the transmission module 7 of the FPGA module 1; the IO expansion port module 3 is connected to the baseboard circuit.

As a further solution of the present invention, the ULPI interface module 4 is a ULPI PHY interface module, which establishes protocol layer contact with the USB interface chip module 2, and outputs complete data to the packet decomposition module 5; the packet decomposition module 5 is used to decompose the USB The data packet is cached in RAM, and the packet information is stored in the FIFO cache; the transaction combination module 6 is used for USB transaction processing, combining several associated token packets, data packets, and handshake packets into a USB transaction and providing the EN signal ; The clock module 8 is input by the USB interface chip module 2 and controls the clocks of the ULPI interface module 4, packet decomposition module 5, transaction combination module 6, and transmission module 7; the transmission module 7 is used to provide the combined USB transactions to the base board The circuit's synchronous clock and EN signal combination is output to the backplane circuit through IO expansion port module 3. When the EN signal is high, one byte in the USB transaction will be output in each synchronous clock cycle.

A USB data listening method, the method includes:

The USB interface chip module 2 non-intrusively intercepts the signals between the master device 9 and the slave device 10 through the USB bus of the USB interface A11 and the USB interface B12 and sends it to the FPGA module 1 for processing. The FPGA module 1 combines the processed data into A USB transaction is output from IO expansion port module 3 to the backplane circuit; the backplane circuit filters the required data for use based on the header file of the transaction.

As a further solution of the present invention, when each USB transaction is output, the first 4 bytes are the transaction information header, and the 4-byte transaction information header format is:

The first byte: tid[7:0], indicating the type of transaction;

The second byte: addr[6:0], indicating the device address corresponding to the transaction;

The third byte: the lower 4 bits are ep[3:0], indicating the endpoint number corresponding to the transaction, and the upper 4 bits are len[3:0];

The fourth byte: len[11:4], len[11:0] indicates the data length corresponding to the transaction;

Followed by 0 to 1024 bytes of transaction data.

Specifically, FPGA module 1 is connected to USB interface chip module 2 and IO expansion port module 3 through different I/O ports. The data transmission between FPGA module 1, USB interface chip module 2 and IO expansion port module 3 is realized by data lines D0~D7 with a bit width of 8 bits. DIR is Direction, which is used to control the transmission direction of the data bus; when the USB interface chip module 2 transmits data to the FPGA module 1, the driver DIR is high; when there is no data transmission, the driver is low and monitors the control signal of the FPGA module 1; at the same time , USB interface chip module 2 will drive DIR high when it cannot receive data. NXT is Next. USB interface chip module 2 will control this signal when transmitting data; when FPGA module 1 sends data to USB interface chip module 2, USB interface chip module 2 will immediately pull NXT high when receiving the data; then FPGA module 1 The next byte will be put on the data bus in the next clock cycle; correspondingly, when USB interface chip module 2 is sending data to FPGA module 1, NXT means that there is a new byte of data to be sent to FPGA module 1 at this time. STP means Stop. When FPGA module 1 sets STP valid, it stops the current data flow on the bus within one clock cycle; if FPGA module 1 is transmitting data to USB interface chip module 2, STP will remain as the last bit of each data packet. One bit of data.

As shown in Figure 1, USB interface A11 is a USB port used to connect the master device 9, USB interface B12 is another USB port used to connect the slave device 10, pull up the middle leads of the USB buses of the two interfaces from the differential pair Two wires are drawn out so that the signal can flow out directly, so that the original connection can be restored and the purpose of not interfering with the original transmission line can be achieved at the hardware level.

As shown in Figure 1, the USB interface chip module 2 non-invasively intercepts the signals between the master device 9 and the slave device 10 through the USB bus of the USB interface A11 and the USB interface B12 and sends it to the FPGA module 1 for processing. The FPGA module 1 will process The completed data is combined into a USB transaction and sent from IO expansion port module 3 to the backplane circuit. The backplane circuit can be used to filter the required data based on the transaction header file.

The circuit diagram shown in Figure 2 solves the main difficulty and realizes the two-way communication of DATA data from the USB interface chip module 2 to the FPGA module 1. Where MUX is the data selector and BUFT is the three-state output buffer. When DIR is high, the three-state output buffer is in a high-impedance state; the data selector turns on DATA and DATA_IN. It is realized that when the USB interface chip module 2 transmits data to the FPGA module 1, the DIR is driven high, and the FPGA module 1 starts to receive the data transmitted from the USB interface chip module 2. The tri-state output buffer transfers DATA_OUT data to DATA when DIR is low. When there is no data transmission, the USB interface chip module 2 drives DIR low and monitors the control signal of the FPGA module 1, so that the FPGA module 1 can write commands into the register of the USB interface chip module 2.

As shown in Figure 1, FPGA module 1 includes: ULPI interface module 4, packet decomposition module 5, transaction combination module 6, transmission module 7, clock module 8; ULPI interface module 4 is a ULPI PHY interface module, and USB interface chip module 2 Establish the connection at the protocol layer, and output the complete data to the packet decomposition module 5; the packet decomposition module 5 caches the USB data packets to RAM, and stores the packet information in the FIFO cache; the transaction combination module 6 is used for USB transaction processing, Several associated token packets, data packets, and handshake packets are combined into a USB transaction and provide the EN signal; the clock module 8 is input by the USB interface chip module 2 and controls the ULPI interface module 4, packet decomposition module 5, and transaction combination module 6. The clock of the transmission module 7; the transmission module 7 is used to output the combined USB transaction, the synchronization clock and the EN signal provided to the base plate to the base plate through the IO expansion port module 3. When the EN signal is high, each synchronization One clock cycle will output a byte in the USB transaction.

As shown in Figure 3, when the ULPI interface module 4 transmits the packet start signal to the packet decomposition module 5, the 8-bit parallel data is stored in the 8-bit wide RAM. When a complete packet transmission is completed, the PID, endpoint , the device address information, data packet length and location in RAM form data with a bit width of 64 and are stored in the 64-bit wide FIFO cache. When no data is transmitted to the backplane, the data in the FIFO is processed. When a transaction transmission is complete, the PIDs of several packets are integrated into the TID of a transaction, the CRC is discarded, and then the information of several packets is integrated into a transaction packet information header.

As shown in Figure 1, the USB interface chip module 2 needs to write the USB protocol into the USB3300 chip so that it can restore the differential signal to a level signal and translate it into a signal that conforms to the ULPI protocol, and then convert the data through the ULPI protocol. The data with a bit width of 8 bits is transferred to the FPGA for processing. And transmit the CLK signal into the FPGA.

As shown in Figure 1, the IO expansion port module 3 is connected to the transmission module 7 of the FPGA module 1; the IO expansion port module 3 outputs the clock signal to the base board to synchronize the base board clock; it outputs the transaction valid signal EN and the USB transaction to the base board.

As shown in Figure 4, it is the baseboard receiving state machine of the present invention that transmits to the baseboard. When each USB transaction is output, when EN is valid, the transaction package will be output in sequence. The first 4 bytes are the transaction information header, and the 4-byte transaction information header format is:

The first byte: tid[7:0], indicating the type of transaction;

The second byte: addr[6:0], indicating the device address corresponding to the transaction;

The third byte: the lower 4 bits are ep[3:0], indicating the endpoint number corresponding to the transaction, and the upper 4 bits are len[3:0];

The fourth byte: len[11:4], len[11:0] indicates the data length corresponding to the transaction;

Followed by 0 to 1024 bytes of transaction data.

After the backplane is powered on, it enters the initial state (IDLE). When the enable signal EN is 1 and the previous clock EN is 0, that is, when a USB transaction is transmitted from the system to the backplane, the first eight-bit data is received. header and enter the HEADER_1 state. The HEADER_1 state EN is 1 to receive the second eight-bit data header and enter the HEADER_2 state. The HEADER_2 state EN is 1 to receive the third eight-bit data header and enter the HEADER_3 state. HEADER_3 state EN is 1 to receive the information header of the fourth eight-bit data and enter the DATA state. In the DATA state, as long as EN is 1, data will continue to be passed down until EN is 0, returning to the initial state machine (IDLE). The backplane can filter the required data based on this state machine and information header constraints.

The specific embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the above-mentioned embodiments. Within the scope of knowledge possessed by those of ordinary skill in the art, other modifications can be made without departing from the purport of the present invention. Various changes.

Claims (2)

1. A USB data listening system, characterized by: including FPGA module (1), USB interface chip module (2), IO expansion port module (3), USB interface A (11), USB interface B (12 ); The USB interface chip module (2) connects the master device (9) and the slave device (10) without intrusion through the USB bus of USB interface A (11) and USB interface B (12); the USB interface chip module (2) It is also connected to the FPGA module (1). The FPGA module (1) includes the ULPI interface module (4), packet decomposition module (5), transaction combination module (6), transmission module (7), and clock module (8); clock module (8) are respectively connected to the USB interface chip module (2), ULPI interface module (4), packet decomposition module (5), transaction combination module (6), and transmission module (7); the IO expansion port module (3) ) is connected to the transmission module (7) of the FPGA module (1); the IO expansion port module (3) is connected to the baseboard circuit; The ULPI interface module (4) is a ULPI PHY interface module, establishes protocol layer contact with the USB interface chip module (2), and outputs complete data to the packet decomposition module (5); the packet decomposition module (5) is used to The USB data packet is cached in RAM, and the packet information is stored in the FIFO cache; the transaction combination module (6) is used for USB transaction processing, combining several associated token packets, data packets, and handshake packets into a USB transaction and Provides the EN signal; the clock module (8) is input by the USB interface chip module (2) and controls the clocks of the ULPI interface module (4), packet decomposition module (5), transaction combination module (6), and transmission module (7); The transmission module (7) is used to output the combined USB transaction, the synchronous clock and the EN signal provided to the backplane circuit to the backplane circuit through the IO expansion port module (3). When the EN signal is high, each synchronization clock cycle One byte in the USB transaction will be output. 2. A USB data listening method, characterized in that the method includes: The USB interface chip module (2) non-invasively intercepts the signals between the master device (9) and the slave device (10) through the USB bus of USB interface A (11) and USB interface B (12) and sends them to the FPGA module (1 ) processing, the FPGA module (1) combines the processed data into a USB transaction and outputs it from the IO expansion port module (3) to the backplane circuit; the backplane circuit filters the required data according to the header file of the transaction for use; When each USB transaction is output, the first 4 bytes are the transaction information header, and the 4-byte transaction information header format is: The first byte: tid[7:0], indicating the type of transaction; The second byte: addr[6:0], indicating the device address corresponding to the transaction; The third byte: the lower 4 bits are ep[3:0], indicating the endpoint number corresponding to the transaction, and the upper 4 bits are len[3:0]; The fourth byte: len[11:4], len[11:0] indicates the data length corresponding to the transaction; Followed by 0 to 1024 bytes of transaction data.