CN112543561B - Manufacturing method of circuit board with cavity structure - Google Patents
Manufacturing method of circuit board with cavity structure Download PDFInfo
- Publication number
- CN112543561B CN112543561B CN201910901196.4A CN201910901196A CN112543561B CN 112543561 B CN112543561 B CN 112543561B CN 201910901196 A CN201910901196 A CN 201910901196A CN 112543561 B CN112543561 B CN 112543561B
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- peelable film
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- circuit
- circuit board
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims description 144
- 239000004743 Polypropylene Substances 0.000 claims description 19
- 229920001155 polypropylene Polymers 0.000 claims description 19
- -1 polypropylene Polymers 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 2
- 239000000428 dust Substances 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 9
- 239000004721 Polyphenylene oxide Substances 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 229920000139 polyethylene terephthalate Polymers 0.000 description 6
- 239000005020 polyethylene terephthalate Substances 0.000 description 6
- 229920006380 polyphenylene oxide Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000003292 glue Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 239000011112 polyethylene naphthalate Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 230000037303 wrinkles Effects 0.000 description 3
- 239000000047 product Substances 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention provides a manufacturing method of a circuit board with a cavity structure, which comprises the following steps: providing a first circuit substrate, and sequentially forming a first peelable film, a second peelable film and a third peelable film on the first circuit substrate, wherein the viscosity of the third peelable film is greater than that of the second peelable film; and peeling the second peelable film and the third peelable film, thereby obtaining the circuit board with the cavity structure. The manufacturing method provided by the invention can prevent crease marks and dust pollution in the insulating layer slotting process, improve the dimensional precision of the cavity and improve the quality of the circuit board.
Description
Technical Field
The invention relates to the technical field of high-density interconnected printed circuit boards, in particular to a manufacturing method of a high-density interconnected circuit board with a cavity structure.
Background
A High Density Interconnect (HDI) circuit board is a circuit board with a relatively high line distribution density fabricated using micro-blind buried via technology, which helps to miniaturize the design of the end product while having higher electronic performance and efficiency. In order to further realize the miniaturization development of electronic products, match the three-dimensional assembly requirements of electronic elements and improve the overall space utilization rate of the products, the prior art generally carries out shape design such as a local cavity, a ladder or a groove body on an HDI circuit board. In the manufacturing process of the cavity, a polypropylene film with a pre-groove is pressed on a circuit substrate, then another circuit substrate is covered, and the groove is opened on the covered circuit substrate, so as to form the cavity. However, the polypropylene film pre-grooving process is prone to crease, dust pollution and other problems, and reduces the dimensional accuracy of the chamber. Moreover, the bottom of the cavity is prone to generate glue overflow when the polypropylene film is pressed, and the quality of the circuit board is affected.
Disclosure of Invention
In view of this, the present invention provides a method for manufacturing a circuit board with a cavity structure, which can prevent the insulating layer from generating creases and dust pollution during the slotting process, improve the dimensional accuracy of the cavity, and improve the quality of the circuit board.
The invention provides a method for manufacturing a circuit board with a cavity structure, which comprises the following steps:
providing a first circuit substrate, wherein the first circuit substrate comprises a first insulating layer and a first conductive circuit layer formed on one surface of the first insulating layer, and the first conductive circuit layer is provided with a window used for exposing part of the first insulating layer;
forming a first peelable film in the fenestration, wherein a first gap is formed between the side wall of the first peelable film and the edge of the fenestration;
adding at least one second circuit substrate on the first conductive circuit layer with the first peelable film, wherein each second circuit substrate comprises a second insulating layer and a second conductive circuit layer, the second insulating layer is formed between the second conductive circuit layer and the first conductive circuit layer, the second conductive circuit layer is provided with a second gap corresponding to the first gap, and the part of the second circuit substrate corresponding to the first peelable film is an area to be removed;
cutting the second circuit substrate along the second gap and the first gap to form a first cut, and separating the region to be removed and the first peelable film from the first circuit substrate;
attaching a second peelable film to the second circuit substrate so that the second peelable film covers at least the region to be removed of the second circuit substrate, wherein the second peelable film has an opening for exposing a part of the region to be removed;
attaching a third peelable film to the second peelable film such that the third peelable film fills the opening and adheres to the area to be removed, wherein the third peelable film has a greater tackiness than the second peelable film and the first peelable film; and
and peeling the third peelable film, the second peelable film, the area to be removed and the first peelable film which are bonded with the third peelable film and the second peelable film to form a cavity, so as to obtain the circuit board with the cavity structure.
The third peelable film is a high-viscosity peeling film, and the third peelable film is adhered to the second conductive circuit layer. The first peelable film and the second peelable film can enable the bottom surface of the cavity (namely, the first insulating layer) and the circuit board with the cavity structure to have good flatness, so that the bottom surface of the cavity in the finally manufactured high-density interconnection circuit board is parallel to a plane of the second conductive circuit line layer facing to the outermost surface of the circuit board with the cavity structure. And before adding the second insulating layer, the second insulating layer does not need to be subjected to pre-grooving treatment, so that the problems of wrinkles, pollution and the like generated in the process of pre-grooving the second insulating layer are avoided, and the dimensional accuracy of the cavity is improved.
Drawings
Fig. 1 is a schematic structural diagram of a first circuit substrate according to a preferred embodiment of the invention.
Fig. 2 is a schematic structural view of the first conductive trace layer shown in fig. 1 after windowing, attaching an initial peelable film, and cutting.
Fig. 3 is a schematic structural diagram of the structure of fig. 2 after the initial peelable film on the first conductive trace layer is peeled off.
Fig. 4 is a schematic structural diagram of the second circuit substrate and the third circuit substrate respectively added on the first conductive trace layer and the fifth conductive trace layer shown in fig. 3.
Fig. 5 is a schematic structural diagram of the second conductive trace layer and the sixth conductive trace layer shown in fig. 4 after surface treatment is performed to form a first solder mask layer and a second solder mask layer, respectively.
Fig. 6 is a schematic structural view of the second circuit board shown in fig. 5 after being cut.
Fig. 7 is a schematic structural view of the second circuit substrate shown in fig. 6 after a second peelable film is bonded thereto.
Fig. 8 is a schematic view of the structure of the second peelable film shown in fig. 7 after a third peelable film is attached thereto.
Fig. 9 is a schematic structural diagram of the circuit board with a cavity structure obtained after the third peelable film, the second peelable film, the area to be removed and the first peelable film which are adhered to the third peelable film and the second peelable film shown in fig. 8 are peeled off.
Description of the main elements
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
To further explain the technical means and effects of the present invention adopted to achieve the intended purpose, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.
The preferred embodiment of the invention provides a method for manufacturing an interconnection circuit board with a cavity structure, which comprises the following steps:
s11, please refer to fig. 1, a first circuit board 10 is provided.
The first circuit substrate 10 includes a first insulating layer 101 and a first conductive trace layer 102 formed on one surface of the first insulating layer 101. The first conductive trace layer 102 has a window 11 for exposing a portion of the first insulating layer 101. In this embodiment, the first circuit substrate 10 further includes a third conductive trace layer 103, a base layer 104, a fourth conductive trace layer 105, a third insulating layer 106, and a fifth conductive trace layer 107 sequentially stacked on the other surface of the first insulating layer 101.
Of course, in other embodiments, the number of conductive line layers in the first circuit board 10 may be changed according to actual circumstances.
The material of the first insulating layer 101, the base layer 104, and the third insulating layer 106 may be one selected from epoxy resin (epoxy resin), polypropylene (PP), BT resin, Polyphenylene Oxide (PPO), polypropylene (PP), Polyimide (PI), Polyethylene Terephthalate (PET), and Polyethylene Naphthalate (PEN). In this embodiment, the first insulating layer 101 and the third insulating layer 106 are made of polypropylene. The base layer 104 is made of polyimide.
At least one first conductive via 12 is formed in the first insulating layer 101, and the first conductive via 12 is used for electrically connecting the first conductive trace layer 102 and the third conductive trace layer 103. At least one second conductive through hole 13 is formed in the base layer 104, and the second conductive through hole 13 is used for electrically connecting the third conductive circuit layer 103 and the fourth conductive circuit layer 105. At least one third conductive via 14 is formed in the third insulating layer 106, and the third conductive via 14 is used for electrically connecting the fourth conductive trace layer 105 and the fifth conductive trace layer 107.
S12, referring to fig. 2, an initial peelable film 20 is formed on the first conductive trace layer 102 and in the window 11.
Wherein the initial peelable film 20 formed in the window 11 is bonded to the first insulating layer 101.
S13, cutting the initial peelable film 20 along the edge of the fenestration 11 to form a second cut 23.
In this embodiment, the cutting is UV cutting, i.e. ultraviolet cutting. In other embodiments, the cutting may also be die cutting.
S14, referring to fig. 3, the initial peelable film 20 on the first conductive trace layer 102 is peeled off, so as to form the first peelable film 22 in the window 11, and a first gap 21 is formed between a sidewall of the first peelable film 22 and an edge of the window 11.
Wherein the first peelable film 22 is a low viscosity release film. The adhesive force of the first peelable film 22 is 10 to 90g/25 mm. The first peelable film 22 is used to protect the first insulating layer 101 and ensure the flatness of the first insulating layer 101 during the subsequent peeling process.
Defining the thickness of the first peelable film 22 as a, the thickness of the first conductive trace layer 102 as b, and a and b satisfy the following relationship: the | a-b | is less than or equal to 10 microns. In the present embodiment, the thickness of the first peelable film 22 is the same as the thickness of the first conductive trace layer 102, that is, a — b.
S15, referring to fig. 4, at least one second circuit substrate 30 is added on the first conductive trace layer 102 having the first peelable film 22.
Each of the second circuit substrates 30 includes a second insulating layer 301 and a second conductive trace layer 302, wherein the second insulating layer 301 is formed between the second conductive trace layer 302 and the first conductive trace layer 102. The second conductive trace layer 302 has a second gap (not shown) corresponding to the first gap 21. A portion of the second wiring substrate 30 corresponding to the first peelable film 22 is a region to be removed 31. At least one fourth conductive via 32 is disposed in the second insulating layer 301, and the fourth conductive via 32 is used for electrically connecting the second conductive trace layer 302 and the first conductive trace layer 102.
The material of the second insulating layer 301 may be one of epoxy resin (epoxy resin), polypropylene (PP), BT resin, Polyphenylene Oxide (PPO), polypropylene (PP), Polyimide (PI), Polyethylene Terephthalate (PET), Polyethylene Naphthalate (PEN), and the like. In this embodiment, the second insulating layer 301 is made of polypropylene.
S16, adding a third circuit substrate 40 on the fifth conductive trace layer 107.
The third circuit substrate 40 includes a fourth insulating layer 401 and a sixth conductive trace layer 402, and the fourth insulating layer 401 is formed between the sixth conductive trace layer 402 and the fifth conductive trace layer 107. At least one fifth conductive via 41 is disposed in the fourth insulating layer 401, and the fifth conductive via 41 is used for electrically connecting the sixth conductive trace layer 402 and the fifth conductive trace layer 107.
The material of the fourth insulating layer 401 may be one of epoxy resin (epoxy resin), polypropylene (PP), BT resin, Polyphenylene Oxide (PPO), polypropylene (PP), Polyimide (PI), Polyethylene Terephthalate (PET), Polyethylene Naphthalate (PEN), and the like. In this embodiment, the fourth insulating layer 401 is made of polypropylene.
S17, referring to fig. 5, a first solder mask layer 50 and a second solder mask layer 51 are formed on the second conductive trace layer 302 except the region 31 to be removed and the sixth conductive trace layer 402, respectively.
Wherein the first solder mask layer 50 does not cover the region to be removed 31. The first solder mask layer 50 and the second solder mask layer 51 can be made of solder mask ink, such as green oil.
S18, referring to fig. 6, the second circuit substrate 30 is cut along the second gap and the first gap 21 to form a first cut 52, so that the region to be removed 31 and the first peelable film 22 are separated from the first circuit substrate 10.
S19, please refer to fig. 7, a second peelable film 60 is attached to the second circuit substrate 30, so that the second peelable film 60 at least covers the region to be removed 31 of the second circuit substrate 30.
Wherein the second peelable film 60 has an opening 601, and the opening 601 is used for exposing a part of the region to be removed 31. The second peelable film 60 is a low viscosity release film. The adhesive force of the second peelable film 60 is 10 to 90g/25 mm. The second peelable film 60 is used to protect the first solder mask layer 50 and ensure the flatness of the first solder mask layer 50 during the subsequent peeling process. The second peelable film 60 also covers the area of the second wiring substrate 30 other than the area to be removed 31.
S20, please refer to fig. 8, a third peelable film 61 is attached to the second peelable film 60, so that the third peelable film 61 is filled in the opening 601 and is adhered to the region to be removed 31.
Specifically, the third peelable film 61 is adhered to the second conductive trace layer 302 through the opening 601. The third peelable film 61 has a greater adhesiveness than the second peelable film 60 and the first peelable film 22. The third peelable film 61 is a high-viscosity peeling film. The adhesive force of the third peelable film 61 is 600 to 3000g/25 mm. The third peelable film 61 includes an adhesive layer 611 and a protective layer 612 formed on the adhesive layer, and the adhesive layer 611 is used for adhering the region to be removed 31.
The first peelable film 22, the second peelable film 60, and the third peelable film 61 each include a peelable glue (not shown) and a Polyimide (PI) film (not shown) formed on the peelable glue. The adhesive force of the first peelable film 22, the second peelable film 60, and the third peelable film 61 is dependent on the adhesive force of the peelable glue. The thickness of the polyimide film is generally 7.5 μm, 12.5 μm, 25.0 μm and 50.0 μm, and the thickness of the peelable glue is generally 10 μm, 15 μm, 20 μm and 25 μm. S21, referring to fig. 9, the third peelable film 61, the second peelable film 60, the region to be removed 31 adhered thereto, and the first peelable film 22 are peeled off to form a cavity 62, thereby obtaining the interconnect board 100 with a cavity structure.
Since the third peelable film 61 of high adhesiveness adheres the area to be removed 31, the area to be removed 31 can be removed (i.e., a decapping process) while peeling off the third peelable film 61.
The cavity 62 penetrates the second conductive trace layer 302, the second insulating layer 301, and the first conductive trace layer 102.
Since the third peelable film 61 is a high-viscosity peeling film, and the third peelable film 61 is adhered to the second conductive trace layer 302, the present invention can remove the region to be removed 31 by using the high viscosity of the third peelable film 61. The first peelable film 22 and the second peelable film 60 can make the bottom surface of the cavity 62 (i.e., the first insulating layer 101) and the cavity structure wiring board 100 have good flatness, so that the bottom surface of the cavity 62 in the cavity structure wiring board 100 finally prepared is parallel to the plane of the second conductive circuit layer 302 facing the outermost surface of the cavity structure wiring board 100. Moreover, before the second insulating layer 301 is added, the second insulating layer 301 does not need to be subjected to pre-grooving treatment, so that the problems of wrinkles, pollution and the like generated in the pre-grooving process of the second insulating layer 301 are avoided, and the dimensional accuracy of the cavity 62 is improved, and according to the invention, the thickness of the second circuit substrate 30 and the difference value between the first peelable film 22 and the first conductive circuit layer 102 are controlled, so that no step difference exists in the inner conductive circuit of the circuit board 100 with the cavity structure, and the cavity 62 with extremely high depth and accuracy is obtained.
According to the invention, the first peelable film 22, the second peelable film 60 and the third peelable film 61 are attached to avoid the problems of insulating layer pre-opening wrinkle pollution and insulating layer gummosis, so that the manufacturing efficiency of the circuit board 100 with the cavity structure is improved, and the flatness is improved.
The above description is only an optimized embodiment of the present invention, but the present invention is not limited to this embodiment in practical application. Other modifications and changes to the technical idea of the present invention should be made by those skilled in the art within the scope of the claims of the present invention.
Claims (10)
1. A manufacturing method of a circuit board with a cavity structure is characterized by comprising the following steps:
providing a first circuit substrate, wherein the first circuit substrate comprises a first insulating layer and a first conductive circuit layer formed on one surface of the first insulating layer, and the first conductive circuit layer is provided with a window used for exposing part of the first insulating layer;
forming a first peelable film in the fenestration, wherein a first gap is formed between the side wall of the first peelable film and the edge of the fenestration;
adding at least one second circuit substrate on the first conductive circuit layer with the first peelable film, wherein each second circuit substrate comprises a second insulating layer and a second conductive circuit layer, the second insulating layer is formed between the second conductive circuit layer and the first conductive circuit layer, the second conductive circuit layer is provided with a second gap corresponding to the first gap, and the part of the second circuit substrate corresponding to the first peelable film is an area to be removed;
cutting the second circuit substrate along the second gap and the first gap to form a first cut, and separating the region to be removed and the first peelable film from the first circuit substrate;
attaching a second peelable film to the second circuit substrate so that the second peelable film covers at least the region to be removed of the second circuit substrate, wherein the second peelable film has an opening for exposing a part of the region to be removed;
attaching a third peelable film to the second peelable film such that the third peelable film fills the opening and adheres to the area to be removed, wherein the third peelable film has a greater tackiness than the second peelable film and the first peelable film; and
and peeling the third peelable film, the second peelable film, the area to be removed and the first peelable film which are bonded with the third peelable film and the second peelable film to form a cavity, so as to obtain the circuit board with the cavity structure.
2. The method for manufacturing a circuit board with a cavity structure according to claim 1, wherein the forming of the first peelable film in the window includes:
forming an initial peelable film on the first conductive circuit layer, wherein the initial peelable film is also filled in the windowing;
cutting the initial peelable film along an edge of the fenestration to form a second cut, thereby forming the first peelable film in the fenestration and having a sidewall of the first peelable film forming the first gap with the edge of the fenestration; and
peeling off the initial peelable film on the first conductive line layer.
3. The method for manufacturing a circuit board with a cavity structure according to claim 1, wherein before the second peelable film is attached, the method further comprises:
forming a first solder mask layer on the second conductive circuit layer except the region to be removed;
wherein the second peelable film further covers an area of the second wiring substrate other than the area to be removed.
4. The method for manufacturing a circuit board with a cavity structure according to claim 1, wherein the third peelable film comprises an adhesive layer and a protective layer formed on the adhesive layer, and the adhesive layer is used for bonding the region to be removed.
5. The method for manufacturing a circuit board with a cavity structure according to claim 1, wherein the first insulating layer and the second insulating layer are made of polypropylene.
6. The method for manufacturing the circuit board with the cavity structure according to claim 1, wherein the adhesive force of the first peelable film and the adhesive force of the second peelable film are 10 to 90g/25mm, and the adhesive force of the third peelable film is 600 to 3000g/25 mm.
7. The method for manufacturing a circuit board with a cavity structure according to claim 1, wherein a thickness of the first peelable film is defined as a, a thickness of the first conductive trace layer is defined as b, and a and b satisfy the following relationship: the | a-b | is less than or equal to 10 microns.
8. The method according to claim 1, wherein the first circuit board further includes a third conductive trace layer, a base layer, a fourth conductive trace layer, a third insulating layer, and a fifth conductive trace layer sequentially stacked on another surface of the first insulating layer, and the first conductive trace layer, the second conductive trace layer, the third conductive trace layer, the fourth conductive trace layer, and the fifth conductive trace layer are electrically connected to each other.
9. The method for manufacturing a circuit board with a cavity structure according to claim 8, further comprising:
and adding a third circuit substrate on the fifth conductive circuit layer, wherein the third circuit substrate comprises a fourth insulating layer and a sixth conductive circuit layer, and the fourth insulating layer is formed between the sixth conductive circuit layer and the fifth conductive circuit layer.
10. The method for manufacturing a circuit board with a cavity structure according to claim 9, further comprising:
and a second solder mask layer is formed on the sixth conductive circuit layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910901196.4A CN112543561B (en) | 2019-09-23 | 2019-09-23 | Manufacturing method of circuit board with cavity structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910901196.4A CN112543561B (en) | 2019-09-23 | 2019-09-23 | Manufacturing method of circuit board with cavity structure |
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| Publication Number | Publication Date |
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| CN112543561A CN112543561A (en) | 2021-03-23 |
| CN112543561B true CN112543561B (en) | 2021-11-16 |
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| CN201910901196.4A Active CN112543561B (en) | 2019-09-23 | 2019-09-23 | Manufacturing method of circuit board with cavity structure |
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Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08288655A (en) * | 1995-04-18 | 1996-11-01 | Nippon Avionics Co Ltd | Method for manufacturing flex-rigid printed wiring board |
| WO2014203603A1 (en) * | 2013-06-18 | 2014-12-24 | 株式会社村田製作所 | Method for manufacturing multi-layer resin substrate |
| KR102435127B1 (en) * | 2015-07-06 | 2022-08-24 | 삼성전기주식회사 | Printed circuit board and camera module having the same |
| JP2018098260A (en) * | 2016-12-08 | 2018-06-21 | 大日本印刷株式会社 | Method of manufacturing multilayer wiring board with recessed portion, and member for lamination |
| CN106658949A (en) * | 2017-01-19 | 2017-05-10 | 广州美维电子有限公司 | Stepped plate and fabrication method thereof |
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