CN112542470A - Array substrate and preparation method thereof - Google Patents

Abstract

The application provides an array substrate and a preparation method thereof. The array substrate includes a substrate; a switching thin film transistor, which is arranged on the substrate; a photosensitive thin film transistor, which is arranged on the substrate; The photosensitive thin film transistors are arranged in the same layer and spaced apart; wherein, the switching thin film transistor includes a first semiconductor layer and a light shielding layer on the substrate; the photosensitive thin film transistor includes a second semiconductor layer on the substrate. In the present application, the light shielding layer, the first semiconductor layer and the second semiconductor layer are prepared by using the same mask process, which reduces the manufacturing process of the array substrate, reduces the production cost of using the existing technology, and improves the productivity efficiency; , and the light shielding layer above the first semiconductor layer is retained, so as to ensure the characteristics of the switching thin film transistor, while avoiding the influence of light on the characteristics of the switching thin film transistor.

Description

Array substrate and preparation method thereof

technical field

The present application relates to the field of display technology, and in particular, to an array substrate and a preparation method thereof.

Background technique

In the field of display technology, driving thin film transistors and sensor thin film transistors are widely used. Sensor thin film transistors require low subthreshold swing, low off-state current density and high electron mobility. In the prior art, indium gallium zinc oxide is usually used. The structure of IGZO and indium zinc oxide (IZO) is used as the semiconductor layer of the thin film transistor to meet the above requirements.

At present, in the in-cell touch technology (in-cell-touch) screen, there is a design in which the driving thin film transistor and the sensor thin film transistor are made in the same panel, which requires the driving thin film transistor to be taken into account during the production. Since indium gallium zinc oxide (IGZO) has light sensitivity, it is necessary to prepare a light shielding layer on the top layer of the driver thin film transistor, which increases the mask process and manufacturing cost.

SUMMARY OF THE INVENTION

The present application provides an array substrate and a preparation method thereof, which are used to solve the technical problems of complicated preparation method steps, high production cost and long cycle in the existing array substrate preparation process.

In order to solve the above-mentioned problems, the technical solutions provided by this application are as follows:

The present application provides a method for preparing an array substrate, including:

Step S10: forming a first metal layer on the substrate, patterning the first metal layer to form first electrodes and second electrodes spaced apart;

Step S20: forming an insulating layer, a semiconductor layer and a light shielding layer on the substrate, the first electrode and the second electrode;

Step S30 : using a mask to pattern the light shielding layer and the semiconductor layer to form a first semiconductor layer and a first light shielding layer above the first electrode, and a first light shielding layer above the second electrode. the second semiconductor layer;

Step S40 : forming a second metal layer on the first light shielding layer, the insulating layer and the second semiconductor layer, and patterning the second metal layer to form two layers on the first light shielding layer. The third electrode and the fourth electrode in the opposite edge regions, and the fifth electrode and the sixth electrode in the two opposite edge regions of the second semiconductor layer.

In the preparation method of the present application, the step 30 includes the following steps:

Step S31: preparing a photoresist on the light shielding layer;

Step S32 : exposing the photoresist by using a mask adjustment plate, and then developing the photoresist to form a first photoresist layer above the first electrode, and a photoresist layer above the second electrode. a second photoresist layer, the thickness of the first photoresist layer is greater than the thickness of the second photoresist layer;

Step S33 : etching the light shielding layer and the semiconductor layer not covered by the first photoresist layer and the second photoresist layer to form a first semiconductor layer and a first semiconductor layer above the first electrode a light shielding layer, and a second semiconductor layer and a second light shielding layer located above the second electrode;

Step S34 : performing ashing treatment on the first photoresist layer and the second photoresist layer, so that the second photoresist layer is completely peeled off, and the first photoresist layer is thinned;

Step S35 : using a dry etching process to etch the first photoresist layer and the second light shielding layer, so that the first photoresist layer and the second light shielding layer are completely peeled off;

Step S36 : removing the remaining photoresist on the surface of the first light shielding layer and the second semiconductor layer after etching.

In the preparation method of the present application, in the step S32, a mask process is performed on the photoresist by using a mask with different transmittances; the mask includes a first transmittance area, a second transmittance The transmittance area and the third transmittance area;

The first transmittance region corresponds to the first electrode and the first transmittance region is opaque; the second transmittance region corresponds to the second electrode and the second transmittance The transmittance of the area is 50%; the third transmittance area corresponds to the remaining area and the transmittance of the third transmittance area is 100%.

In the preparation method of the present application, step S33 includes the following steps:

Step S331: using a dry etching process to etch the light shielding layer not covered by the first photoresist layer and the second photoresist layer;

Step S332: Etch the semiconductor layer not covered by the first photoresist layer and the second photoresist layer by using a wet etching process.

In the preparation method of the present application, step S40 includes the following steps:

Step S41: depositing a second metal layer on the first light shielding layer, the insulating layer and the second semiconductor layer;

Step S42 : patterning the second metal layer through a mask to form a third electrode and a fourth electrode located at two opposite edge regions of the first light shielding layer, and forming a third electrode and a fourth electrode located at the second semiconductor layer The fifth electrode and the sixth electrode of the two opposing edge regions of the layer.

The present application also provides an array substrate, comprising:

substrate;

a switching thin film transistor, which is arranged on the substrate in an array, and the switching thin film transistor includes a first electrode and a first semiconductor layer that are arranged in layers;

a photosensitive thin film transistor, which is arranged on the substrate, and the photosensitive thin film transistor includes a second electrode and a second semiconductor layer that are stacked and arranged;

Wherein, the switching thin film transistor and the photosensitive thin film transistor are arranged at intervals, and the switching thin film transistor further includes a light shielding layer located above the first semiconductor layer.

In the array substrate of the present application, the array substrate includes a first metal layer, an insulating layer, a semiconductor layer, a second metal layer, and a passivation layer that are stacked and arranged;

The first metal layer is disposed on the substrate, and the first metal layer includes the first electrode and the second electrode arranged at intervals;

the insulating layer is disposed above the first metal layer;

The semiconductor layer is disposed above the insulating layer, and the semiconductor layer includes the first semiconductor layer and the second semiconductor layer;

The second metal layer is disposed above the semiconductor layer, the second metal layer includes a third electrode and a fourth electrode located at two opposite edge regions of the light shielding layer, and a third electrode and a fourth electrode located at two opposite edge regions of the second semiconductor layer. a fifth electrode and a sixth electrode of opposite edge regions;

The passivation layer is disposed above the insulating layer.

In the array substrate of the present application, the switching thin film transistor includes the first electrode, the first semiconductor layer, the light shielding layer, the third electrode and the fourth electrode on the substrate;

The photosensitive thin film transistor includes the second electrode, the second semiconductor layer, the fifth electrode and the sixth electrode on the substrate; wherein,

Both the first semiconductor layer and the second semiconductor layer include a stacked first metal oxide layer and a second metal oxide layer.

In the array substrate of the present application, the first semiconductor layer, the light shielding layer and the second semiconductor layer are prepared and formed through the same mask process.

In the array substrate of the present application, the material of the light shielding layer is molybdenum oxide.

Beneficial effects: The present application uses the same mask process to prepare the first semiconductor layer, the light shielding layer and the second semiconductor layer in the array substrate, which reduces the manufacturing process of the array substrate, reduces the production cost of the existing technology and improves the production capacity Benefit; wherein, the mask manufacturing process uses masks with different transmittances, including a half mask corresponding to the light shielding layer and the first semiconductor layer, so that the light shielding layer remains on the switching thin film transistor , while ensuring the characteristics of the switching thin film transistor, the influence of light on the characteristics of the switching thin film transistor is avoided.

Description of drawings

The technical solutions and other beneficial effects of the present application will be apparent through the detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram of a process flow of an array substrate provided by an embodiment of the present application;

2A-2I are schematic structural diagrams of the array substrate provided in the embodiment of the present application during the preparation process;

FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

In the prior art, there is a design in which the driving thin film transistor and the sensor thin film transistor are fabricated in the same panel in an in-cell-touch screen, which requires that the driving thin film should be taken into account during fabrication. The switching characteristics of transistors and the photosensitivity of sensor thin film transistors, because indium gallium zinc oxide (IGZO) has photosensitivity, so it is necessary to prepare a light shielding layer on the top layer of the prepared driving thin film transistor, resulting in an increase in the mask process and manufacturing cost . Based on this, the present application provides an array substrate and a preparation method thereof, which can solve the above-mentioned defects.

The technical solutions of the present application will now be described with reference to specific embodiments.

Example 1

Please refer to FIG. 1 , which is a schematic diagram of a process flow of an array substrate provided by an embodiment of the present application.

In this embodiment, the preparation method of the array substrate includes:

Step S10 : forming a first metal layer on the substrate 10 , and patterning the first metal layer to form a first electrode 21 and a second electrode 22 arranged at intervals, as shown in FIG. 2A .

In this embodiment, the step S10 includes the following steps:

Step S11: Provide a substrate 10, the substrate 10 includes but is not limited to a glass substrate and a flexible substrate.

Further, in this embodiment, the substrate 10 is a flexible and transparent PI substrate, mainly polyimide, and the PI material can effectively improve the light transmittance.

Step S12: depositing a first metal layer on the substrate 10, the material of the first metal layer includes but not limited to metals such as aluminum, molybdenum, titanium, copper and alloys thereof, and the method for depositing the first metal layer includes But not limited to physical vapor deposition.

Step S13 : patterning the first metal layer through a mask to form first electrodes 21 and second electrodes 22 arranged at intervals.

Further, in this embodiment, the first electrode 21 is a first grid, and the second electrode 22 is a second grid.

Step S20 : forming an insulating layer 30 , a semiconductor layer 40 and a light shielding layer 50 on the first electrode layer 20 , as shown in FIG. 2B .

In this embodiment, the step S20 includes the following steps:

Step S21 : preparing an insulating layer 30 on the substrate 10 , the insulating layer 30 completely covers the first electrode 21 and the second electrode 22 , the preparation method of the insulating layer 30 includes but is not limited to chemical vapor deposition Law.

In this embodiment, the insulating layer 30 is a gate insulating layer, and the material of the insulating layer 30 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, etc. or a stack thereof, and the thickness of the insulating layer 30 For 4000A-8000A.

Step S22 : preparing a semiconductor layer 40 on the insulating layer 30 , the semiconductor layer 40 includes a first metal oxide layer 41 and a second metal oxide layer 42 sequentially prepared on the insulating layer 30 , the semiconductor layer 40 is Methods of making layer 40 include, but are not limited to, physical vapor deposition.

The material of the first metal oxide layer 41 includes but is not limited to indium gallium zinc oxide (IGZO). The thickness of the first metal oxide layer 41 is 40 nm-100 nm; Materials include but are not limited to indium zinc oxide (IZO), and the thickness of the second metal oxide layer 42 is 40 nm-100 nm.

Step S23: Prepare a layer of light-shielding material on the semiconductor layer 40, the light-shielding material includes but not limited to molybdenum oxide, indium-magnesium oxide and other materials; An annealing process is performed to form the light shielding layer 50 .

Step S30 : using a mask to pattern the light shielding layer 50 and the semiconductor layer 40 to form a first semiconductor layer 401 and a first light shielding layer 501 located above the first electrode 21 , and The second semiconductor layer 402 above the second electrode is shown in FIG. 2G .

The first semiconductor layer 401 and the second semiconductor layer 402 both include a first metal oxide layer 41 and a second metal oxide layer 42 that are stacked and disposed, and the material of the first metal oxide layer 41 includes but does not Limited to indium gallium zinc oxide (IGZO), the material of the second metal oxide layer 42 includes but is not limited to indium zinc oxide (IZO).

In this embodiment, the step S30 includes the following steps:

Step S31 : preparing a photoresist on the light shielding layer 50 .

Step S32 : exposing the photoresist with a mask adjustment plate, and then developing the photoresist to form a first photoresist layer 61 above the first electrode and above the second electrode The second photoresist layer 62, the thickness of the first photoresist layer 61 is greater than the thickness of the second photoresist layer 62, as shown in FIG. 2C.

Wherein, the photoresist is subjected to a mask process using a mask plate with different transmittances; the mask plate includes a first transmittance region Tr1, a second transmittance region Tr2 and a third transmittance Area Tr3.

The first transmittance region Tr1 corresponds to the first electrode 21 and the first transmittance region Tr1 does not transmit light; the two transmittance region Tr2 corresponds to the second electrode 22 and the second The transmittance of the transmittance area Tr1 is 50%; the third transmittance area Tr3 corresponds to the remaining area and the transmittance of the third transmittance area is 100%.

In this embodiment, the thickness difference between the second photoresist layer 62 and the first photoresist layer 61 is 1um-2um, which is not limited in this embodiment.

It should be noted that, in this embodiment, the method of exposing the photoresist includes but is not limited to using masks with different transmittances; in this embodiment, using masks with different transmittances The masking process performed by the film plate on the photoresist is only used for illustration, which is not limited in this embodiment.

Step S33 : etching the light shielding layer 50 and the semiconductor layer 40 not covered by the first photoresist layer 61 and the second photoresist layer 62 to form a first photoresist layer above the first electrode 21 The semiconductor layer 401 and the first light shielding layer 501 , and the second semiconductor layer 402 and the second light shielding layer 502 located above the second electrode 22 are shown in FIG. 2D .

In this embodiment, the step S33 includes the following steps:

Step S331 : using a dry etching process to etch the light shielding layer 50 not covered by the first photoresist layer 61 and the second photoresist layer 62 .

Step S332 : using a wet etching process to etch the semiconductor layer 40 not covered by the first photoresist layer 61 and the second photoresist layer 62 .

Step S34 : performing ashing treatment on the first photoresist layer 61 and the second photoresist layer 62 , so that the second photoresist layer 62 is completely peeled off, and the first photoresist layer 61 is thinned to form The first sub-photoresist layer 610 is shown in FIG. 2E.

Step S35: The second light shielding layer 502 is etched by an etching process, as shown in FIG. 2F.

In this embodiment, the method for etching the second light shielding layer 502 includes, but is not limited to, dry etching.

Step S36 : peel off the first sub-photoresist layer 610 . As shown in FIG. 2G , the first sub-photoresist layer 610 is peeled off, and the first light shielding layer 501 remains on the second metal oxide layer 42 .

Step S40 : forming a second metal layer on the surface of the first light shielding layer 501 , the insulating layer 30 and the second semiconductor layer 402 , and patterning the second metal layer to form a second metal layer on the light shielding layer The third electrode 71 and the fourth electrode 72 in the two opposite edge regions 501 , and the fifth electrode 73 and the sixth electrode 74 in the two opposite edge regions of the second semiconductor layer 402 , as shown in FIG. 2H .

In this embodiment, the step S40 includes the following steps:

Step S41 : depositing a second metal layer on the first light shielding layer 501 , the insulating layer 30 and the second semiconductor layer 402 , the material of the second metal layer includes but is not limited to aluminum, molybdenum, titanium, For metals such as copper and its alloys, the method for depositing the second metal layer includes, but is not limited to, physical vapor deposition.

Step S42 : patterning the second metal layer through a mask to form a third electrode 71 and a fourth electrode 72 located in two opposite edge regions of the first light shielding layer 501 , and forming a third electrode 71 and a fourth electrode 72 located in the The fifth electrode 73 and the sixth electrode 74 of the two opposite edge regions of the second semiconductor layer 402 .

Further, in this embodiment, the third electrode 71 and the fourth electrode 72 are first source/drain electrodes, and the fifth electrode 73 and the sixth electrode 74 are second source/drain electrodes .

In this embodiment, the preparation method of the array substrate further includes step S50: in the third electrode 71, the first light shielding layer 501, the fourth electrode 72, the insulating layer 30, the first A passivation layer 80 is formed on the five electrodes 73 , the second semiconductor layer 402 and the sixth electrode 74 to form an array substrate, as shown in FIG. 2I .

The material of the passivation layer 80 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc. or a stack thereof.

In this embodiment, the light shielding layer 50 and the semiconductor layer 40 in the array substrate are prepared by the same mask process, which reduces the manufacturing process of the array substrate, reduces the production cost of the prior art and improves the productivity.

In the present application, the light-shielding layer 50 and the semiconductor layer 40 are prepared by using the same mask process, which reduces the manufacturing process of the array substrate, reduces the production cost of using the existing technology, and improves the productivity; at the same time, the first semiconductor is retained. The light shielding layer 51 above the layer 401, while ensuring the characteristics of the switching thin film transistor 100, avoids the influence of light on the characteristics of the switching thin film transistor 100; and the photosensitive thin film transistor 200 is removed by dry etching The light-shielding layer 50 on the light-sensitive thin film transistor 200 enhances the photosensitivity of the photosensitive thin film transistor 200 .

Embodiment 2

Please refer to FIG. 3 , which is a schematic structural diagram of an array substrate provided by an embodiment of the present application.

In this embodiment, the array substrate includes a substrate 10 ; a switching thin film transistor 100 , the switching thin film transistor 100 is arranged on the substrate 10 in an array, and the switching thin film transistor 100 includes a stacked first electrode 21 and The first semiconductor layer 401; the photosensitive thin film transistor 200, the photosensitive thin film transistor 200 is disposed on the substrate 10, and the photosensitive thin film transistor 200 includes the second electrode 22 and the second semiconductor layer 402 arranged in layers; The switching thin film transistor 100 is spaced apart from the photosensitive thin film transistor 200 , and the switching thin film transistor 100 further includes a light shielding layer 50 located above the first semiconductor layer.

In this embodiment, the photosensitive thin film transistor 100 and the display thin film transistor 200 are fabricated on the same substrate 10 to realize integrated sensing and display functions, and at the same time, the thickness of the array substrate can be reduced.

In this embodiment, the array substrate includes a first metal layer, an insulating layer 30 , a semiconductor layer 40 , a second metal layer and a passivation layer 80 that are stacked on the substrate 10 in sequence.

In this embodiment, the substrate 10 includes but is not limited to a glass substrate and a flexible substrate.

Further, in this embodiment, the substrate 10 is a flexible and transparent PI substrate, mainly polyimide, and the PI material can effectively improve the light transmittance.

In this embodiment, the first metal layer is disposed on the substrate 10 , and the first metal includes the first electrode 21 and the second electrode 22 arranged at intervals; the first metal layer The materials include but are not limited to metals such as aluminum, molybdenum, titanium, copper and their alloys.

In this embodiment, the insulating layer 30 is disposed above the first metal layer, the insulating layer 30 is a gate insulating layer, and the insulating layer 30 completely covers the first electrode 21 and the second metal layer. For the electrode 22, the material of the insulating layer 30 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc. or a stack thereof, and the thickness of the insulating layer 30 is 4000A-8000A.

In this embodiment, the semiconductor layer 40 is disposed above the insulating layer 30, and the semiconductor layer 40 includes the first semiconductor layer 401 and the second semiconductor layer 402; the first semiconductor layer 41 is disposed above the first electrode 21 ; the second semiconductor layer 42 is disposed above the second electrode 22 ; wherein, the first semiconductor layer 401 and the second semiconductor layer 402 both comprise stacked first Metal oxide layer 41 and second metal oxide layer 42 .

The material of the first metal oxide layer 41 includes but is not limited to indium gallium zinc oxide (IGZO). The thickness of the first metal oxide layer 41 is 40 nm-100 nm; Materials include but are not limited to indium zinc oxide (IZO), and the thickness of the second metal oxide layer 42 is 40 nm-100 nm.

In this embodiment, the light shielding layer 50 is disposed above the first semiconductor layer 401 , and the material of the light shielding layer 50 includes, but is not limited to, molybdenum oxide, indium magnesium oxide and other materials.

In this embodiment, the first semiconductor layer 401 , the light shielding layer 50 and the second semiconductor layer 402 are prepared and formed through the same masking process, thereby saving the manufacturing process and reducing the product cost.

In this embodiment, the second metal layer is disposed above the semiconductor layer 40 and the insulating layer 30 ; the second metal layer includes a third electrode 71 , a fourth electrode 72 , and a fifth electrode arranged at intervals 73 and the sixth electrode 74 .

The third electrode 71 and the fourth electrode 72 are located above the light shielding layer 50 and cover two opposite edge regions of the light shielding layer 50; the fifth electrode 73 and the sixth electrode 74 are located at the above the second semiconductor layer 402 and covering two opposite edge regions of the second semiconductor layer 402 .

Further, in this embodiment, the third electrode 71 and the fourth electrode 72 are first source/drain electrodes, and the fifth electrode 73 and the sixth electrode 74 are second source/drain electrodes .

In this embodiment, the passivation layer 80 is disposed above the insulating layer 30 , and the material of the passivation layer 80 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc. or a stack thereof.

In this embodiment, the switching thin film transistor 100 includes the first electrode 21 , the first semiconductor layer 401 , the light shielding layer 50 , and the third electrode 71 , which are disposed on the substrate 10 and are stacked. and the fourth electrode 72 ; the photosensitive thin film transistor 200 includes the second electrode 22 , the first semiconductor layer 402 , the fifth electrode 73 and the first semiconductor layer 402 , which are disposed on the substrate 10 and are stacked. Six electrodes 74 .

In this embodiment, the light-shielding layer 50 above the first semiconductor layer 401 is retained, which ensures the characteristics of the switching thin film transistor 100 and avoids the influence of light on the characteristics of the switching thin film transistor 100; and removes the photosensitive The light shielding layer 50 on the thin film transistor 200 enhances the photosensitivity of the photosensitive thin film transistor 200 .

The present application provides an array substrate and a preparation method thereof. The array substrate includes a substrate; a switching thin film transistor, which is arranged on the substrate; a photosensitive thin film transistor, which is arranged on the substrate; The photosensitive thin film transistors are arranged in the same layer and spaced apart; wherein, the switching thin film transistor includes a first semiconductor layer and a light shielding layer on the substrate; the photosensitive thin film transistor includes a second semiconductor layer on the substrate.

In the present application, the light-shielding layer and the semiconductor layer are prepared by using the same mask process, which reduces the manufacturing process of the array substrate, reduces the production cost of using the existing technology, and improves the productivity efficiency; meanwhile, the upper part of the first semiconductor layer is retained. The light shielding layer of the photosensitive thin film transistor ensures the characteristics of the switching thin film transistor while avoiding the influence of light on the characteristics of the switching thin film transistor; and removing the light shielding layer on the photosensitive thin film transistor through dry etching enhances the Photosensitivity of photosensitive thin-film transistors.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

An array substrate and a preparation method thereof provided by the embodiments of the present application have been described in detail above. The principles and implementations of the present application are described with specific examples in this article. The technical solution of the application and its core idea; those of ordinary skill in the art should understand that: it can still make modifications to the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications or replacements, The essence of the corresponding technical solutions does not deviate from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. The preparation method of the array substrate is characterized by comprising the following steps:

step S10: forming a first metal layer on a substrate, and carrying out patterning treatment on the first metal layer to form a first electrode and a second electrode which are arranged at intervals;

step S20: forming an insulating layer, a semiconductor layer, and a light shielding layer on the substrate, the first electrode, and the second electrode;

step S30: patterning the light shielding layer and the semiconductor layer by using a mask plate to form a first semiconductor layer and a first light shielding layer which are positioned above the first electrode, and a second semiconductor layer which is positioned above the second electrode;

step S40: and forming a second metal layer on the first shading layer, the insulating layer and the second semiconductor layer, and patterning the second metal layer to form a third electrode and a fourth electrode which are positioned in two opposite edge areas of the first shading layer, and a fifth electrode and a sixth electrode which are positioned in two opposite edge areas of the second semiconductor layer.

2. The method for preparing an array substrate according to claim 1, wherein the step 30 comprises the steps of:

step S31: preparing a photoresist on the shading layer;

step S32: exposing the photoresist by using a mask plate, and then developing the photoresist to form a first photoresist layer positioned above the first electrode and a second photoresist layer positioned above the second electrode, wherein the thickness of the first photoresist layer is greater than that of the second photoresist layer;

step S33: etching the shading layer and the semiconductor layer which are not covered by the first light resistance layer and the second light resistance layer to form a first semiconductor layer and a first shading layer which are positioned above the first electrode, and a second semiconductor layer and a second shading layer which are positioned above the second electrode;

step S34: ashing the first photoresist layer and the second photoresist layer to completely strip the second photoresist layer and thin the first photoresist layer to form a first sub-photoresist layer;

step S35: etching the second shading layer by adopting an etching process;

step S36: and stripping the first sub photoresist layer.

3. The method according to claim 2, wherein in step S32, masks with different transmittances are used to perform a masking process on the photoresist; the mask plate comprises a first penetration rate area, a second penetration rate area and a third penetration rate area;

the first transmittance region corresponds to the first electrode and is opaque; the second penetration rate area corresponds to the second electrode, and the penetration rate of the second penetration rate area is 50%; the third transmittance region corresponds to the remaining region and has a transmittance of 100%.

4. The method for preparing an array substrate according to claim 2, wherein the step S33 comprises the following steps:

step S331: etching the light shielding layer which is not covered by the first light resistance layer and the second light resistance layer by adopting a dry etching process;

step S332: and etching the semiconductor layer uncovered by the first light resistance layer and the second light resistance layer by adopting a wet etching process.

5. The method for preparing an array substrate of claim 1, wherein the step S40 comprises the following steps:

step S41: depositing a second metal layer on the first light-shielding layer, the insulating layer and the second semiconductor layer;

step S42: and patterning the second metal layer through a mask plate to form a third electrode and a fourth electrode which are positioned in two opposite edge areas of the first light shielding layer, and a fifth electrode and a sixth electrode which are positioned in two opposite edge areas of the second semiconductor layer.

6. An array substrate, comprising:

a substrate;

the switching thin film transistor is arranged on the substrate in an array mode and comprises a first electrode and a first semiconductor layer which are arranged in a stacked mode;

the photosensitive thin film transistor is arranged on the substrate and comprises a second electrode and a second semiconductor layer which are arranged in a stacked mode;

the switch thin film transistor and the photosensitive thin film transistor are arranged at intervals, and the switch thin film transistor further comprises a shading layer located above the first semiconductor layer.

7. The array substrate of claim 6, wherein the array substrate comprises a first metal layer, an insulating layer, a semiconductor layer, a second metal layer, and a passivation layer in a stacked arrangement;

the first metal layer is arranged on the substrate and comprises the first electrode and the second electrode which are arranged at intervals;

the insulating layer is arranged above the first metal layer;

the semiconductor layer is disposed over the insulating layer, the semiconductor layer including the first semiconductor layer and the second semiconductor layer;

the second metal layer is arranged above the semiconductor layer and comprises a third electrode and a fourth electrode which are positioned in two opposite edge areas of the light shading layer, and a fifth electrode and a sixth electrode which are positioned in two opposite edge areas of the second semiconductor layer;

the passivation layer is disposed over the insulating layer.

8. The array substrate of claim 7, wherein the switching thin film transistor comprises the first electrode, the first semiconductor layer, the light shielding layer, the third electrode, and the fourth electrode on the substrate;

the photosensitive thin film transistor comprises the second electrode, the second semiconductor layer, the fifth electrode and the sixth electrode which are positioned on the substrate; wherein,

the first semiconductor layer and the second semiconductor layer each include a first metal oxide layer and a second metal oxide layer which are stacked.

9. The array substrate of claim 7, wherein the first semiconductor layer, the light-shielding layer and the second semiconductor layer are formed by a same photo-masking process.

10. The array substrate of claim 6, wherein the light shielding layer is made of molybdenum oxide.

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