CN112542204A - Low-voltage alarm method and device for nonvolatile chip, storage medium and terminal - Google Patents
Low-voltage alarm method and device for nonvolatile chip, storage medium and terminal Download PDFInfo
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- CN112542204A CN112542204A CN202011589855.4A CN202011589855A CN112542204A CN 112542204 A CN112542204 A CN 112542204A CN 202011589855 A CN202011589855 A CN 202011589855A CN 112542204 A CN112542204 A CN 112542204A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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Abstract
The invention discloses a low-voltage alarm method, a device, a storage medium and a terminal of a nonvolatile chip, wherein the nonvolatile chip is quitted from programming and erasing operation when a higher voltage point is detected, when a lower voltage point is detected, namely a configuration register and a state register are unstable in voltage and even power down, as long as after the nonvolatile chip is electrified again, the content which is consistent with the content stored in the corresponding register before the nonvolatile chip is quitted from operation for one time is read from the nonvolatile chip, and the content is reconfigured into the configuration register and the state register, so that when the nonvolatile chip executes operation again, the data in the configuration register and the state register can not be mistaken, and the operation effectiveness of the nonvolatile chip is ensured; through setting up the low-voltage detection of two voltage points, make different actions respectively according to the difference of voltage point when taking place the low-voltage warning, guarantee non-volatile chip reliability.
Description
Technical Field
The invention relates to the technical field of Nor Flash, in particular to a low-voltage alarm method and device of a nonvolatile chip, a storage medium and a terminal.
Background
The programming and erasing operations of the Nor Flash chip take a relatively long time, and if the external voltage is unstable or even the power is directly cut off at the moment, the external capacitor or the capacitor inside the Nor Flash chip is not enough to support the whole operation process, the Nor Flash chip needs to ensure that the data of the memory cell is not interfered and lost under the condition of unstable voltage.
In general, when the low voltage is detected by the low voltage detection circuit, the Nor Flash is directly controlled to exit the programming or erasing operation. However, when the voltage is severely jittered and the transient current is large during programming and erasing, the configuration register and the status register inside the Nor Flash are changed (errors occur), and if the programming and erasing operations are simply exited, the configuration register and the status register inside the Nor Flash can cause the operation executed after the Nor Flash is normally powered on again to be invalid under the condition of the errors.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a low-voltage alarm method, a low-voltage alarm device, a storage medium and a terminal of a nonvolatile chip, and aims to solve the problem that the conventional Nor Flash only simply exits the current operation when the external voltage is abnormal, and the subsequent operation is easy to fail due to errors of a configuration register and a state register.
The technical scheme of the invention is as follows: a low-voltage alarm method of a nonvolatile chip specifically comprises the following steps:
when the Nor Flash is in the algorithm stage, acquiring the voltage in the Nor Flash for executing the current operation in real time;
judging whether the current voltage is equal to or less than a first preset value or not, if not, the Nor Flash does not exit the current operation,
if so, enabling the Nor Flash to exit the current operation;
judging whether the current voltage is equal to or less than a second preset value or not, if not, not changing the current state of Nor Flash,
when Nor Flash is normally powered on again, the content consistent with the content stored in the corresponding register before Nor Flash last quits operation is obtained, and the content is reconfigured into the register.
In the low-voltage alarm method of the nonvolatile chip, the algorithm phase is Nor Flash to execute programming operation or erasing operation.
The low-voltage alarm method of the nonvolatile chip is characterized in that the second preset value is smaller than the first preset value.
The low-voltage alarm method of the nonvolatile chip is characterized in that the register comprises a configuration register and a status register.
The low-voltage alarm method of the nonvolatile chip is characterized in that when the Nor Flash is in an algorithm phase, the voltage in the Nor Flash executing the current operation is acquired in real time, and the method specifically comprises the following steps: and when the Nor Flash is in the algorithm stage, updating the data stored in the register and simultaneously storing the data in the Nor Flash, and acquiring the voltage in the Nor Flash for executing the current operation in real time.
The low-voltage alarm method of the nonvolatile chip is characterized in that the content which is consistent with the content stored in the corresponding register before the Nor Flash last quit operation is obtained, and the content which is consistent with the content stored in the corresponding register before the Nor Flash last quit operation is read.
A low voltage alarm device of a non-volatile type chip, comprising:
the voltage acquisition module is used for acquiring the voltage in the Nor Flash executing the current operation in real time when the Nor Flash is in the algorithm stage;
the first judgment module is used for judging whether the current voltage is equal to or less than a first preset value;
the exit module enables the Nor Flash to exit the current operation;
the second judgment module is used for judging whether the current voltage is equal to or less than a second preset value;
and the register resetting module is used for acquiring the content consistent with the content stored in the corresponding register before the Nor Flash exits the operation last time when the Nor Flash is normally powered on again, and reconfiguring the content into the register.
The low-voltage alarm device of the nonvolatile chip is characterized in that a storage space for updating and storing data consistent with the data stored in the configuration register and the status register in real time is arranged in the Nor Flash.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform any of the methods described above.
A terminal comprising a processor and a memory, the memory having stored therein a computer program, the processor being adapted to perform the method of any preceding claim by invoking the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a low-voltage alarm method, a device, a storage medium and a terminal of a nonvolatile chip, when a higher voltage point is detected, Nor Flash is quitted from programming and erasing operation, when a lower voltage point is detected, namely when the voltage of a configuration register and a state register is unstable or even power failure occurs, as long as after Nor Flash is electrified again, the content consistent with the content stored in the corresponding register before Nor Flash is quitted from operation last time is read from Nor Flash, and the content is reconfigured into the configuration register and the state register, so that when Nor Flash executes operation again, data in the configuration register and the state register cannot be mistaken, and the validity of Nor Flash operation is ensured; by setting low voltage detection of two voltage points, different behaviors are respectively made according to the difference of the voltage points when low voltage alarm occurs, so that the Nor Flash reliability is ensured.
Drawings
FIG. 1 is a flow chart of the steps of the low voltage alarm method of the non-volatile chip of the present invention.
Fig. 2 is a schematic diagram of a low voltage alarm device of a nonvolatile chip in the present invention.
Fig. 3 is a schematic diagram of a terminal in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, a low voltage alarm method for a nonvolatile chip specifically includes the following steps:
s1: when the Nor Flash is in the algorithm stage, acquiring the voltage in the Nor Flash for executing the current operation in real time;
s2: judging whether the current voltage is equal to or smaller than a first preset value, if so, executing S3, otherwise, executing S1;
s3: enabling the Nor Flash to exit the current operation, and jumping to S4;
s4: judging whether the current voltage is equal to or smaller than a second preset value, if so, executing S5, otherwise, executing S4;
s5: and when the Nor Flash is normally electrified again, reading the content which is stored in the Nor Flash and is consistent with the content stored in the corresponding register before the Nor Flash quits the operation last time, and reconfiguring the content into the register.
In some embodiments, the algorithm phase is a program operation or an erase operation.
In some embodiments, the second predetermined value is smaller than the first predetermined value, such as 3.3V Nor Flash (i.e. the normal voltage applied to the memory cell by the Nor Flash performing the corresponding operation is 3.3V), and the first predetermined value can be set to 1.9V, and the second predetermined value can be set to 1.2V.
In some embodiments, the registers include a configuration register and a status register.
In certain embodiments, the S1 specifically includes the following processes: and when the Nor Flash is in the algorithm stage, updating the data stored in the register and simultaneously storing the data in the Nor Flash, and acquiring the voltage in the Nor Flash for executing the current operation in real time.
The Nor Flash has the function of not losing due to power failure, so that even if the applied voltage is unstable or even loses power, the data stored in the Nor Flash cannot be lost, and therefore, even if errors occur when the voltage is unstable or even loses power in the configuration register and the state register, as long as after the Nor Flash is electrified again, the content consistent with the content stored in the corresponding register before the Nor Flash is quitted for operation last time is read from the Nor Flash, and the content is reconfigured into the configuration register and the state register, so that when the Nor Flash executes operation again, the data in the configuration register and the state register cannot be mistaken, and the effectiveness of the Nor Flash operation is ensured.
As shown in fig. 2, a low voltage alarm device of a nonvolatile type chip includes:
the voltage acquisition module 101 is used for acquiring the voltage in the Nor Flash executing the current operation in real time when the Nor Flash is in the algorithm stage;
the first judging module 102 is used for judging whether the current voltage is equal to or smaller than a first preset value;
an exit module 103, which enables the Nor Flash to exit the current operation;
a second judging module 104, configured to judge whether the current voltage is equal to or smaller than a second preset value;
and the register resetting module 105 is used for acquiring the content consistent with the content stored in the corresponding register before the Nor Flash is last quitted from operation when the Nor Flash is normally powered on again, and reconfiguring the content into the register.
Referring to fig. 3, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: when the Nor Flash is in the algorithm stage, acquiring the voltage in the Nor Flash for executing the current operation in real time; judging whether the current voltage is equal to or smaller than a first preset value or not, if not, enabling the Nor Flash not to exit the current operation, and if so, enabling the Nor Flash to exit the current operation; and judging whether the current voltage is equal to or less than a second preset value or not, otherwise, not changing the current state of the Nor Flash, and if so, acquiring the content consistent with the content stored in the corresponding register before the Nor Flash is last quitted from operation, and reconfiguring the content into the register.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: when the Nor Flash is in the algorithm stage, acquiring the voltage in the Nor Flash for executing the current operation in real time; judging whether the current voltage is equal to or smaller than a first preset value or not, if not, enabling the Nor Flash not to exit the current operation, and if so, enabling the Nor Flash to exit the current operation; and judging whether the current voltage is equal to or less than a second preset value or not, otherwise, not changing the current state of the Nor Flash, and if so, acquiring the content consistent with the content stored in the corresponding register before the Nor Flash is last quitted from operation, and reconfiguring the content into the register. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A low-voltage alarm method of a nonvolatile chip is characterized by comprising the following steps:
when the Nor Flash is in the algorithm stage, acquiring the voltage in the Nor Flash for executing the current operation in real time;
judging whether the current voltage is equal to or less than a first preset value or not, if not, the Nor Flash does not exit the current operation,
if so, enabling the Nor Flash to exit the current operation;
judging whether the current voltage is equal to or less than a second preset value or not, if not, not changing the current state of Nor Flash,
when Nor Flash is normally powered on again, the content consistent with the content stored in the corresponding register before Nor Flash last quits operation is obtained, and the content is reconfigured into the register.
2. The low voltage alarm method of a non-volatile type chip according to claim 1, wherein the algorithm stage performs a program operation or an erase operation for Nor Flash.
3. The low voltage alarm method of a non-volatile chip according to claim 1, wherein the second preset value is smaller than the first preset value.
4. The low voltage alarm method of a non-volatile chip according to claim 1, wherein the registers include a configuration register and a status register.
5. The low-voltage alarm method of the nonvolatile chip as claimed in claim 1, wherein the obtaining the voltage in the Nor Flash executing the current operation in real time when the Nor Flash is in the algorithm phase specifically includes the following processes: and when the Nor Flash is in the algorithm stage, updating the data stored in the register and simultaneously storing the data in the Nor Flash, and acquiring the voltage in the Nor Flash for executing the current operation in real time.
6. The low voltage alarm method of claim 1, wherein the obtaining of the content consistent with the content stored in the register corresponding to Nor Flash before the last operation exit is performed by reading the content stored in Nor Flash consistent with the content stored in the register corresponding to Nor Flash before the last operation exit.
7. A low voltage alarm device of a nonvolatile type chip, comprising:
the voltage acquisition module is used for acquiring the voltage in the Nor Flash executing the current operation in real time when the Nor Flash is in the algorithm stage;
the first judgment module is used for judging whether the current voltage is equal to or less than a first preset value;
the exit module enables the Nor Flash to exit the current operation;
the second judgment module is used for judging whether the current voltage is equal to or less than a second preset value;
and the register resetting module is used for acquiring the content consistent with the content stored in the corresponding register before the Nor Flash exits the operation last time when the Nor Flash is normally powered on again, and reconfiguring the content into the register.
8. The low voltage alarm device of a nonvolatile type chip as claimed in claim 7, wherein a storage space for storing data in accordance with the data stored in the configuration register and the status register is updated in real time is provided in the Nor Flash.
9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 6.
10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 6 by calling the computer program stored in the memory.
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| CN202011589855.4A CN112542204A (en) | 2020-12-29 | 2020-12-29 | Low-voltage alarm method and device for nonvolatile chip, storage medium and terminal |
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| CN202011589855.4A CN112542204A (en) | 2020-12-29 | 2020-12-29 | Low-voltage alarm method and device for nonvolatile chip, storage medium and terminal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023193545A1 (en) * | 2022-04-06 | 2023-10-12 | 上海美仁半导体有限公司 | Power-failure protection method and apparatus for chip, and chip and storage medium |
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| US20130301373A1 (en) * | 2012-05-14 | 2013-11-14 | Eugene Jinglun Tam | Memory Chip Power Management |
| CN106557438A (en) * | 2015-09-30 | 2017-04-05 | 中兴通讯股份有限公司 | A kind of method of power down protection, device and electronic equipment |
| CN108983939A (en) * | 2017-05-31 | 2018-12-11 | 西部数据技术公司 | Power failure processing is carried out using ceasing and desisting order |
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2020
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130301373A1 (en) * | 2012-05-14 | 2013-11-14 | Eugene Jinglun Tam | Memory Chip Power Management |
| CN106557438A (en) * | 2015-09-30 | 2017-04-05 | 中兴通讯股份有限公司 | A kind of method of power down protection, device and electronic equipment |
| CN108983939A (en) * | 2017-05-31 | 2018-12-11 | 西部数据技术公司 | Power failure processing is carried out using ceasing and desisting order |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023193545A1 (en) * | 2022-04-06 | 2023-10-12 | 上海美仁半导体有限公司 | Power-failure protection method and apparatus for chip, and chip and storage medium |
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Application publication date: 20210323 |