CN112540934B - Method and system for ensuring quality of service when multiple delay-critical programs are jointly executed - Google Patents

Abstract

The invention discloses a method and a system for ensuring the service quality when a plurality of delay key programs are executed together, which start the plurality of delay key programs; each delay key program is preset in a corresponding core, and the delay key programs on each core share the last-level cache space; dividing each delay key program into a plurality of program stages; dividing each program stage into a plurality of program intervals; sampling a program interval in each program phase of each delay critical program in a process in which a plurality of delay critical programs are operated together; calculating first, second and third actual performance data of each program stage according to the sampling data; classifying the phase types and performances of the corresponding program phases according to the first, second and third actual performance data; and dynamically adjusting the cache space occupied by each delay key program in the running process according to the stage type and the performance type of each program stage of each delay key program.

Description

Method and system for ensuring quality of service when multiple delay-critical programs are jointly executed

technical field

The present application relates to the technical field of parallel and distributed computing, and in particular, to a method and system for ensuring quality of service when multiple delay-critical programs are jointly executed.

Background technique

The statements in this section merely mention the background art related to the present application and do not necessarily constitute prior art.

The data center has gone from concept to maturity. In a data center, in order to improve resource utilization, a large number of programs are executed on as few servers as possible. In a server node, multiple programs are executed on a node. The advantage of executing multiple programs together is that the utilization of the server can be increased, but the problem is that the program performance will be degraded. The degree of program performance degradation depends on the program characteristics. For some programs, the performance degradation is not obvious when executed with other programs, while for some programs, the performance drops significantly when executed with other programs.

At the same time, a large number of latency-critical programs are running in the data center. The customer executes the program in the data center and has certain service quality requirements for the program, for example, the program performance cannot be lower than 90% of that when executed alone. When delay-critical programs are executed together with other programs, it is easy to cause serious performance degradation due to performance interference, thus failing to meet customer service quality requirements. This is a problem that must be solved. Therefore, a method is needed to ensure the quality of service of delay-critical programs on the basis of improving system resource utilization as much as possible. This is a problem that this application must solve.

SUMMARY OF THE INVENTION

In order to solve the deficiencies of the prior art, the present application provides a method and system for ensuring the quality of service when multiple delay-critical programs are jointly executed;

In the first aspect, the present application provides a method for ensuring service quality when multiple delay-critical programs are jointly executed;

Methods to ensure quality of service when multiple latency-critical programs are executed together, including:

Initialize the hardware counter and start multiple delay-critical programs; each delay-critical program is preset in the corresponding core, and the delay-critical programs on each core share the last level of cache space LLC;

Divide each delay-critical program into several program stages; divide each program stage into several program intervals;

In the process that multiple delay-critical programs are running together, the hardware performance counter is used to sample the program interval in each program stage of each delay-critical program; and third actual performance data; classify the phase type of the corresponding program stage according to the first actual performance data; classify the performance of the program stage according to the second and third actual performance data;

According to the stage type and performance type of each program stage of each delay-critical program, the cache space occupied by each delay-critical program during the running process is dynamically adjusted.

In the second aspect, the present application provides a system for ensuring the quality of service when multiple delay-critical programs are jointly executed;

A system that guarantees quality of service when multiple latency-critical programs are executed together, including:

an initialization module, which is configured to: initialize a hardware counter, and start a plurality of delay-critical programs; each delay-critical program is preset in a corresponding core, and the delay-critical programs on each core share the last-level cache space LLC;

a stage division module, which is configured to: divide each delay-critical program into several program stages; further divide each program stage into several program intervals;

The classification module is configured to: sample program intervals in each program stage of each delay-critical program using hardware performance counters during a process in which a plurality of delay-critical programs are run together; calculate each delay-critical program according to the sampled data The first, second and third actual performance data of the program stage; the stage type of the corresponding program stage is classified according to the first actual performance data; the performance of the program stage is classified according to the second and third actual performance data;

The dynamic adjustment module is configured to: dynamically adjust the cache space occupied by each delay-critical program during the running process according to the stage type and performance type of each program stage of each delay-critical program.

In a third aspect, the present application also provides an electronic device, comprising: one or more processors, one or more memories, and one or more computer programs; wherein the processor is connected to the memory, and one or more of the above The computer program is stored in the memory, and when the electronic device runs, the processor executes one or more computer programs stored in the memory, so that the electronic device performs the method described in the first aspect above.

In a fourth aspect, the present application further provides a computer-readable storage medium for storing computer instructions, and when the computer instructions are executed by a processor, the method described in the first aspect is completed.

In a fifth aspect, the present application also provides a computer program (product), including a computer program, which when run on one or more processors, is used to implement the method of any one of the foregoing first aspects.

Compared with the prior art, the beneficial effects of the present application are:

By monitoring the performance indicators of delay-critical programs in real time, and using CAT to dynamically divide LLC resources for different types of delay-critical programs, it not only ensures the performance of multiple delay-critical programs when they are executed together, but also improves the utilization of LLC resources as much as possible.

Intel technology that supports Last Level Cache (LLC) allocation enables better cache utilization through cache partitioning. The present application can take advantage of this technique to guarantee user performance requirements by preventing delay-critical programs from polluting each other's caches. In addition, the present application can better meet the user's performance requirements by allocating more LLC resources to delay-critical programs that benefit from performance and reducing or stopping the allocation to delay-critical programs that do not benefit.

The invention dynamically adjusts the space occupied by the program by using the performance index of the stage in which the program is running. The present invention can improve the quantity of delay key programs and the resource utilization rate of LLC as much as possible while ensuring the program service quality.

Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will become apparent from the description which follows, or may be learned by practice of the invention.

Description of drawings

The accompanying drawings that form a part of the present application are used to provide further understanding of the present application, and the schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute improper limitations on the present application.

Fig. 1 is the flow chart of the resource division method of the first embodiment;

FIG. 2 is a flow chart of the performance analysis of the program stage of the first embodiment.

Detailed ways

It should be noted that the following detailed description is exemplary and intended to provide further explanation of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It should be noted that the terminology used herein is for the purpose of describing specific embodiments only, and is not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural as well, furthermore, it is to be understood that the terms "including" and "having" and any conjugations thereof are intended to cover the non-exclusive A process, method, system, product or device comprising, for example, a series of steps or units is not necessarily limited to those steps or units expressly listed, but may include those steps or units not expressly listed or for such processes, methods, Other steps or units inherent to the product or equipment.

Embodiments of the invention and features of the embodiments may be combined with each other without conflict.

Terminology Explanation:

Latency-critical programs refer to applications that have strict requirements on tail latency. Tail latency is an important performance indicator for latency-critical programs.

LLC, refers to: Last Level Cache, the last level cache, refers to the highest level cache that is usually shared by all functional units on the chip (such as CPU cores, IGPs, and DSPs).

CAT, refers to: Cache Allocation Technology, that is, cache allocation technology, the basic goal of which is to enable resource allocation based on application priority or class of service (CLOS). The Intel Xeon processor E5 v4 family (and a subset of the communications-focused Intel Xeon processor E5 v3 family) introduced the ability to configure and utilize cache allocation techniques on the last level of cache.

CLOS refers to: Class of Service, that is, service level. As an abstract concept, CLOS may have multiple resource control attributes attached, thereby reducing the software overhead during context exchange.

Example 1

This embodiment provides a method for ensuring quality of service when multiple delay-critical programs are jointly executed;

Methods to ensure quality of service when multiple latency-critical programs are executed together, including:

S101: Initialize a hardware counter, and start multiple delay-critical programs; each delay-critical program is preset in a corresponding core, and the delay-critical programs on each core share the last level cache space (LLC);

S102: Divide each delay key program into several program stages; divide each program stage into several program intervals;

S103: in the process that multiple delay-critical programs are jointly running, use a hardware performance counter to sample the program interval in each program stage of each delay-critical program;

Calculate the first, second and third actual performance data for each program stage from the sampled data;

classifying the phase type of the corresponding program phase according to the first actual performance data;

Classifying the performance of the program phases according to the second and third actual performance data;

S104: Dynamically adjust the cache space occupied by each delay-critical program during the running process according to the stage type and performance type of each program stage of each delay-critical program.

It should be understood that in S101, in order to ensure that each delay-critical program does not have CPU time contention, the initial state of the system places each delay-critical program in a different core, and the delay-critical programs on each core share the LLC.

Exemplarily, the multiple delay critical degrees refer to two or more delay critical programs.

As one or more embodiments, the S101 further includes:

Assuming that the cache space LLC has a total of N-way space, M-way space is reserved as spare space, and the remaining N-M-way space is evenly distributed to all delay-critical programs; N and M are positive integers.

Exemplarily, CAT is used to divide each delay-critical program into different CLOSs and isolate them, so as to reduce the influence among delay-critical programs.

Exemplarily, assuming that the system has N-way LLC space, M-way cache way space is reserved for CLOS#1 as a candidate space, and the remaining N-M-way space is evenly distributed to all delay-critical programs.

路。将N路LLC空间隔离起来，定义为CLOS#1，作为备用空间，值得注意的是，备用空间的地址是从CLOS#0的尾地址的下一个地址开始的。将剩余的LLC空间分配给延迟关键程序2，空间定义为CLOS#2。Exemplarily, it is assumed that there are two delay-critical programs. Since CAT only supports continuous division of LLC space, LLC space is allocated from low to high addresses. Delay-critical program 1 occupies the size of the space represented by CLOS#0, and the size is equal to

road. The N-way LLC space is isolated and defined as CLOS#1 as a spare space. It is worth noting that the address of the spare space starts from the next address of the tail address of CLOS#0. Allocate the remaining LLC space to delay critical program 2, with space defined as CLOS#2.

As one or more embodiments, the S102: Divide each delay-critical program into several program stages; the specific steps include:

The number of instructions is counted by a counter, and the stages of the program are divided by executing a set number of instructions.

As one or more embodiments, the S102: subdivide each program stage into several program intervals; the specific steps include:

Count the conditional branch instructions, and trigger an interrupt when X conditional branch instructions are executed;

That is, every X conditional branch instruction is regarded as a program interval; another hardware counter is responsible for recording the total number of instructions executed during this period, and X is a positive integer.

Exemplarily, each program stage is further divided into several program intervals; the specific steps further include:

Using different sampling periods, each program stage is divided into several program intervals.

It should be understood that, in S102, each delay-critical program is divided into program stages including a fixed number of instructions. In order to better obtain program performance information, the present application introduces a two-stage stage detection method.

Stage division: During the running process of the program, the performance indicators (such as IPC) of the program may change. The program fragments belonging to the same stage have similar performance indicators, while the performance indicators of program fragments belonging to different stages are different. Performance indicators, which divide the program into different stages. The present application uses a fixed number of instructions to divide the stages of the program, and then uses the IPC indicator to classify the runtime stages of the program. The fixed number of instructions can be 10 million, 100 million, or 1 billion.

interval division. In order to obtain the phase information of the runtime program in more detail, the present application adopts an interval division method to subdivide the program phases. In order to reduce sampling overhead and information loss, the present application adopts performance data to be sampled once every X conditional branch instructions. In this application, different sampling periods can be selected according to the actual situation, such as 100M and 200M.

As one or more embodiments, the S103: in the process that multiple delay-critical programs are jointly running, use a hardware performance counter to sample the program interval of each program stage of each delay-critical program; the specific steps include: :

In the process that multiple delay-critical programs are running together, the hardware performance counter is used to sample the program interval of each program stage of each delay-critical program to obtain performance indicators IPC, LLC misses, LLC Hits and LLC references.

Using the acquired LLC misses, LLC hits, and LLC citations, program gap metrics MPKI _LLC and HPKI _LLC are calculated. The formulas for calculating MPKI _LLC and HPKI _LLC for program intervals are as follows:

Num _Miss refers to LLC misses, Num _Ins refers to LLC citations, and Num _Hit refers to LLC hits.

It should be understood that, using the performance indicators of all intervals in the program stage, the mean value of the performance indicators is calculated as the performance indicator of the stage in which the delay-critical program is located, which is used to analyze the stage behavior of the delay-critical program.

As one or more embodiments, the S103: Calculate the first, second and third actual performance data of each program stage according to the sampled data; the specific steps include:

Calculate the first actual performance data of each program stage according to the sampled data; the first actual performance data refers to: the average IPC of the number of instructions per cycle;

Calculate the second actual performance data of each program stage according to the sampled data; the second actual performance data refers to: the mean value MPKI LLC of the number of missed instructions per thousand instructions on the _LLC ;

Calculate the third actual performance data of each program stage according to the sampled data; the third actual performance data refers to the average value of the number of hit instructions per thousand instructions on the LLC HPKI _LLC .

Exemplarily, according to the data sampled at each interval in the stage, the average value of IPC, MPKI _LLC (the number of missed instructions per thousand instructions on the LLC) and HPKI _LLC (the number of hit instructions per thousand instructions on the LLC) at the stage is calculated. The average calculation steps of IPC _LLC , MPKI _LLC and HPKI _LLC are as follows:

IPC _LLC1 refers to the IPC indicator for the first interval, n denotes the number of intervals in a program phase, MPKI _LLC1 refers to the MPKI indicator for the first interval, and HPKI _LLC1 refers to the HPKI indicator for the first interval.

As one or more embodiments, the S103: Classify the phase type of the corresponding program phase according to the first actual performance data; the specific steps include:

将程序阶段类型划分为3类：according to

The program phase types are divided into 3 categories:

Class A:

Class B:

Class C:

Among them, α refers to the first set threshold value, and β refers to the second set threshold value.

As one or more embodiments, the S103: Classify the performance of the program stage according to the second and third actual performance data; the specific steps include:

和

将程序性能类型分为3类：according to

and

Divide program performance types into 3 categories:

class a:

class b:

class c:

Here, η refers to the third set threshold, γ refers to the fourth set threshold, and η<γ.

As one or more embodiments, the S104: According to the stage type and the performance type of each program stage of each delay-critical program, perform the cache space occupied during the running of each delay-critical program. Dynamic adjustment; specific steps include:

Determine the stage type and performance type of each program stage of each delay-critical program;

If the program stage type is class A and the performance type is class a or b, it is preliminarily judged that the program stage needs to increase the cache space; in the process of increasing the cache space, if the program stage type does not change, immediately stop increasing the cache space and Reduce the increased cache space; if the stage type becomes B or C, save the modification;

不变，则继续减少缓存空间，否则还原修改操作；If the program stage type is class A and the performance type is class c, it is preliminarily judged that the program stage needs to reduce the cache space; if the 1-way cache space is reduced,

If it does not change, continue to reduce the cache space, otherwise restore the modification operation;

If the program stage is class B and the performance type is class b, the cache space occupied by the program stage will not be changed;

If the program stage is class B and the performance type is class a or c, it is preliminarily judged that the program stage needs to reduce the cache space; if the 1-way cache space is reduced and the stage type has not changed to type A, continue to reduce the cache space; otherwise, Revert modified operations;

If the program stage is class C, and the performance type is class a or class c, it is necessary to judge whether there is excess resources in the program stage. Cache space; otherwise, restore the modified operation;

If the program stage is class C and the performance type is class b, the cache space occupied by the program stage will not be changed;

As one or more embodiments, the method further includes:

Obtain the resource usage of LLC for dynamic management;

If there is free space in CLOS#1, the space is obtained from CLOS#1. If the cache space in CLOS#1 is allocated, it is judged whether the adjacent program on the physical address is in a state of excess resources; The performance status allocates excess space, and if there is no excess resources, it continues to wait for free space; if there is no free space for a long time, data migration is performed.

The stage performance data for each program is registered in the Historical Stage & Performance Table (HPPT). HPPT stores phase information and performance information for each program. The present application dynamically adjusts the cache occupied by the current stage according to the stage behavior of the running program and the program runtime performance information.

The cache space occupied by the delay-critical program is dynamically adjusted according to the stage of the delay-critical program and MPKI_LLC and HPKI_LLC.

Figure 1 describes the resource partitioning method. For each program that needs to be executed, use hardware performance counters to obtain program performance information.

Figure 2 describes the program phase performance analysis method.

指标对程序运行时阶段进行分析，并利用

和

指标对程序性能进行分析，进而动态的调整程序所占的缓存空间。For each program that needs to be executed, use

Metrics analyze the runtime phases of the program and utilize

and

The indicator analyzes the program performance, and then dynamically adjusts the cache space occupied by the program.

Embodiment 2

This embodiment provides a system for ensuring the quality of service when multiple delay-critical programs are jointly executed;

A system that guarantees quality of service when multiple latency-critical programs are executed together, including:

an initialization module, which is configured to: initialize a hardware counter, and start a plurality of delay-critical programs; each delay-critical program is preset in a corresponding core, and the delay-critical programs on each core share the last-level cache space LLC;

a stage division module, which is configured to: divide each delay-critical program into several program stages; further divide each program stage into several program intervals;

The classification module is configured to: sample the program interval in each program stage of each delay-critical program by using hardware performance counters in the process that a plurality of delay-critical programs are run together; calculate each delay-critical program according to the sampled data The first, second and third actual performance data of the program stage; the stage type of the corresponding program stage is classified according to the first actual performance data; the performance of the program stage is classified according to the second and third actual performance data;

The dynamic adjustment module is configured to: dynamically adjust the cache space occupied by each delay-critical program during the running process according to the stage type and performance type of each program stage of each delay-critical program.

It should be noted here that the above initialization module, stage division module, classification module and dynamic adjustment module correspond to steps S101 to S104 in the first embodiment, and the examples and application scenarios implemented by the above modules and the corresponding steps are the same, but not the same. It is limited to the content disclosed in the first embodiment above. It should be noted that the above modules can be executed in a computer system such as a set of computer-executable instructions as part of the system.

The description of each embodiment in the foregoing embodiments has its own emphasis. For the part that is not described in detail in a certain embodiment, reference may be made to the relevant description of other embodiments.

The proposed system can be implemented in other ways. For example, the system embodiments described above are only illustrative. For example, the division of the above modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into other A system, or some feature, can be ignored, or not implemented.

Embodiment 3

This embodiment also provides an electronic device, comprising: one or more processors, one or more memories, and one or more computer programs; wherein the processor is connected to the memory, and the one or more computer programs are Stored in the memory, when the electronic device runs, the processor executes one or more computer programs stored in the memory, so that the electronic device executes the method described in the first embodiment.

It should be understood that, in this embodiment, the processor may be a central processing unit CPU, and the processor may also be other general-purpose processors, digital signal processors DSP, application-specific integrated circuits ASIC, off-the-shelf programmable gate array FPGA or other programmable logic devices , discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory may include read-only memory and random access memory and provide instructions and data to the processor, and a portion of the memory may also include non-volatile random access memory. For example, the memory may also store device type information.

In the implementation process, each step of the above-mentioned method can be completed by a hardware integrated logic circuit in a processor or an instruction in the form of software.

The method in the first embodiment can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor. The software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware. To avoid repetition, detailed description is omitted here.

Those skilled in the art can realize that the units and algorithm steps of each example described in conjunction with this embodiment can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

Embodiment 4

This embodiment also provides a computer-readable storage medium for storing computer instructions, and when the computer instructions are executed by the processor, the method described in the first embodiment is completed.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (8)

1. A method for ensuring quality of service when multiple delay-critical programs are jointly executed, characterized in that it includes: Initialize the hardware counter and start multiple delay-critical programs; each delay-critical program is preset in the corresponding core, and the delay-critical programs on each core share the last level of cache space LLC; Divide each delay-critical program into several program stages; divide each program stage into several program intervals; In the process that multiple delay-critical programs are running together, the hardware performance counter is used to sample the program interval in each program stage of each delay-critical program; and third actual performance data; classify the phase type of the corresponding program stage according to the first actual performance data; classify the performance of the program stage according to the second and third actual performance data; calculate the performance of each program stage according to the sampled data The first, second and third actual performance data; the specific steps include: calculating the first actual performance data of each program stage according to the sampled data; the first actual performance data refers to: the average value of the IPC of the number of instructions per cycle; The second actual performance data of each program stage is calculated by data; the second actual performance data refers to: the mean value MPKI _LLC of the number of missed instructions per thousand instructions on the LLC; the third actual performance data of each program stage is calculated according to the sampled data ; The third actual performance data refers to: the mean value of the number of hit instructions per thousand instructions on the LLC HPKI _LLC ; According to the second and third actual performance data, the performance of the program stage is classified; Concrete steps include: according to

The program phase types are divided into 3 categories: Class A:

Class B:

Class C:

Wherein, α refers to the first set threshold, and β refers to the second set threshold; or, The performance of the program phase is classified according to the second and third actual performance data; the specific steps include: according to

and

Divide program performance types into 3 categories: class a:

class b:

class c:

Wherein, η refers to the third set threshold, γ refers to the fourth set threshold, and η<γ; According to the stage type and performance type of each program stage of each delay-critical program, dynamically adjust the cache space occupied by each delay-critical program during the running process; the specific steps include: Determine the stage type and performance type of each program stage of each delay-critical program; If the program stage type is class A and the performance type is class a or b, it is preliminarily judged that the program stage needs to increase the cache space; in the process of increasing the cache space, if the program stage type does not change, immediately stop increasing the cache space and Reduce the increased cache space; if the stage type becomes B or C, save the modification; If the program stage type is class A and the performance type is class c, it is preliminarily judged that the program stage needs to reduce the cache space; if the 1-way cache space is reduced,

If it does not change, continue to reduce the cache space, otherwise restore the modification operation; If the program stage is class B and the performance type is class b, the cache space occupied by the program stage will not be changed; If the program stage is class B and the performance type is class a or c, it is preliminarily judged that the program stage needs to reduce the cache space; if the 1-way cache space is reduced and the stage type has not changed to type A, continue to reduce the cache space; otherwise, Revert modified operations; If the program stage is class C, and the performance type is class a or class c, it is necessary to judge whether there is excess resources in the program stage. Cache space; otherwise, restore the modified operation; If the program stage is class C and the performance type is class b, the cache space occupied by the program stage will not be changed; According to the stage type and performance type of each program stage of each delay-critical program, the cache space occupied by each delay-critical program during the running process is dynamically adjusted. 2. method as claimed in claim 1 is characterized in that, described initializing hardware counter, starts a plurality of delay key programs; Also comprises: Assuming that the cache space LLC has a total of N-way space, M-way space is reserved as spare space, and the remaining N-M-way space is evenly distributed to all delay-critical programs; N and M are positive integers. 3. method as claimed in claim 1 is characterized in that, described dividing each delay key program into several program stages; Concrete steps comprise: The number of instructions is counted by a counter, and the stages of the program are divided by executing a set number of instructions. 4. method as claimed in claim 1 is characterized in that, each program stage is divided into several program intervals again; Concrete steps comprise: Count the conditional branch instructions, and trigger an interrupt when X conditional branch instructions are executed; That is, every X conditional branch instruction is regarded as a program interval; another hardware counter is responsible for recording the total number of instructions executed during this period, and X is a positive integer. 5. method as claimed in claim 1 is characterized in that, in the process that a plurality of delay key programs are jointly operated, utilize hardware performance counter to sample the program interval of each program stage of each delay key program; Specific steps include: In the process that multiple delay-critical programs are running together, the hardware performance counter is used to sample the program interval of each program stage of each delay-critical program to obtain performance indicators IPC, LLC misses, LLC Hits and LLC citations. 6. A system for ensuring the quality of service when multiple delay-critical programs are jointly executed, characterized by including: an initialization module, which is configured to: initialize a hardware counter and start a plurality of delay-critical programs; each delay-critical program is preset in a corresponding core, and the delay-critical programs on each core share the last-level cache space LLC; a stage division module, which is configured to: divide each delay-critical program into several program stages; further divide each program stage into several program intervals; The classification module is configured to: sample program intervals in each program stage of each delay-critical program using hardware performance counters during a process in which a plurality of delay-critical programs are run together; calculate each delay-critical program according to the sampled data The first, second and third actual performance data of the program stage; the stage type of the corresponding program stage is classified according to the first actual performance data; the performance of the program stage is classified according to the second and third actual performance data; according to The sampling data calculates the first, second and third actual performance data of each program stage; the specific steps include: calculating the first actual performance data of each program stage according to the sampled data; the first actual performance data refers to: every cycle The average value of the number of instructions IPC; calculate the second actual performance data of each program stage according to the sampled data; the second actual performance data refers to: the mean value MPKI _LLC of the number of missed instructions per thousand instructions on the LLC; calculate each The third actual performance data of the program stage; the third actual performance data refers to: the mean value HPKI _LLC of the number of hit instructions per thousand instructions on the LLC; the performance of the program stage is classified according to the second and third actual performance data; concrete steps include: according to

The program phase types are divided into 3 categories: Class A:

Class B:

Class C:

Wherein, α refers to the first set threshold, and β refers to the second set threshold; or, The performance of the program phase is classified according to the second and third actual performance data; the specific steps include: according to

and

Divide program performance types into 3 categories: class a:

class b:

class c:

Wherein, η refers to the third set threshold, γ refers to the fourth set threshold, and η<γ; According to the stage type and performance type of each program stage of each delay-critical program, dynamically adjust the cache space occupied by each delay-critical program during the running process; the specific steps include: Determine the stage type and performance type of each program stage of each delay-critical program; If the program stage type is class A and the performance type is class a or b, it is preliminarily judged that the program stage needs to increase the cache space; in the process of increasing the cache space, if the program stage type does not change, immediately stop increasing the cache space and Reduce the increased cache space; if the stage type becomes B or C, save the modification; If the program stage type is class A and the performance type is class c, it is preliminarily judged that the program stage needs to reduce the cache space; if the 1-way cache space is reduced,

If it does not change, continue to reduce the cache space, otherwise restore the modification operation; If the program stage is class B and the performance type is class b, the cache space occupied by the program stage will not be changed; If the program stage is class B and the performance type is class a or c, it is preliminarily judged that the program stage needs to reduce the cache space; if the 1-way cache space is reduced and the stage type has not changed to type A, continue to reduce the cache space; otherwise, Revert the modified operation; If the program stage is class C, and the performance type is class a or class c, it is necessary to judge whether there is excess resources in the program stage. Cache space; otherwise, restore the modified operation; If the program stage is class C and the performance type is class b, the cache space occupied by the program stage will not be changed; The dynamic adjustment module is configured to: dynamically adjust the cache space occupied by each delay-critical program during the running process according to the stage type and performance type of each program stage of each delay-critical program. 7. An electronic device, characterized in that it comprises: one or more processors, one or more memories, and one or more computer programs; wherein the processor is connected to the memory, and the one or more computer programs are Stored in a memory, when the electronic device is running, the processor executes one or more computer programs stored in the memory to cause the electronic device to perform the method of any one of claims 1-5 above. 8. A computer-readable storage medium, characterized in that it is used for storing computer instructions, and when the computer instructions are executed by a processor, the method according to any one of claims 1-5 is completed.

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