CN112534695A

CN112534695A - Method for controlling MMC

Info

Publication number: CN112534695A
Application number: CN201880096403.7A
Authority: CN
Inventors: M·穆罕默迪
Original assignee: ABB Grid Switzerland AG
Current assignee: Hitachi Energy Ltd
Priority date: 2018-08-06
Filing date: 2018-08-06
Publication date: 2021-03-19
Also published as: WO2020030245A1

Abstract

The present disclosure relates to a method of controlling an MMC (7) in an inverter arrangement (4) between a DC network (2) and a three-phase AC network (5). The method includes detecting an internal AC fault in an inverter arrangement. The method also includes controlling the MMC by blocking each of the cells in the negative arm while the positive arm remains in operation and controls the current of each phase to zero.

Description

Method for controlling MMC

Technical Field

The present disclosure relates to a method of controlling a Direct Current (DC) to Alternating Current (AC) Modular Multilevel Converter (MMC).

Background

An MMC is a Voltage Source Converter (VSC) type power Converter, also called Voltage Source inverter, comprising series-connected cells (also called modules or sub-modules) forming Converter branches (also called arms). These branches can be configured in several ways, resulting in a dedicated converter topology. Depending on the output voltage requirements of these branches to provide only positive voltages or also negative voltages, the cells in the branches may be implemented by only half-bridge (HB, also known as unipolar or unidirectional) cells or full-bridge (FB, also known as bipolar, bidirectional or H-bridge) cells, or a combination of HB and FB cells, respectively. A DC to three-phase AC MMC inverter structure in a double star configuration may be used for interconnection of a three-phase grid (e.g., 50 or 60Hz) with a DC grid (e.g., a high voltage DC (hvdc) grid).

HVDC connected MMC inverters are prone to high cell overvoltage during internal AC faults, which are faults between the MMC (in particular its cells/valves) and the auxiliary side of the transformer interfacing with the AC grid (also referred to as the valve side, i.e. the side facing towards the MMC and facing away from the AC grid).

WO 2017/080597 discloses an MMC for handling AC side faults. The MMC comprises a control unit configured to enter a first protection control mode upon detection of an operational disturbance of the converter, the first protection control mode comprising controlling all bipolar voltage contribution units to operate as unipolar voltage contribution units, and if the operational disturbance is identified as a fault with respect to a phase of the connected AC link, blocking units of a phase leg connected to the connection for the remainder of the first protection control mode, and controlling units of the phase leg connected to a health of the AC link to handle the effects of the fault. This solution is mainly applicable to the MMC arm of FB cells only, whereas the case of the mixed FB and HB cell arm may be more challenging to handle.

Disclosure of Invention

It is an object of the present invention to provide a new method of detecting and handling internal AC faults in an inverter arrangement comprising at least one MMC, in particular when said inverter arrangement comprises a plurality of serially connected MMCs. Some embodiments of the invention are particularly useful for MMCs having arms with mixed FB and HB cells. Moreover, some embodiments of the invention are particularly useful for MMCs connected in series with at least one other MMC.

According to an aspect of the invention, a method of controlling an inverter arrangement between a DC network and a three-phase AC network is provided. The inverter arrangement comprises a plurality of series connected converter arrangements, each converter arrangement comprising a controller and an MMC having a topology with one positive leg and one negative leg per phase. Each of the arms comprises a plurality of series-connected converter cells, each of these cells comprising an energy storage device and a plurality of valves. At least 50% of the plurality of series-connected converter cells of each arm are full-bridge cells. The method comprises, in each of the plurality of converter arrangements, by a controller in the converter arrangement: sensing at least one characteristic of the MMC; detecting that an internal AC fault has occurred in one of the plurality of converter arrangements based on the sensed characteristic; and in response to the detection of the fault, controlling the MMC in the converter arrangement by blocking the negative arm of the MMC while keeping the positive arm of the MMC unblocked and controlling the current magnitude of each phase towards zero.

According to another aspect of the present invention, there is provided a computer program product comprising computer-executable components for causing a controller to perform an embodiment of the method of the present disclosure when the computer-executable components are run on processing circuitry comprised in the controller.

According to another aspect of the invention, an inverter arrangement is provided, which is configured for use between a DC network and a three-phase AC network. The inverter arrangement comprises a plurality of series connected converter arrangements, each converter arrangement comprising a controller and an MMC having a topology with one positive leg and one negative leg per phase. Each of the arms comprises a plurality of series-connected converter cells, each of the cells comprising an energy storage device and a plurality of valves, at least 50% of the plurality of series-connected converter cells of each arm being full-bridge cells. In each of a plurality of series-connected converter arrangements, a controller comprises a processing circuit and a data storage device storing instructions executable by the processing circuit, whereby the controller is operable to: sensing at least one characteristic of an MMC in the converter arrangement; detecting that an internal AC fault has occurred in one of the plurality of converter arrangements based on the sensed characteristic; and in response to the detection of the fault, controlling the MMC in the converter arrangement by blocking the negative arm of the MMC while keeping the positive arm of the MMC unblocked and controlling the current magnitude of each phase towards zero.

By the way of detecting an internal AC fault outlined herein, an MMC can itself detect an internal AC fault in another MMC connected in series with it without the need for time consuming inter-MMC communication, which may delay the effective handling of the fault. According to the present disclosure, regardless of whether the internal AC fault is at its own MMC or at another serially connected MMC, the controller can control the MMC in the same way by blocking all negative arm cells while keeping the positive arm unblocked and controlling the current of each phase to zero.

It should be noted that any feature of any one of the aspects may be applicable to any other aspect, where appropriate. Likewise, any advantage of any one of the aspects may apply to any one of the other aspects. Other objects, features and advantages of the included embodiments will become apparent from the following detailed disclosure, from the appended dependent claims and from the drawings.

In general, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined herein. All references to "a/an/the element, device, component, means, step, etc" are to be interpreted openly as referring to at least one instance of the element, device, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. The use of "first," "second," etc. for various features/components of the present disclosure is intended only to distinguish the features/components from other similar features/components, and not to impart any order or hierarchy to the features/components.

Drawings

Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

fig. 1 is a schematic circuit diagram of an embodiment of an HVDC system according to the present invention.

Fig. 2 is a schematic circuit diagram of an embodiment of a DC-AC converter arrangement according to the invention.

Fig. 3 is a schematic circuit diagram of an embodiment of a converter arm of an MMC comprising both HB and FB converter cells according to the present invention.

Fig. 4 is a schematic functional block diagram illustrating an embodiment of a control method for non-communicative internal AC fault detection in accordance with the present invention.

Fig. 5 is a schematic view of an embodiment of a sensing arrangement in a converter arrangement according to the present invention.

Fig. 6 is a schematic block diagram of an embodiment of a controller of an inverter arrangement according to the present invention.

Fig. 7 is a schematic flow chart diagram of an embodiment of a control method of internal AC fault handling according to the present invention.

Fig. 8 is a more detailed schematic flow chart of an embodiment of the method steps of detecting an internal AC fault according to the present invention.

Detailed Description

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown. However, many different forms of other embodiments are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

Fig. 1 shows a system 1, in particular a HVDC system, wherein a DC network 2 is connected to an AC network 5 by means of an inverter arrangement 4. The inverter arrangement 4 comprises at least one VSC in the form of an MMC 7, for example, as shown, at least two MMCs 7 in series. On the other hand, on the rectifier side, the rectifier arrangement 3 may comprise at least one Line Commutated Converter (LCC), for example, as shown, at least two LCCs in series. However, the present disclosure focuses on the inverter arrangement 4.

The inverter arrangement 4 comprises at least one converter arrangement 6 and a controller 10 (see fig. 6). Each converter arrangement 6 comprises an MMC and a converter transformer 8 interfacing the MMC with the AC network 5. It may be convenient to connect the MMCs 7, and thus the converter arrangements 6, in series, in view of the voltage rating of each MMC, especially for high voltage applications, such as HVDC. For example, as illustrated in the figure, if the nominal voltage of the HVDC network 2 is 800kV and the available MMCs have a rated voltage of 400kV, two serially connected MMCs 7 are required in the inverter arrangement 4. In the figure, these MMCs 7 comprise an upper MMC 7a in an up-converter arrangement 6a, which up-converter arrangement 6a further comprises an upper transformer 8a, said upper MMC 7a having a positive terminal p at 800kV (voltage of the HVDC network 2) and a negative terminal n at 400 kV. The serially connected MMC 7 further comprises a lower MMC 7b in the lower converter arrangement 6b, which lower converter arrangement 6b further comprises a lower transformer 8b, said lower MMC 7b having a positive terminal p at 400kV (same as the negative terminal voltage of the upper MMC 7 a) and a negative terminal n at 0kV (connected to ground). Each MMC has two DC terminals: a positive DC terminal p connecting the positive arms 21p together; and a negative DC terminal n connecting the negative arms 21n together. Generally, a positive current flows into the MMC at the positive terminal and flows out of the MMC at the negative terminal.

As discussed herein, the first MMC may (in the system of fig. 1) be either one of an upper MMC and a lower MMC, and the second MMC is the other. It should be noted that in other embodiments the inverter arrangement 4 may comprise more than two converter arrangements 6, wherein each MMC 7 is in a series connection.

Fig. 2 shows a converter arrangement 6, which converter arrangement 6 comprises an MMC and a transformer 8, as discussed above with reference to fig. 1. Since the AC network 5 is a three-phase AC network, the MMC 7 comprises three phases 20, here denoted 20a, 20b and 20c, each connected to a respective one of the three phases of the AC network. Each phase 20 includes two arms 21, a negative arm 21n connected to the negative terminal n and a positive arm 21p connected to the positive terminal p. Thus, the MMC 7 has a modular multilevel topology, wherein each phase 20 has one positive leg 21p and one negative leg 21n, wherein each of said legs 21 comprises a plurality of series-connected converter cells. In some embodiments of the present invention, the MMC has a double star topology (also referred to as a double-wye or double-Y topology), as shown in fig. 2.

In this figure, the valves V of the different arms 21 of MMC 7 are collectively referred to as: vap for positive arm 21p of phase 20a, Van for negative arm 21n of phase 20a, Vbp for positive arm 21p of phase 20b, Vbn for negative arm 21n of phase 20b, Vcp for positive arm 21p of phase 20c, Vcn for negative arm 21n of phase 20 c.

The internal AC fault 22 is shown schematically in fig. 2. As discussed herein, an internal AC fault is a fault occurring in the converter arrangement 6 between the valve side of the transformer 8 and the MMC 7 (typically defined as the valve of the MMC).

Fig. 3 shows an arm 21 of the MMC 7, for example, any one of the positive arm or the negative arm in fig. 2. The arm 21 comprises a plurality of series-connected converter cells 31 and (optionally) at least one series-connected reactor 34. Each of the cells includes an energy storage device 33 and a plurality of valves 35. In the example of fig. 3, the arm includes both a full-bridge (FB) cell 31F and a half-bridge (HB) cell 31H, here in a 1:1 ratio of 50% each. Typically, at least 50% of the FB cells 31F are needed, and thus have at most 50% HB cells. Thus, according to embodiments of the present disclosure, each arm 21 has between 50% and 100% FB cells. However, as discussed further below, embodiments of the present invention may be particularly useful when each arm 21 includes at least one HB cell, e.g., up to 50% HB cells.

Each valve 35 includes a semiconductor switch S, here conventionally denoted as S1, S2, S3 and S4 in FB unit 31F, and S1 and S2 in HB unit 31H. In the figure, each of the semiconductor switches S comprises a dual-mode insulated gate transistor (BIGT), which may be suitable in some embodiments. However, in some other embodiments, another type of semiconductor switch may be suitable, for example, an Insulated Gate Bipolar Transistor (IGBT), a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a forced commutated thyristor, or any other forced commutated switch. Each valve 35 also typically includes an anti-parallel unidirectional semiconductor device 36, for example, including a diode, such as a freewheeling diode. To avoid cluttering the figure, the reference numerals for the valve 35 and the anti-parallel unidirectional semiconductor device 36 are given only in the top cell of the figure.

The energy storage device 33 may comprise a capacitor arrangement comprising at least one capacitor. The energy storage device 33, and thus its cells 31, may be charged and discharged during operation when its cells 31 are inserted in its arm 21, rather than being bypassed in its arm 21. The cell 31 can only be charged or discharged when inserted. Also, the charging or discharging of the cell depends on the current direction. Therefore, due to the different structure of the FB cell 31F compared to the HB cell 31H, the charging and discharging of the cells may be different for FB and HB cells in the same arm 21. For example, when the negative arm 21n is blocked, for current flowing from ground through the negative arm, the HB cell will be bypassed (and therefore not charged) via the anti-parallel unidirectional semiconductor device 36, while the FB cell will be inserted (and therefore charged and result in an increased voltage) via the anti-parallel unidirectional semiconductor device 36. Thus, a reverse voltage may be generated by the FB cell in the negative arm, which may limit the cell charging current (also referred to herein as fault current) caused by the internal AC fault 22 in the inverter arrangement 4. Therefore, if all cells in each arm are FB cells, the fault current is more effectively limited. However, embodiments of the invention are useful with up to 50% HB cells in each arm.

Another factor to consider is the period of time from the occurrence of the fault 22 to the detection of the fault, i.e. the detection delay. The smaller the detection delay, the more effective the limitation of the fault current. From the above discussion, it may be particularly important to effectively limit the fault current when the HB cell is in the arm. Thus, according to the present invention, a communication-less detection of an internal AC fault in the series-connected converter arrangement 6 is proposed, i.e. an internal AC fault in a second converter arrangement of the series connection comprising a second MMC is typically detected in a first converter arrangement comprising the first MMC by a converter arrangement sub-controller in the controller 10, without requiring a signaling from the second converter arrangement to the first converter arrangement in order to inform the first converter arrangement about the fault in the second converter arrangement.

Fig. 4 shows an example embodiment of a procedure performed in a

first converter arrangement

6a or 6b, for example by a converter arrangement controller 10 of the first converter arrangement, for a communication-less detection of an internal AC fault in a

second converter arrangement

6b or 6 a.

The inputs to the process of the embodiment of fig. 4 are (expressed herein as per unit, pu):

a DC current Idc followed in time, for example sampled continuously or periodically, for example as measured at the positive terminal p and/or the negative terminal n of the MMC. The direction of the DC current measurement at the positive terminal p is positive in the direction into the MMC 7 (the current towards the valve of the MMC is positive), while the direction of the DC current measurement at the negative terminal n is positive in the direction out of the MMC 7 (the current in the direction away from the valve of the MMC is positive). The sum of the currents flowing in the valve positive arm 21p (Vap, Vbp, and Vcp) is equal to the DC current Idcp, and similarly, the sum of the currents flowing in the valve negative arm 21n (Van, Vbn, and Vcn) is equal to the DC current Idcn. Therefore, instead of the DC current, the sum of the arm currents in 21p/21n may be used.

o based on the DC current Idc, a pre-fault DC current (idcperflt) measured before the fault 22, e.g. at the positive terminal p and/or the negative terminal n of the MMC, may be compared with the DC current during the fault 22.

-a DC voltage (Udc) of the MMC, which is followed in time, e.g. sampled continuously or periodically.

o sensing the DC voltage allows determining the voltage difference Δ Udc over a predetermined number of control cycles. In an embodiment, the number of control cycles may be 3, i.e. Δ Udc is calculated as the difference of the measured Udc of the current control cycle minus the measured Udc of the control cycle three cycles ago. Generally, according to experimental results, the number of control cycles is an integer in the range of 1 to 10, or 2 to 5, preferably 3. Typical examples of control period durations are in the range from 100 to 200 mus.

Alternatively, in some embodiments, the DC rated voltage of the MMC may be used as the predetermined threshold voltage value Um 1.

-the pre-fault power of the first MMC may optionally be obtained based on the sensed voltage and currents Udc and Idc,

which may be used to determine whether the converter was in inverter operation prior to the fault (during steady state operation).

This may be optional, for example, because it may already be known whether the MMC operates as an inverter or a rectifier.

Then, the process steps of non-communication fault detection in the first MMC 7 connected in series with the other MMC(s) may be:

a) during the fault 22, an internal AC fault has occurred in the upper converter arrangement 6a (the first MMC is part of the lower converter arrangement 6b relative to the upper converter arrangement in which the fault has occurred) if the DC current Idc in the converter changes its direction from positive to negative with more than a predetermined second threshold current value (e.g. in the range of-1.2 to-2.0 pu, e.g. -1.5pu) (where the negative sign indicates that the current has changed its direction). Note that the DC current at both the pole and the neutral point (neutral) of the down-converter may typically vary in the same direction at the same level. It is further noted that the converter arrangement controller 10 may not know in advance whether its converter arrangement with the first MMC is connected as an up-converter arrangement or as a down-converter arrangement in the inverter arrangement 4.

b) During the fault 22, if the DC current Idc increases in the same direction (which means no negative sign since the current does not change direction) with more than a predetermined first threshold current Im1 (e.g. in the range of 0.2 to 1.0pu, e.g. 0.5pu), an internal AC fault has occurred in the lower converter arrangement 6b (the first MMC is part of the upper converter arrangement 6a relative to the lower converter arrangement 6b in which the fault has occurred). Note that the DC currents at both the pole and the neutral point in the up-converter may generally increase in the same direction at the same level. Again, note that the converter arrangement controller 10 may not know in advance whether its converter arrangement with the first MMC is connected as an up-converter arrangement or a down-converter arrangement in the inverter arrangement 4, which is why both steps a) and b) may be performed for the first MMC, and the or function shown in fig. 4 indicates that an internal AC fault may have occurred if any of the contents discussed in a) and b) occurred.

c) Optionally, during the fault 22, the DC voltage difference (Δ Udc) over, for example, three control cycles may meet a requirement above a predetermined threshold voltage value Um1 and/or below the negative value of said predetermined threshold voltage value-Um 1. The predetermined threshold voltage value Um1 may be in the range of, for example, 0.5 to 1.0pu, for example, corresponding to the rated voltage of an MMC. In some embodiments, the difference in the sensed DC voltage difference (Δ Udc) is above a predetermined threshold voltage value Um1 and below the negative value of said predetermined threshold voltage value Um1 during a predefined time window of, for example, a few milliseconds, such as five milliseconds or three milliseconds or a quarter of the fundamental frequency period of the AC network 5. This condition of step c) together with the conditions of steps a) and b) mentioned above can distinguish internal AC faults from other types of faults, such as DC faults.

An OFF-delay (OFF-delay) may be imposed when criterion a) or b), or criterion c) has occurred, which means that when the signal goes high and then goes low again, it remains high for a set time specified by the OFF-delay time. Voltage and current transients due to fault 22 may occur at slightly different times in the MMC, after determining that either of conditions a) or b) is met or that condition c) is met, a turn-off delay may be used to see if the other conditions [ c) or a)/b ] are also met. Typical examples of the turn-off delay duration may be in the range from 10 to 20 ms. The output in fig. 4 refers to the output from the no communication fault detection algorithm.

Note that the communication-less fault detection method for a series converter is faster than using direct communication, which always includes some communication delay. The reason is that the non-communicating method detects the fault 22 in the initial stage of the fault and does not wait for the faulty second converter arrangement to detect the fault first and then to communicate the fault communication to the first converter arrangement.

If an internal AC fault 22 instead occurs in the first converter arrangement, the fault is detected by the converter arrangement sub-controller of the controller 10 directly by conventional means, for example using differential protection.

Regardless of whether a fault 22 is detected by the first converter arrangement directly in the first converter arrangement or by the non-communication detection in the second converter arrangement, the same processing steps for controlling the first MMC are taken, namely:

the positive leg 21p of the first MMC should remain in operation, i.e. remain unblocked, so that the control phase current approaches zero, e.g. to zero or close to zero, as it converges towards zero by controlling the positive leg, e.g. controlling the phase current until the magnitude of the phase current is close to zero.

The negative arm 21n of the first MMC should block causing the FB cell 31F in arm 21n to build up a reverse voltage on the negative arm.

As a result of this control method, the reverse voltage generated by the FB cell on the negative arm is sufficient to limit the cell charging current due to the internal AC fault 22.

Fig. 5 shows a sensing arrangement 51 in the converter arrangement 6 at each terminal of the MMC 7 in the converter arrangement 6 at which a forward current (a current flowing in a forward direction from the DC grid 2 towards ground) flows into and out of the valve arrangement of the MMC, respectively. As discussed herein, the sensing arrangement may be used to sense the DC current Idc and the DC voltage Udc. The sensing arrangement (51) comprises a current sensor (52) and a voltage sensor (53). The current sensor is arranged to sense the DC current locally within the converter arrangement 6, e.g. without requiring a separate communication channel. Similarly, the voltage sensor is arranged to sense the DC voltage locally within the converter arrangement. The converter arrangement further comprises a controller (54) receiving the sensed DC current and DC voltage from the current sensor and the voltage sensor, respectively. The controller 54 may be a sub-controller or part of the controller 10 of the converter arrangement 6, as discussed herein.

Fig. 6 schematically shows an embodiment of the controller 10 of the inverter arrangement 4 of the present disclosure. The controller may for example be centralized or distributed, and the controller may for example comprise a sub-controller for each of the MMCs 7 in each of the converter arrangements 6, in the inverter arrangement 4, and/or in each of the cells 31 and/or valves 35 of said MMC. Typically, each converter arrangement 6 comprises a controller 10, which may or may not be in communication with other controllers in the inverter arrangement. The controller may be arranged for controlling the MMC (S) of the inverter arrangement 4 by using a reference and controlling the conducting and non-conducting state of the valve switch S of said MMC (S) based on said reference. The controller 10 includes a processing circuit 11, such as a Central Processing Unit (CPU). The processing circuit 11 may comprise one or more processing units in the form of microprocessor(s). However, other suitable devices with computing capabilities may be included in the processing circuit 301, such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or a Complex Programmable Logic Device (CPLD). The processing circuitry 11 is configured to run one or more computer programs or Software (SW)13 stored in data storage 12 of one or more memory units, such as memory. The storage unit is considered a computer-readable device as discussed herein, and may be, for example, in the form of Random Access Memory (RAM), flash memory, or other solid state memory or hard disk, or may be a combination thereof. The processing circuitry 11 may also be configured to store data in the storage means 12 as required.

Fig. 7 illustrates some embodiments of the methods of the present disclosure. The method includes sensing characteristics of the M1 MMC, such as a DC current Idc and a DC voltage Udc of the MMC. The method also includes detecting that the M2 has experienced an internal AC fault 22 in one of the plurality of converter arrangements based on sensing the characteristics of the M1. For example, the detecting M2 includes: in some embodiments it is detected that an internal AC fault has occurred in its own converter arrangement, or in some other embodiments it is detected that an internal AC fault has occurred in another converter arrangement of the plurality of converter arrangements.

As discussed herein, the detection M2 may be performed by means of a communication-less detection process, in particular when a fault 22 is detected in a series connected converter arrangement 6 instead of detecting a fault 22 in the converter arrangement in which the detection M2 is being performed. Referring to fig. 8, then the no communication detection M2 includes: a pre-fault 22 DC current idcprflt is determined, for example at the positive terminal p and/or the negative terminal n of the MMC. Further, detecting M2 may include: it is determined that the difference between the DC current Idc sensed by M11 and the pre-fault DC current idcperflt is above a predetermined first threshold current value Im1 or below a predetermined second threshold current value Im 2. In some embodiments, the predetermined first threshold current value Im1 is in a range from 0.2 to 1.0 pu. In some embodiments, the predetermined second threshold current value Im2 is in a range from-1.2 to-2.0 pu. Further, detecting M2 may include: it is determined that the absolute value of the difference Δ Udc in DC voltage sensed by M12 over multiple control cycles during fault 22 is above a predetermined threshold voltage value Um 1. In some embodiments, the predetermined threshold voltage value Um1 is in the range from 0.5 to 1.0 pu. In some embodiments, during a predefined time window, the difference Δ Udc in DC voltage of sensing M1 is above a predetermined threshold voltage value Um1 and below the negative of the predetermined threshold voltage value-Um 1.

However, in some embodiments, wherein detecting M2 comprises detecting that an internal AC fault has occurred in its own converter arrangement, then detecting M2 comprises using differential protection instead of the so-called no-communication detection described herein and with reference to fig. 8. Then, in some embodiments, the method comprises signaling information about detecting the internal AC fault of M2 to the respective controller(s) 10 of the other converter arrangement of the plurality of converter arrangements of the inverter arrangement.

Detecting M1 also includes determining M11 that, e.g., at the positive terminal p and/or the negative terminal n of the MMC, the DC current Idc during the fault 22 changes its direction by at least 1.5pu compared to the pre-fault DC current (e.g., according to Idc-idcperflt < -1.5pu), or increases by at least 0.5pu compared to the pre-fault DC current (e.g., according to Idc-idcperflt >0.5 pu). According to | Idcp-Idcn | <0.1pu, detecting M1 further includes determining that the difference between the DC current Idcp at the positive terminal p and the DC current Idcn at the negative terminal n during the fault is at most 0.1 pu. Detecting M1 further includes: it is determined that the difference Δ Udc in DC voltage over n control cycles during the fault 22, M14, is above a predefined factor "a" between 0 and 1 times the positive rated voltage + Udc _ rate of the MMC and below a predefined factor "a" between 0 and 1 times the negative rated voltage-Udc _ rate of the MMC during a predetermined time window.

In some embodiments of the present invention, the DC current Idc and the DC voltage Udc are sensed M1 at one or both of the positive and negative terminals p and/or n of MMC 7. In some embodiments, the DC current Idc is sensed as a DC current flowing into the positive DC terminal p of the MMC, a DC current flowing out of the negative terminal n of the MMC, or a current of the (e.g., six) arms 21 of the MMC. In some embodiments, the DC voltage Udc is sensed as a voltage between the positive DC terminal p and ground, a voltage between the negative DC terminal n and ground, or a voltage between the two DC terminals p and n.

Referring to fig. 8, in some embodiments of the invention, detecting that an M2 internal AC fault has occurred in another converter arrangement of the plurality of converter arrangements comprises: determining that a change in the sensed DC current Idc of M11 during the fault 22 as compared to the pre-fault DC current Idc-preflt is equal to or greater than a predetermined first threshold, and determining that the difference Δ Udc in the DC voltage sensed by M12 over multiple control cycles during the fault 22 at M1 is equal to or greater than a predetermined second threshold. In some embodiments, the number of control cycles is an integer in the range of 1 to 10, or 2 to 5, preferably 3.

In some embodiments, the sensed DC current change being equal to or greater than the predetermined first threshold corresponds to the DC current Idc sensed M1 changing its direction by at least 1.5pu compared to the pre-fault DC current idcperflt (e.g., according to Idc-idcperflt < -1.5pu), where Idc may be sensed at the positive terminal p, Idcp, of MMC 7 or at the negative terminal n, Idcn, of MMC 7.

In some other embodiments, the sensed DC current change being equal to or greater than the predetermined first threshold corresponds to the DC current Idc of the sense M1 increasing by at least 0.5pu compared to the pre-fault DC current idcperflt.

Thus, in some embodiments, the absolute value of the first threshold is at least 0.5pu, i.e., the first threshold is-0.5 pu or +0.5 pu.

In some embodiments of the invention, the absolute value of the second threshold is at least the rated DC voltage Udc _ rate of the MMC, i.e. the second threshold is + Udc _ rate or-Udc _ rate. In some embodiments, sensing that the difference Δ Udc in the DC voltage of M1 is equal to or greater than the predetermined second threshold over a plurality of control cycles during the fault 22 corresponds to the difference Δ Udc in the DC voltage being above the positive DC rated voltage + Udc _ rate of the MMC and below the negative DC rated voltage-Udc _ rate of the MMC during the predetermined window of time. In some embodiments of the invention, the predetermined time window in the determining step M14 is less than 5ms, for example one quarter of the fundamental frequency period of the AC network 5.

In some embodiments of the invention, at least one of the plurality of series-connected converter cells 31 of each arm 21 is a half-bridge cell 31H and up to 50% is a half-bridge cell 31H, i.e. each arm comprises both FB cells and HB cells.

In some embodiments of the present invention, the MMC has a double star topology.

In at least one of the converter arrangements 6, the detecting M2 comprises detecting an internal AC fault between a valve side of a

transformer

8b or 8a and another

MMC

7b or 7a connected to the AC network 5 through the valve side, wherein the other MMC is comprised in an external converter arrangement 6, with which external converter arrangement 6 at least one converter arrangement 6 is connected in series.

Additionally, in at least another one of the converter arrangements 6, detecting M2 comprises: in which an internal AC fault between its

MMC

7a or 7b and the valve side of its

transformer

8a or 8b, through which its MMC is connected to the AC network 5, is detected internally, i.e. the converter arrangement 6 can detect a fault 22 within itself by a conventional detection procedure, such as differential protection.

Regardless of whether the fault 22 is detected in its own converter arrangement or externally, in response to the detection of said fault, each of the plurality of series-connected converter arrangements 6 controls its MMC by blocking each of the cells 31 in the negative arm 21n while keeping the positive arm 21p in operation and controlling the current of each phase 20 to zero.

An embodiment of the method of the invention may be performed by a controller 10 (e.g. comprising a converter controller 51, which is the converter controller 51 of each converter arrangement 6 comprised in the inverter arrangement 4), which controller 10 comprises a processing circuit 11 associated with the data storage 12. The processing circuitry may be provided with one or more processing units CPU in the form of microprocessor(s) executing appropriate software stored in an associated memory to obtain the required functionality. However, other suitable devices with computing capabilities may be included in the processor, such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), etc., in order to control the valves of the individual MMCs 7 in the inverter arrangement 4 and to perform embodiments of the method of the present disclosure, while executing suitable software 13, which software 13 is stored, for example, in a suitable data storage device 12, such as RAM, flash memory or a hard disk, or in the processing circuit itself (e.g., in case of an FPGA).

Embodiments of the invention may be conveniently implemented using one or more conventional general purpose or special purpose digital computers, computing devices, machines or microprocessors, including one or more processors, memories, and/or computer readable storage media programmed according to the teachings of the present disclosure. Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those skilled in the software art.

In some embodiments, the present invention includes a computer program product 12, the computer program product 12 being a non-transitory storage medium or computer-readable medium (media) having stored thereon/therein instructions 13 in the form of computer-executable components or Software (SW) that can be used to program a computer to perform any of the methods/processes of the present invention. Examples of storage media may include, but are not limited to, any type of disk including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and/or data.

In a more general embodiment of the invention, a method of controlling an MMC 7 in an inverter arrangement 4 between a DC network 2 and a three-phase AC network 5 is provided, wherein the method comprises detecting an internal AC fault 22 in the M1 inverter arrangement, and controlling the M2 the MMC by blocking each of the cells 31 in the negative leg 21n while the positive leg 21p remains in operation and controlling the current of each phase 20 to zero.

The present disclosure has been described above primarily with reference to several embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the disclosure, as defined by the appended claims.

Claims

1. A method of controlling an inverter arrangement (4) between a DC network (2) and a three-phase AC network (5), the inverter arrangement comprising a plurality of series-connected converter arrangements (6a, 6b), each converter arrangement comprising a controller (10) and a Modular Multilevel Converter (MMC) (7), the Modular Multilevel Converter (MMC) (7) having a topology with one positive arm (21p) and one negative arm (21n) per phase (20), wherein each of the arms (21) comprises a plurality of series-connected converter cells (31), each of the cells comprising an energy storage device (33) and a plurality of valves (35), at least 50% of the plurality of series-connected converter cells of each arm being full-bridge cells (31F),

the method comprises, in each converter arrangement of the plurality of converter arrangements (6), by a controller (10) in the converter arrangement:

sensing (M1) at least one characteristic of the MMC;

detecting (M2) that an internal AC fault (22) has occurred in one of the plurality of converter arrangements based on the sensed (M1) characteristic; and

in response to the detection (M2) of the fault (22), controlling (M3) the MMCs in the converter arrangement by blocking a negative arm (21n) of the MMC while keeping a positive arm (21p) of the MMC unblocked and controlling a current magnitude of each phase (20) towards zero.

2. The method of claim 1, wherein the at least one characteristic comprises: -sensing (M1) a DC current (Idc) and/or a DC voltage (Udc), e.g. at one or both of the positive and negative DC terminals (p, n) of the MMC (7), -sensing (M1) a DC current (Idc) and/or a DC voltage (Udc), e.g. between the positive and/or negative terminal and ground or between the positive and negative terminal.

3. The method of any preceding claim, wherein detecting (M2) that the internal AC fault has occurred comprises:

determining (M11) a difference between the sensed DC current (Idc) and the pre-fault DC current (Idcperflt):

above a predetermined first threshold current value (Im 1); or

Below a predetermined second threshold current value (Im 2).

4. A method according to claim 3, wherein the predetermined first threshold current value (Im1) is in the range from 0.2 to 1.0 per unit.

5. The method according to claim 3 or 4, wherein the predetermined second threshold current value (Im2) is in the range from-1.2 to-2.0 per unit.

6. The method of any preceding claim, wherein detecting (M2) that the internal AC fault has occurred comprises:

determining (M12) that an absolute value of a difference (Δ Udc) in the DC voltage sensed (M1) over a plurality of control cycles during the fault (22) is above a predetermined threshold voltage value (Um 1).

7. The method according to claim 6, wherein the predetermined threshold voltage value (Um1) is in the range from 0.5 to 1.0 per unit.

8. Method according to claim 6 or 7, wherein during a predefined time window the difference (Δ Udc) in the sensed (M1) DC voltage is above the predetermined threshold voltage value (Um1) and below the negative value (-Um1) of the predetermined threshold voltage value.

9. The method of any preceding claim, wherein the detecting (M2) in at least one of the plurality of transducer arrangements comprises: detecting that the internal AC fault has occurred in another converter arrangement of the plurality of converter arrangements (6).

10. The method of any preceding claim, wherein the detecting (M2) in at least one of the plurality of transducer arrangements comprises: the internal AC fault has occurred in its own converter arrangement is detected by differential protection.

11. The method of claim 10, wherein the method comprises: signaling information about detecting (M2) an internal AC fault to respective controllers (10) of other of the plurality of converter arrangements.

12. A computer program product (12) comprising computer-executable components (13) for causing a controller (10) to perform the method of any preceding claim when the computer-executable components are run on processing circuitry (11) comprised in the controller.

13. An inverter arrangement (4), the inverter arrangement (4) being configured between a DC network (2) and a three-phase AC network (5), the inverter arrangement comprising:

a plurality of series connected converter arrangements (6a, 6b), each converter arrangement comprising a controller (10) and a Modular Multilevel Converter (MMC) (7), the Modular Multilevel Converter (MMC) (7) having a topology with one positive arm (21p) and one negative arm (21n) per phase (20), wherein each of the arms (21) comprises a plurality of series connected converter cells (31), each of the cells comprising an energy storage device (33) and a plurality of valves (35), at least 50% of the plurality of series connected converter cells of each arm being a full bridge cell (31F);

wherein, in each converter arrangement of the plurality of series-connected converter arrangements, the controller (10) comprises a processing circuit (11) and a data storage device (12) storing instructions (13) executable by the processing circuit, whereby the controller is operable to:

sensing at least one characteristic of the MMC in the converter arrangement;

detecting (22) that an internal AC fault has occurred in one of the plurality of converter arrangements based on the sensed characteristic; and

in response to detection of the fault (22), controlling the MMC in the converter arrangement by blocking a negative leg (21n) of the MMC while keeping a positive leg (21p) of the MMC unblocked and controlling a current magnitude of each phase (20) towards zero.