CN112530885A - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN112530885A CN112530885A CN201910880284.0A CN201910880284A CN112530885A CN 112530885 A CN112530885 A CN 112530885A CN 201910880284 A CN201910880284 A CN 201910880284A CN 112530885 A CN112530885 A CN 112530885A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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Abstract
The invention relates to a chip packaging structure and a chip packaging method, which comprise a chip and a back gold layer, wherein the chip comprises a first chip surface and a second chip surface which are oppositely arranged, the back gold layer covers the second chip surface, the back gold layer comprises a first back gold layer surface close to the chip and a second back gold layer surface far away from the chip, at least one open slot is formed in the back gold layer, the open slot penetrates through the back gold layer in the direction towards the chip, and at least part of the open slot is opposite to the second chip surface. The chip packaging structure can solve the problem that the back gold layer can generate bad stress damage to the chip under the action of expansion with heat and contraction with cold in the existing chip packaging structure.
Description
Technical Field
The invention relates to the technical field of packaging, in particular to a chip packaging structure and a chip packaging method.
Background
At present, in the technical field of semiconductor packaging, in order to meet the heat dissipation requirements of chips and packaged devices, a back gold layer is generally formed by depositing metal on the back of a chip, and the back gold layer can be formed by overlapping multiple layers of metal, so that the heat resistance of the chip is effectively reduced, and the heat dissipation efficiency of the chip is improved.
Because the thermal expansion coefficient of the back gold layer is different from that of the chip, the back gold layer and the chip have different deformation under the action of expansion with heat and contraction with cold, so that the back gold layer can generate larger stress action on the chip under the action of expansion with heat and contraction with cold, and the chip can be damaged by stress. With the increasing size of semiconductor chips, the stress failure becomes more severe.
Disclosure of Invention
The invention aims to provide a chip packaging structure, which aims to solve the problem that a back gold layer can generate adverse stress damage to a chip under the action of thermal expansion and cold contraction in the conventional chip packaging structure.
In order to achieve one of the above objectives, an embodiment of the present invention provides a chip package structure, including a chip and a back gold layer, where the chip includes a first surface of the chip and a second surface of the chip, the back gold layer covers the second surface of the chip, the back gold layer includes a first surface close to the chip and a second surface far from the chip, the back gold layer is provided with at least one open slot, the open slot penetrates through the back gold layer in a direction toward the chip, and a position of at least a portion of the open slot faces the second surface of the chip.
As a further improvement of the embodiment of the present invention, two or more open grooves are formed in the back gold layer, and the two or more open grooves are distributed in a centrosymmetric manner with respect to the center of the second surface of the back gold layer.
As a further improvement of an embodiment of the present invention, four open slots are formed in the back gold layer, and the four open slots are located on two central axes of the back gold layer to form a cross-shaped pattern.
As a further improvement of the embodiment of the present invention, four open slots are formed in the back gold layer, and the four open slots are located on two diagonal lines of the back gold layer to form an X-shaped pattern.
As a further improvement of an embodiment of the present invention, the four open slots are all two annular open slots with side edges parallel to the two arc-shaped end portions.
As a further improvement of the embodiment of the present invention, one end of the annular open slot forms an opening at the edge of the second surface of the back gold layer.
As a further improvement of one embodiment of the invention, the maximum width of the annular opening groove does not exceed 2 mm.
As a further improvement of an embodiment of the present invention, a polymer heat dissipation dielectric film or a polymer composite material layer with a filler is further disposed between the second surface of the chip and the first surface of the back gold layer.
An embodiment of the present invention further provides a chip packaging method, including: covering the back gold layer on the second surface of the chip, so that the first surface of the back gold layer is close to the chip and the second surface of the back gold layer is far away from the chip; and carrying out laser cutting on the second surface of the back gold layer to form at least one open slot, so that the open slot penetrates through the back gold layer in the direction towards the chip and the position of at least part of the open slot is opposite to the second surface of the chip.
As a further improvement of an embodiment of the present invention, the method further comprises: and forming a polymer heat dissipation dielectric film or a polymer composite material layer with filler on the second surface of the chip.
As a further improvement of an embodiment of the present invention, the method further comprises: and covering the high-temperature thinning support film or the high-temperature temporary bonding carrier plate on the first surface of the chip.
As a further improvement of an embodiment of the present invention, the method further comprises: and carrying out plasma cleaning on the second surface of the back gold layer.
Compared with the prior art, the invention has the beneficial effects that: the second surface of the chip is provided with a back gold layer, an open slot penetrating the back gold layer is formed in the back gold layer, and at least part of the open slot is opposite to the second surface of the chip, so that the adverse stress damage of the back gold layer to the chip under the action of thermal expansion and cold contraction can be greatly relieved.
Drawings
Fig. 1 is a schematic structural diagram of a chip package structure in embodiment 1 of the present invention;
fig. 2 is a schematic diagram of a pattern formed on the second surface of the back gold layer by the open slot in embodiment 1 of the present invention;
fig. 3 is a schematic diagram of a pattern formed on the second surface of the gold-backed layer by an open slot in embodiment 2 of the present invention;
fig. 4 to 6 are schematic diagrams of other patterns formed on the second surface of the gold-backed layer by the open grooves in embodiment 2 of the present invention;
fig. 7 is a schematic structural diagram of a chip package structure in embodiment 3 of the present invention;
fig. 8 is a flowchart illustrating a chip packaging method according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be clearly and completely described below with reference to the detailed description of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
Structures or devices may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As in the present invention, for convenience of description, in the chip package structure, one side of the chip away from the back gold layer is the front side of the chip, and the opposite side thereof close to the back gold layer is the back side of the chip; the direction of the plane where the chip is located is the horizontal direction, and the direction perpendicular to the plane where the chip is located is the vertical direction.
As shown in fig. 1 to 6, an embodiment of the present invention provides a chip package structure, including a chip 1 and a back gold layer 5, where the chip 1 includes a chip first surface 11 and a chip second surface 12 that are oppositely disposed, the back gold layer 5 covers the chip second surface 12, the back gold layer 5 includes a back gold layer first surface 51 close to the chip 1 and a back gold layer second surface 52 far away from the chip, at least one open slot 7 is formed in the back gold layer 5, the open slot 7 penetrates through the back gold layer 5 in a direction toward the chip 1, and at least a portion of the open slot 7 faces the chip second surface 12.
Specifically, the chip package structure in this embodiment may be formed by cutting the wafer level package structure, that is, after the wafer level package structure is packaged, the wafer level package structure may be cut by laser to form a granular independent chip package structure, and meanwhile, the chip package structure is cut into a square shape. The chip packaging structure comprises a chip 1 and a back gold layer 5, wherein the back gold layer 5 can completely cover the back surface of the chip 1; the back surface of the chip 1 is defined as a chip second surface 12, and the other surface of the chip 1, which is arranged opposite to the chip first surface 11; one surface of the back gold layer 5 close to the chip 1 is a back gold layer first surface 51, and the other surface of the back gold layer 5 far from the chip 1 is a back gold layer second surface 52.
The thermal expansion coefficient of the back gold layer 5 is different from that of the chip 1, and the back gold layer 5 may generate large stress on the chip 1 under the action of thermal expansion and contraction. A through opening groove 7 is formed in the back gold layer 5, the opening groove 7 is located on the second surface 12 of the chip, a part of the structure of the opening groove 7 may be located on the second surface 12 of the chip, or the whole structure of the opening groove 7 may be located on the second surface 12 of the chip, so that the positions of at least part of the opening groove 7 and the second surface 12 of the chip correspond to each other; the back gold layer 5 is divided into a plurality of blocks by the open slot 7, when the back gold layer 5 is subjected to the action of expansion with heat and contraction with cold, the thermal stress transmitted along the plane direction of the back gold layer 5 or the thickness direction of the back gold layer 5 can be effectively blocked by the open slot 7, so that the deformation quantity of the back gold layer 5 caused by expansion with heat and contraction with cold is extremely small, the stress action on the second surface 12 of the chip after deformation is also greatly reduced, and the chip 1 is extremely small in adverse stress influence.
Alternatively, a plurality of open grooves 7 may be provided to divide the back au layer 5 into a plurality of discrete portions to quickly reduce the thermal stress effect of the back au layer 5. The section shape of the open slot 7 on the section of the back metal layer 5 is not limited, and the open slot can be vertically arranged or obliquely arranged; to facilitate laser cutting, the opening grooves 7 may be formed parallel to the thickness direction of the back metal layer 5 and have a rectangular cross section.
Further, two or more open grooves 7 are formed in the back gold layer 5, and the two or more open grooves 7 are distributed in a central symmetry manner with respect to the center of the second surface 52 of the back gold layer.
Specifically, the number of the open grooves 7 is two or more, and the whole is centrosymmetric with the center of the second surface 52 of the back gold layer as the center. From this, two or more open slots 7 can be cut apart into a plurality of parts with back gold layer 5, and a plurality of part centrosymmetries, the stress of back gold layer 5 when expend with heat and contract with cold is dispersed or cut off by the symmetry to the stress action can reduce fast, and the adverse stress influence that chip 1 received can be alleviated or eliminated fast.
Alternatively, the open grooves 7 may be formed on the second surface 52 of the gold-backed layer in a closed pattern or an open line segment.
Furthermore, four open slots 7 are formed in the back gold layer 5, and the four open slots 7 are located on two central axes of the back gold layer 5 to form a cross-shaped pattern.
Furthermore, four open grooves 7 are formed in the back gold layer 5, and the four open grooves 7 are located on two diagonal lines of the back gold layer 5 to form an X-shaped pattern.
Furthermore, the four open grooves 7 are two annular open grooves 7 with the side edges parallel to the two arc-shaped end parts.
In order to facilitate the processing and achieve the best effect, four open slots 7 can be uniformly arranged on two central axes or two diagonal lines of the back metal layer 5. The four open slots 7 are all annular open slots 7, the shape of each open slot is similar to that of a playground runway, two side edges of each annular open slot 7 are parallel to each other, and two ends of each annular open slot 7 are transition arcs.
When the four annular open grooves 7 are uniformly arranged on two central axes of the back gold layer 5, a cross-shaped pattern can be formed together. When the annular open grooves 7 are uniformly arranged on two diagonal lines of the back gold layer 5, an X-shaped pattern is formed. From this, only need to open four annular open slots 7 in back of the body gold layer 5, can cut apart into five independent parts with back of the body gold layer 5, can greatly cushion the stress effect that expend with heat and contract with cold and bring, and the stress relieving effect is splendid, and processing is simple and convenient simultaneously.
Alternatively, the annular shape formed by the open groove 7 on the second surface 52 of the gold-backed layer may also be a hollow circle, a hollow square, or the like. Meanwhile, the pattern of the open groove 7 may be not only a ring shape but also an arc shape, a part of a hollow square shape, a part of a hollow oval shape, or the like.
Further, one end of the annular opening groove 7 is opened at the edge of the second surface 52 of the back gold layer.
Further, the maximum width of the annular opening groove 7 is not more than 2 mm.
Specifically, one end of the annular opening 7 is exposed from the edge of the second surface 52 of the back gold layer, so as to form an opening or a gap which is open to the external environment. When the annular open slot 7 is filled with the colloid in the subsequent process, the air in the colloid can be smoothly discharged to the external environment from the position of the opening or the notch, so that the air content in the colloid is reduced, the bonding performance of the colloid is improved, and the process performance of the packaging structure is finally ensured.
In addition, to ensure that the stress applied to the chip 1 is minimized, the size of the annular opening 7 may be limited, specifically, the maximum width of the annular opening 7 is within 3mm, and when the maximum width does not exceed 2mm, the stress application and adverse stress damage effects are minimized.
Alternatively, the pattern formed by the open slot 7 on the second surface 52 of the gold-backed layer may also be a completely closed pattern, such as a hollow circle or a hollow square, which may be located at the center of the second surface 52 of the gold-backed layer and completely closed. Therefore, the back gold layer 5 can be divided into two or more independent parts which are completely disconnected, and under the action of thermal expansion and cold contraction, the stress transmitted inside the back gold layer 5 is directly blocked by the open groove 7, so that the overall stress of the back gold layer 5 is greatly reduced.
Further, a polymer heat dissipation dielectric film 9 or a polymer composite material layer 9 with filler is disposed between the chip second surface 12 and the back gold layer first surface 51.
Specifically, before the back gold layer 5 is covered, the second surface 12 of the chip may be further provided with a thin polymer heat dissipation dielectric film 9 or a polymer composite material layer 9 with a filler, which not only plays a certain role in insulation and buffering, but also protects the chip 1 and prevents the chip 1 from being touched or even cut due to an excessively large depth when the opening groove 7 is formed by subsequent laser.
For ease of understanding, examples are described in detail below:
example 1
As shown in fig. 1 to 2, the chip package structure in this embodiment includes a chip 1 and a back gold layer 5, the chip 1 includes a chip first surface 11 and a chip second surface 12 that are disposed opposite to each other, the back gold layer 5 covers the chip second surface 12, and the back gold layer 5 includes a back gold layer first surface 51 close to the chip 1 and a back gold layer second surface 52 far from the chip 1.
Four open slots 7 are uniformly arranged on two central axes of the back gold layer 5, and the four open slots 7 form a cross-shaped pattern together. The four open slots 7 are all annular and form an annular shape similar to the shape of a playground runway, two side edges of the annular open slots 7 are parallel to each other, and two ends of the annular open slots 7 are arc-shaped.
The back gold layer 5 is divided into five independent parts by the four annular open grooves 7, stress generated by the back gold layer 5 under the action of expansion with heat and contraction with cold is quickly buffered by the annular open grooves 7, the stress relieving effect is excellent, and the processing technology is simple and convenient.
Meanwhile, one end of the annular opening groove 7 is exposed from the edge of the second surface 52 of the back gold layer, so as to form an opening or a gap which is open towards the external environment. When the annular open slot 7 is filled with the colloid in the subsequent process, air in the colloid can be smoothly discharged to the external environment from the position of the opening or the notch, so that the adhesive property of the colloid can be improved, and the process property of the packaging structure can be ensured.
Example 2
As shown in fig. 3, the chip package structure in this embodiment also includes a chip 1 and a back gold layer 5, and is different from embodiment 1 in that four open slots 7 are uniformly formed on two diagonal lines of the back gold layer 5, and the four open slots 7 form an X-shaped pattern together.
Further, as shown in fig. 4 to 6, the annular shape of the open groove 7 formed on the gold-backed layer second surface 52 may also be a hollow circle, a hollow square, or the like. Meanwhile, the pattern of the open groove 7 may be not only a ring shape but also an arc shape, a part of a hollow square shape, a part of a hollow oval shape, or the like.
Example 3
As shown in fig. 7, the chip package structure in this embodiment also includes a chip 1 and a back gold layer 5, and unlike embodiment 1, the package structure further includes a polymer heat dissipation dielectric film 9 or a polymer composite material layer 9 with a filler, which is disposed between the chip second surface 12 and the back gold layer first surface 51. The thin polymer heat dissipation dielectric film 9 or the polymer composite material layer 9 with the filler not only plays a certain role in insulation and buffering, but also can protect the chip 1 and prevent the chip 1 from being touched and even cut due to overlarge depth when the opening groove 7 is formed by subsequent laser.
As shown in fig. 8, an embodiment of the present invention further provides a chip packaging method, where the method includes the following steps, which are specifically described below:
s02, the back gold layer 5 is covered on the second surface 12 of the chip such that the first surface 51 of the back gold layer is close to the chip 1 and the second surface 52 of the back gold layer is far from the chip 1.
Specifically, the chip packaging structure comprises a chip 1 and a back gold layer 5, wherein the chip 1 comprises a chip first surface 11 and a chip second surface 12 which are oppositely arranged, the back gold layer 5 covers the chip second surface 12, and the back gold layer 5 comprises a back gold layer first surface 51 close to the chip 1 and a back gold layer second surface 52 far away from the chip 1.
In the packaging process, the back gold layer 5 is covered on the second surface 12 of the chip, so that the first surface 51 of the back gold layer is close to the chip 1 and the second surface 52 of the back gold layer is far away from the chip 1. The material of the back gold layer 5 is not limited, and can be formed by laminating a plurality of metals, so that the thermal resistance of the chip 1 is effectively reduced, and the heat dissipation efficiency of the chip 1 is improved.
And S04, performing laser cutting on the second surface 52 of the back gold layer to form at least one open slot 7, so that the open slot 7 penetrates through the back gold layer 5 in the direction towards the chip 1 and the position of at least part of the open slot 7 is opposite to the second surface 12 of the chip.
Specifically, the thermal expansion coefficient of the back gold layer 5 is different from that of the chip 1, and the back gold layer 5 may generate a large stress on the chip 1 under the action of thermal expansion and cold contraction. In order to eliminate or relieve the stress, at least one through opening groove 7 is formed in the back gold layer 5, the opening groove 7 is located on the second surface 12 of the chip, a part of the structure of the opening groove 7 may be located on the second surface 12 of the chip, or the whole structure of the opening groove 7 may be located on the second surface 12 of the chip, so that the position of at least part of the opening groove 7 corresponds to the second surface 12 of the chip; the back gold layer 5 is divided into a plurality of blocks by the open slot 7, and when the back gold layer 5 is subjected to expansion with heat and contraction with cold, the thermal stress transmitted along the plane direction of the back gold layer 5 or the thickness direction of the back gold layer can be effectively blocked by the open slot 7, so that the deformation quantity of the back gold layer 5 caused by expansion with heat and contraction with cold is extremely small, the stress action on the second surface 12 of the chip after deformation is also greatly reduced, and the chip 1 is extremely small in adverse stress influence.
Alternatively, a plurality of open grooves 7 may be provided to divide the back au layer 5 into a plurality of discrete portions to quickly reduce the thermal stress effect of the back au layer 5. The section shape of the open slot 7 on the section of the back metal layer 5 is not limited, and the open slot can be vertically arranged or obliquely arranged; to facilitate laser cutting, the opening grooves 7 may be formed parallel to the thickness direction of the back metal layer 5 and have a rectangular cross section.
Further, before step S02, the method further includes:
and S011, forming a polymer heat dissipation dielectric film 9 or a polymer composite material layer 9 with filler on the second surface of the chip.
Specifically, before the back gold layer 5 is covered, the second surface 12 of the chip may be further provided with a thin polymer heat dissipation dielectric film 9 or a polymer composite material layer 9 with a filler, which not only plays a certain role in insulation and buffering, but also protects the chip 1 and prevents the chip 1 from being touched or even cut due to an excessively large depth when the opening groove 7 is formed by subsequent laser.
Further, before step S02, the method further includes:
and S013, covering the high-temperature thinning support film or the high-temperature temporary bonding carrier plate on the first surface 11 of the chip.
Specifically, before the second surface 12 of the chip is covered with the back gold layer 5, a high temperature thinning support film or a high temperature temporary bonding carrier plate may be covered on the first surface 11 of the chip, so as to protect and fix the chip 1, and enhance the overall strength of the chip 1, so as to perform subsequent process processing on the second surface 12 of the chip for the structures such as the back gold layer 5 or the polymer heat dissipation dielectric film 9. Meanwhile, after the subsequent process is finished, the high-temperature thinning support film or the high-temperature temporary bonding support plate can be removed in time.
Further, after step S04, the method further includes:
s05: the back gold layer second surface 52 is plasma cleaned.
Specifically, after all the open grooves 7 are cut by the laser, the second surface 52 of the back gold layer can be subjected to a plasma cleaning process to remove metal chips and impurities generated by cutting, so that the chip packaging structure is kept clean, and the subsequent processing process is facilitated.
The packaging method of the chip packaging structure is generally described as follows:
when the chip packaging structure is packaged, a layer of high-temperature thinning support film or high-temperature temporary bonding support plate is covered on the first surface 11 of the chip; next, a thin polymer heat dissipation dielectric film 9 or a polymer composite material layer 9 with filler is disposed on the second surface 12 of the chip in advance, and then the back gold layer 5 is covered to make the back gold layer 5 cover the second surface 12 of the chip.
After the back gold layer 5 is covered, laser lithography is performed on the back gold layer second surface 52 to form at least one open slot 7 penetrating through the back gold layer 5, and the positions of at least part of the open slots 7 are opposite to the chip second surface 12. After all the open grooves 7 are cut by the laser, the second surface 52 of the back gold layer is subjected to a plasma cleaning process to remove metal chips and impurities generated by cutting.
In addition, the chip package structure may be a wafer level package structure, and the wafer level package structure may be cut and separated by laser cutting to form a granular independent package chip structure.
In summary, in the chip package structure provided by the present invention, the back gold layer 5 covers the second surface 12 of the chip, at least one opening groove 7 extending toward the chip 1 and penetrating through the back gold layer 5 is formed in the back gold layer 5, and the position of at least a portion of the opening groove 7 faces the second surface 12 of the chip, so as to buffer the stress action generated by the back gold layer 5 at the corresponding position under the action of thermal expansion and cold contraction, thereby eliminating the adverse stress damage caused by the stress action to the chip 1.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention and is not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention are included in the scope of the present invention.
Claims (12)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113629021A (en) * | 2021-08-09 | 2021-11-09 | 长江存储科技有限责任公司 | Semiconductor device package structure and manufacturing method thereof |
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