CN112511134B - Clock signal circuit for correcting high duty ratio - Google Patents
Clock signal circuit for correcting high duty ratio Download PDFInfo
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- CN112511134B CN112511134B CN202011433747.8A CN202011433747A CN112511134B CN 112511134 B CN112511134 B CN 112511134B CN 202011433747 A CN202011433747 A CN 202011433747A CN 112511134 B CN112511134 B CN 112511134B
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- 239000003990 capacitor Substances 0.000 claims description 10
- 230000003247 decreasing effect Effects 0.000 claims description 3
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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Abstract
The invention discloses a clock signal circuit for correcting a high duty ratio, and relates to the technical field of integrated circuits. The circuit comprises a first inverter, a second inverter, a first current mirror module, a second current mirror module, a first control field effect transistor, a second control field effect transistor and a third control field effect transistor; the first inverter is connected to the signal input end and the second inverter respectively, and the second inverter is connected to the signal output end; the first control field effect transistor is connected with the first inverter, the second control field effect transistor, the third control field effect transistor, the first current mirror module and the second current mirror module; the second control field effect transistor and the third control field effect transistor are connected to the signal output end; the first current mirror module is connected with the second control field effect transistor, and the second current mirror module is connected with the third control field effect transistor. According to the technical scheme, the current of the mirror images of the first control field effect transistor and the second current mirror module is controlled, so that the duty ratio of the waveform output by the signal output end is accurately controlled.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a clock signal circuit for correcting a high duty cycle.
Background
In modern circuitry, the most commonly used signal for clocking signals may be generated by a crystal oscillator or by an RC oscillator. Different circuit blocks have different requirements on the clock signal. For example, analog-to-digital converters require that the jitter on the edges of the input clock signal be particularly small, that the frequency of the input clock signal be very stable in a real-time clock circuit (RTC), that the Mixer (Mixer) in some rf circuits require that the clock signal generated by the local oscillator have a duty cycle other than 50% in order to achieve the goal of increasing the conversion gain, and that the duty cycle of the clock signal be 50% in a double frequency circuit. In the prior art, the quality of the clock signal generated by the crystal oscillator or the RC oscillator is sometimes not good, and the clock duty ratio is poor.
Disclosure of Invention
The invention mainly aims to provide a clock signal circuit for correcting high duty ratio, which aims to accurately control the duty ratio of an output clock signal waveform.
In order to achieve the above object, the present invention provides a clock signal circuit for correcting a high duty ratio, the circuit including a first inverter, a second inverter, a first current mirror module, a second current mirror module, and a first control fet, a second control fet, and a third control fet;
the first inverter is respectively connected with the signal input end and the second inverter, and the second inverter is connected with the signal output end; the first control field effect transistor is connected with the first inverter, the second control field effect transistor, the third control field effect transistor, the first current mirror module and the second current mirror module; the second control field effect transistor and the third control field effect transistor are connected to the signal output end; the first current mirror module is connected with the second control field effect transistor, and the second current mirror module is connected with the third control field effect transistor and is also connected with a first current source and a second current source;
the first inverter receives a clock signal and sends the clock signal after reverse to the second inverter, the second control field effect transistor and the third control field effect transistor respectively receive signals output by the second inverter and are switched on/off according to the signals, the first current mirror module mirrors the current of the current source to the second control field effect transistor, the second current mirror module mirrors the current of the current source to the third control field effect transistor, and the duty ratio of the signals output by the signal output end is controlled by controlling the mirror currents of the first current mirror module and the second current mirror module;
the first control field effect transistor is connected with the second control field effect transistor and the third control field effect transistor, and the grid voltage of the first control field effect transistor is increased or decreased through on/off of the second control field effect transistor and the third control field effect transistor, so that circuit feedback is formed.
Preferably, the first control field effect transistor is an NMOS field effect transistor; the second control field effect transistor is a PMOS field effect transistor; the third control field effect transistor is an NMOS field effect transistor.
Preferably, the drain electrode of the first control field effect transistor is connected with the first inverter, the grid electrode of the first control field effect transistor is connected with the drain electrodes and the source electrodes of the second control field effect transistor and the third control field effect transistor, and the drain electrodes and the source electrodes of the second control field effect transistor and the third control field effect transistor are grounded; the source electrode of the second control field effect transistor is connected with the first current mirror module, the grid electrode of the second control field effect transistor is connected with the signal output end and the second inverter, and the drain electrode of the second control field effect transistor is connected with the first current mirror module and the second current mirror module; and the grid electrode of the third control field effect transistor is connected with the signal output end and the second inverter, the source electrode of the third control field effect transistor is connected with the second current mirror module, and the drain electrode of the third control field effect transistor is connected with the first current mirror module and the second current mirror module.
Preferably, the circuit further comprises a first capacitor, one end of the first capacitor is connected to a power supply, and the other end of the first capacitor is connected to the grid electrode of the first control field effect transistor, the second control field effect transistor and the drain electrode of the third control field effect transistor.
Preferably, the first inverter includes a first PMOS transistor and a first NMOS transistor, where gates of the first PMOS transistor and the first NMOS transistor are connected to each other and to the signal input terminal; the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and the second inverter; the source electrode of the first NMOS tube is connected with the drain electrode of the first control field effect tube.
Preferably, the second inverter includes a second PMOS transistor and a second NMOS transistor; the grid electrodes of the second PMOS tube and the second NMOS tube are connected with each other and connected with the drain electrodes of the first PMOS tube and the first NMOS tube; the drains of the second PMOS tube and the second NMOS tube are connected with each other and are connected with the signal output end, the grid electrode of the second control field effect tube and the grid electrode of the third control field effect tube; the source electrode of the second PMOS tube is connected to a power supply, and the source electrode of the second NMOS tube is grounded.
Preferably, the first current mirror includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor, gates of the third PMOS transistor, the fourth PMOS transistor, and the seventh PMOS transistor are connected to each other, a drain of the third PMOS transistor is connected to a source of the second control field effect transistor, and a drain of the fourth PMOS transistor is connected to the second current mirror module, a drain of the second control field effect transistor, and a drain of the third control field effect transistor; the source electrode of the seventh PMOS tube is connected with a power supply, and the drain electrode of the seventh PMOS tube is connected with the second current mirror module;
the grid electrodes of the fifth PMOS tube and the sixth PMOS tube are connected with each other and are connected with the drain electrodes of the second current mirror module, the second control field effect tube and the third control field effect tube; the sources of the fifth PMOS tube and the sixth PMOS tube are connected to a power supply; the drain electrode of the fifth PMOS tube is connected with the source electrode of the third PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the fourth PMOS tube.
Preferably, the second current mirror comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;
the ninth NMOS tube is connected with a first current source, the current of the first current source is mirrored to the seventh NMOS tube, and the current is mirrored to a branch where the third NMOS tube is located through the seventh NMOS tube;
the tenth NMOS tube is connected to the second current source, and mirrors the current of the second current source to the branch where the fourth NMOS tube is located, and then mirrors the current to the branch where the third PMOS tube is located through the fourth PMOS tube.
Preferably, the gate of the third NMOS transistor is connected to the gates of the fourth NMOS transistor, the fifth NMOS transistor, and the tenth NMOS transistor; the drain electrode of the third NMOS tube is connected with the source electrode of the third control field effect tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the sixth NMOS tube;
the drain electrode of the fourth NMOS tube is connected with the first capacitor, the drain electrode of the fourth PMOS tube, the grid electrode of the first control field effect tube, the drain electrode of the second control field effect tube and the drain electrode of the third control field effect tube; the source electrode of the fourth NMOS tube is connected with the drain electrode of the seventh NMOS tube;
the drain electrode of the fifth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the eighth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the grid electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube;
the drain electrode of the ninth NMOS tube is connected with the first current source, and the drain electrode of the tenth NMOS tube is connected with the second current source; the sources of the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube and the tenth NMOS tube are grounded.
According to the technical scheme, reference current is poured from a current source, then the first current mirror module and the second current mirror module mirror images the branches where the second control field effect transistor and the third control field effect transistor are located, and the duty ratio of waveforms output by the signal output end is accurately controlled by controlling the mirrored current of the first control field effect transistor and the second current mirror module.
Drawings
FIG. 1 is a circuit diagram of a clock signal circuit for correcting a high duty cycle according to the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention is further described below with reference to the accompanying drawings.
The embodiment of the invention provides a clock signal circuit for correcting a high duty ratio, which is used for adjusting an input clock signal with the high duty ratio so as to output the clock signal with the duty ratio required by a subsequent circuit.
As shown in fig. 1, a clock signal circuit for correcting a high duty ratio according to an embodiment of the present invention includes a first inverter, a second inverter, a first current mirror module, a second current mirror module, a first control fet M1, a second control fet M2, and a third control fet M3; the first inverter is respectively connected to the signal input end IN and the second inverter, and the second inverter is connected to the signal output end OUT; the first control field effect transistor M1 is connected to the first inverter, the second control field effect transistor M2, the third control field effect transistor M3, the first current mirror module and the second current mirror module; the second control field effect transistor M2 and the third control field effect transistor M3 are connected to the signal output end OUT; the first current mirror module is connected with the second control field effect transistor M2, and the second current mirror module is connected with the third control field effect transistor M3 and is also connected with a first current source I1 and a second current source I2; the first inverter receives a clock signal and sends the clock signal after reverse to the second inverter, the second control field effect transistor M2 and the third control field effect transistor M3 respectively receive signals output by the second inverter and are switched on/off according to the signals, the first current mirror module mirrors the current of the current source to the second control field effect transistor M2, the second current mirror module mirrors the current of the current source to the third control field effect transistor M3, and the duty ratio of the signals output by the signal output end OUT is controlled by controlling the mirror currents of the first current mirror module and the second current mirror module; the first control fet M1 is connected to the second control fet M2 and the third control fet M3, and the gate voltage of the first control fet M1 is increased or decreased by on/off of the two to form a circuit feedback.
Specifically, as shown IN fig. 1, the signal input terminal IN inputs a clock signal of a high duty ratio, and the signal output terminal OUT outputs an adjusted clock signal. The clock signal with high duty ratio enters the input end of the first inverter, and due to the high duty ratio, the input clock signal has a long time period with high level and a short time period with low level, so that after passing through the first inverter, the point A is discharged, the voltage of the point A is reduced, and after passing through the second inverter, the voltage of the signal output end OUT is in high level for a long time, so that the third control field effect transistor M3 is turned on. When the current of the branch of the first current mirror module is smaller than that of the branch of the second current mirror module, the voltage of the point Vcntl is reduced, so that the Gate voltage of the first control field effect tube M1 is reduced, the current flowing through the first control field effect tube M1 is reduced, the falling time of the point A is slower, the time of the point A at a high level is longer, the low level time of the signal output end OUT is prolonged, at the moment, the second control field effect tube M2 is opened, the voltage of the point Vcntl is increased, the Gate voltage of the first control field effect tube M1 is increased, the current flowing through the first control field effect tube M1 is increased, and the voltage of the point A is increased, so that negative feedback is formed.
And the reference current is poured into the first current source I1 and the second current source I2, and then the first current mirror module and the second current mirror module mirror the branches where the second control field effect transistor M2 and the third control field effect transistor M3 are located. The duty ratio of the waveform output by the control signal output end OUT is achieved by controlling the current of the mirror images of the first control field effect transistor M1 and the second current mirror module.
Preferably, as shown in fig. 1, the first control fet M1 is an NMOS fet; the second control field effect transistor M2 is a PMOS field effect transistor; the third control fet M3 is an NMOS fet. The drain electrode of the first control field effect tube M1 is connected with the first inverter, the grid electrode of the first control field effect tube M1 is connected with the drain electrodes and the source electrodes of the second control field effect tube M2 and the third control field effect tube M3, and the drain electrodes and the source electrodes are grounded; the source electrode of the second control field effect transistor M2 is connected with the first current mirror module, the grid electrode is connected with the signal output end OUT and the second inverter, and the drain electrode is connected with the first current mirror module and the second current mirror module; and the grid electrode of the third control field effect transistor M3 is connected with the signal output end OUT and the second inverter, the source electrode of the third control field effect transistor M is connected with the second current mirror module, and the drain electrode of the third control field effect transistor M is connected with the first current mirror module and the second current mirror module. The rising and falling time of the clock signal waveform can be controlled by the first control field effect transistor M1.
Preferably, as shown in fig. 1, the circuit further includes a first capacitor C1, where one end of the first capacitor C1 is connected to a power supply, and the other end is connected to the gate of the first control fet M1, the drain of the second control fet M2, and the drain of the third control fet M3. The first capacitor C1 is used to stabilize the point voltage of the point B.
Preferably, as shown IN fig. 1, the first inverter includes a first PMOS transistor Mp1 and a first NMOS transistor Mn1, where gates of the first PMOS transistor Mp1 and the first NMOS transistor Mn1 are connected to each other and to the signal input terminal IN; the source electrode of the first PMOS tube Mp1 is connected with a power supply, and the drain electrode of the first PMOS tube Mp1 is connected with the drain electrode of the first NMOS tube Mn1 and the second inverter; the source electrode of the first NMOS transistor Mn1 is connected to the drain electrode of the first control FET M1.
Preferably, as shown in fig. 1, the second inverter includes a second PMOS transistor Mp2 and a second NMOS transistor Mn2; the gates of the second PMOS transistor Mp2 and the second NMOS transistor Mn2 are connected to each other and to the drains of the first PMOS transistor Mp1 and the first NMOS transistor Mn 1; the drains of the second PMOS transistor Mp2 and the second NMOS transistor Mn2 are connected to each other and to the signal output terminal OUT, the gate of the second control fet M2, and the gate of the third control fet M3; the source electrode of the second PMOS transistor Mp2 is connected to a power supply, and the source electrode of the second NMOS transistor Mn2 is grounded.
Preferably, as shown in fig. 1, the first current mirror includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a seventh PMOS transistor MP7, gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the seventh PMOS transistor MP7 are connected to each other, a drain of the third PMOS transistor MP3 is connected to a source of the second control field effect transistor M2, and a drain of the fourth PMOS transistor MP4 is connected to the second current mirror module, a drain of the second control field effect transistor M2, and a drain of the third control field effect transistor M3; the source electrode of the seventh PMOS tube Mp7 is connected with a power supply, and the drain electrode of the seventh PMOS tube Mp7 is connected with a second current mirror module; the gates of the fifth PMOS transistor Mp5 and the sixth PMOS transistor Mp6 are connected to each other and to the drains of the second current mirror module, the second control fet M2, and the third control fet M3; the sources of the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are connected to a power supply; the drain electrode of the fifth PMOS transistor Mp5 is connected to the source electrode of the third PMOS transistor Mp3, and the drain electrode of the sixth PMOS transistor Mp6 is connected to the source electrode of the fourth PMOS transistor Mp 4. The double layer current mirror makes the circuit more stable.
Preferably, as shown in fig. 1, the second current mirror includes a third NMOS transistor Mn3, a fourth NMOS transistor Mn4, a fifth NMOS transistor Mn5, a sixth NMOS transistor Mn6, a seventh NMOS transistor Mn7, an eighth NMOS transistor Mn8, a ninth NMOS transistor Mn9, and a tenth NMOS transistor Mn10; the ninth NMOS transistor Mn9 is connected to the first current source I1, mirrors the current of the first current source I1 to the seventh NMOS transistor Mn7, and mirrors the current to the branch where the third NMOS transistor Mn3 is located through the seventh NMOS transistor Mn 7; the tenth NMOS transistor Mn10 is connected to the second current source I2, mirrors the current of the second current source I2 to the branch where the fourth NMOS transistor Mn4 is located, and mirrors the current to the branch where the third PMOS transistor Mp3 is located through the fourth PMOS transistor Mp 4. The double layer current mirror makes the circuit more stable.
Preferably, as shown in fig. 1, the gate of the third NMOS transistor Mn3 is connected to the gates of the fourth NMOS transistor Mn4, the fifth NMOS transistor Mn5, and the tenth NMOS transistor Mn10; the drain electrode of the third NMOS tube Mn3 is connected with the source electrode of the third control field effect tube M3, and the source electrode is connected with the drain electrode of the sixth NMOS tube Mn 6; the drain electrode of the fourth NMOS Mn4 is connected to the first capacitor C1, the drain electrode of the fourth PMOS Mp4, the gate electrode of the first control fet M1, the drain electrode of the second control fet M2, and the drain electrode of the third control fet M3; the source electrode of the fourth NMOS tube Mn4 is connected with the drain electrode of the seventh NMOS tube Mn 7; the drain electrode of the fifth NMOS tube Mn5 is connected with the drain electrode of the seventh PMOS tube MP7, and the source electrode is connected with the drain electrode of the eighth NMOS tube Mn 8; the grid electrode of the sixth NMOS tube Mn6 is connected with the grid electrodes of the seventh NMOS tube Mn7, the eighth NMOS tube Mn8 and the ninth NMOS tube Mn 9; the drain electrode of the ninth NMOS tube Mn9 is connected to the first current source I1, and the drain electrode of the tenth NMOS tube Mn10 is connected to the second current source I2; the sources of the sixth NMOS tube Mn6, the seventh NMOS tube Mn7, the eighth NMOS tube Mn8, the ninth NMOS tube Mn9 and the tenth NMOS tube Mn10 are grounded.
The circuit principle of the embodiment of the invention is as follows:
the clock signal with high duty ratio enters the input end of the first inverter consisting of the first PMOS tube MP1 and the first NMOS tube Mn1, and because of the high duty ratio, the input clock signal is in a long high-level time period and a short low-level time period, so that after passing through the first inverter, the discharge time of the point A is longer through the first NMOS tube Mn1, the voltage of the point A is gradually reduced, and then the voltage of the signal output end OUT is in a higher state for a longer time through the second inverter consisting of the second PMOS tube MP2 and the second NMOS tube Mn 2. At this time, the third control fet M3 is turned on. When the branch current of the first current mirror module is smaller than that of the second current mirror module, the voltage of the point Vcntl is reduced, so that the Gate voltage of the first control field effect transistor M1 is reduced, the current flowing through the first control field effect transistor M1 is reduced, the falling time of the point A is slower, the time of the point A at a high level is longer, the low level time of the signal output end OUT is prolonged, at the moment, the second control field effect transistor M2 is opened, the voltage of the point Vcntl is increased, the Gate voltage of the first control field effect transistor M1 is increased, the current flowing through the first control field effect transistor M1 is increased, and the voltage of the point A is increased, so that negative feedback is formed.
The third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5 and the sixth PMOS tube MP6 form a PMOS current mirror structure, the third NMOS tube Mn3, the fourth NMOS tube Mn4, the sixth NMOS tube Mn6 and the seventh NMOS tube Mn7 form an NMOS current mirror structure, reference current is poured into the first current source I1 and the second current source I2, and then the reference current is mirrored to a branch where the third PMOS tube MP3 and the third NMOS tube Mn3 are located. The branch circuit where the seventh PMOS transistor Mp7, the fifth NMOS transistor Mn5, and the eighth NMOS transistor Mn8 are located provides the bias voltage required by the current mirror. Meanwhile, the grid electrode of the first control field effect tube M1 is connected with the output end of an inverter formed by the second control field effect tube M2 and the third control field effect tube M3. By controlling the current of the mirror images of the first control field effect transistor M1 and the current mirror module, the rising and falling time of the control voltage in each period of the clock signal can be controlled, and the aim of accurately controlling the duty ratio of the waveform output by the signal output end OUT can be achieved.
It should be understood that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes using the descriptions of the present invention and the accompanying drawings, or direct or indirect application in other relevant technical fields, are included in the scope of the present invention.
Claims (9)
1. The clock signal circuit for correcting the high duty ratio is characterized by comprising a first inverter, a second inverter, a first current mirror module, a second current mirror module, a first control field effect transistor, a second control field effect transistor and a third control field effect transistor;
the first inverter is respectively connected with the signal input end and the second inverter, and the second inverter is connected with the signal output end; the first control field effect transistor is connected with the first inverter, the second control field effect transistor, the third control field effect transistor, the first current mirror module and the second current mirror module; the second control field effect transistor and the third control field effect transistor are connected to the signal output end; the first current mirror module is connected with the second control field effect transistor, and the second current mirror module is connected with the third control field effect transistor and is also connected with a first current source and a second current source;
the first inverter receives a clock signal and sends the clock signal after reverse to the second inverter, the second control field effect transistor and the third control field effect transistor respectively receive signals output by the second inverter and are switched on/off according to the signals, the first current mirror module mirrors the current of the current source to the second control field effect transistor, the second current mirror module mirrors the current of the current source to the third control field effect transistor, and the duty ratio of the signals output by the signal output end is controlled by controlling the mirror currents of the first current mirror module and the second current mirror module;
the first control field effect transistor is connected with the second control field effect transistor and the third control field effect transistor, and the grid voltage of the first control field effect transistor is increased or decreased through on/off of the second control field effect transistor and the third control field effect transistor, so that circuit feedback is formed.
2. The high duty cycle corrected clock signal circuit of claim 1, wherein the first control fet is an NMOS fet;
the second control field effect transistor is a PMOS field effect transistor; the third control field effect transistor is an NMOS field effect transistor.
3. The high duty cycle corrected clock signal circuit of claim 2, wherein the drain of the first control fet is connected to the first inverter, the gate is connected to the drains and sources of the second and third control fets are grounded;
the source electrode of the second control field effect transistor is connected with the first current mirror module, the grid electrode of the second control field effect transistor is connected with the signal output end and the second inverter, and the drain electrode of the second control field effect transistor is connected with the first current mirror module and the second current mirror module;
and the grid electrode of the third control field effect transistor is connected with the signal output end and the second inverter, the source electrode of the third control field effect transistor is connected with the second current mirror module, and the drain electrode of the third control field effect transistor is connected with the first current mirror module and the second current mirror module.
4. The high duty cycle corrected clock signal circuit of claim 2, further comprising a first capacitor having one end connected to a power supply and the other end connected to the gates of the first control fet, the second control fet, and the drain of the third control fet.
5. The high duty cycle corrected clock signal circuit of claim 4, wherein the first inverter comprises a first PMOS and a first NMOS, gates of the first PMOS and the first NMOS being connected to each other and to the signal input; the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and the second inverter; the source electrode of the first NMOS tube is connected with the drain electrode of the first control field effect tube.
6. The high duty cycle corrected clock signal circuit of claim 5, wherein the second inverter comprises a second PMOS transistor and a second NMOS transistor; the grid electrodes of the second PMOS tube and the second NMOS tube are connected with each other and connected with the drain electrodes of the first PMOS tube and the first NMOS tube; the drains of the second PMOS tube and the second NMOS tube are connected with each other and are connected with the signal output end, the grid electrode of the second control field effect tube and the grid electrode of the third control field effect tube;
the source electrode of the second PMOS tube is connected to a power supply, and the source electrode of the second NMOS tube is grounded.
7. The clock signal circuit for correcting high duty cycle of claim 4, wherein the first current mirror comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube and a seventh PMOS tube,
the gates of the third PMOS tube, the fourth PMOS tube and the seventh PMOS tube are connected with each other, the drain electrode of the third PMOS tube is connected with the source electrode of the second control field effect tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrodes of the second current mirror module, the second control field effect tube and the third control field effect tube; the source electrode of the seventh PMOS tube is connected with a power supply, and the drain electrode of the seventh PMOS tube is connected with the second current mirror module;
the grid electrodes of the fifth PMOS tube and the sixth PMOS tube are connected with each other and are connected with the drain electrodes of the second current mirror module, the second control field effect tube and the third control field effect tube; the sources of the fifth PMOS tube and the sixth PMOS tube are connected to a power supply; the drain electrode of the fifth PMOS tube is connected with the source electrode of the third PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the fourth PMOS tube.
8. The high duty cycle corrected clock signal circuit of claim 7, wherein the second current mirror comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;
the ninth NMOS tube is connected with the first current source and mirrors the current of the first current source to the sixth NMOS tube so that the first current source mirrors to the branch where the third NMOS tube is located;
the tenth NMOS tube is connected to the second current source, and mirrors the current of the second current source to the branch where the fourth NMOS tube is located, and then mirrors the current to the branch where the third PMOS tube is located through the fourth PMOS tube.
9. The high duty cycle corrected clock signal circuit of claim 8, wherein the gate of the third NMOS transistor is connected to the gates of the fourth NMOS transistor, the fifth NMOS transistor, and the tenth NMOS transistor; the drain electrode of the third NMOS tube is connected with the source electrode of the third control field effect tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the sixth NMOS tube;
the drain electrode of the fourth NMOS tube is connected with the first capacitor, the drain electrode of the fourth PMOS tube, the grid electrode of the first control field effect tube, the drain electrode of the second control field effect tube and the drain electrode of the third control field effect tube; the source electrode of the fourth NMOS tube is connected with the drain electrode of the seventh NMOS tube;
the drain electrode of the fifth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the eighth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the grid electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube;
the drain electrode of the ninth NMOS tube is connected with the first current source, and the drain electrode of the tenth NMOS tube is connected with the second current source; the sources of the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube and the tenth NMOS tube are grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011433747.8A CN112511134B (en) | 2020-12-10 | 2020-12-10 | Clock signal circuit for correcting high duty ratio |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011433747.8A CN112511134B (en) | 2020-12-10 | 2020-12-10 | Clock signal circuit for correcting high duty ratio |
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| CN112511134A CN112511134A (en) | 2021-03-16 |
| CN112511134B true CN112511134B (en) | 2023-07-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5164621A (en) * | 1990-11-06 | 1992-11-17 | Mitsubishi Denki Kabushiki Kaisha | Delay device including generator compensating for power supply fluctuations |
| US6262616B1 (en) * | 1999-10-08 | 2001-07-17 | Cirrus Logic, Inc. | Open loop supply independent digital/logic delay circuit |
| CN102594299A (en) * | 2012-02-03 | 2012-07-18 | 深圳创维－Rgb电子有限公司 | Square-wave generator circuit |
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2020
- 2020-12-10 CN CN202011433747.8A patent/CN112511134B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5164621A (en) * | 1990-11-06 | 1992-11-17 | Mitsubishi Denki Kabushiki Kaisha | Delay device including generator compensating for power supply fluctuations |
| US6262616B1 (en) * | 1999-10-08 | 2001-07-17 | Cirrus Logic, Inc. | Open loop supply independent digital/logic delay circuit |
| CN102594299A (en) * | 2012-02-03 | 2012-07-18 | 深圳创维－Rgb电子有限公司 | Square-wave generator circuit |
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| CN112511134A (en) | 2021-03-16 |
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