CN112510037B - 3D logic chip capacitor circuit, logic chip and electronic equipment - Google Patents

Abstract

The embodiment of the application solves the problems of limited capacitance value of a unit area of a capacitor on a logic chip, high off-chip capacitance cost and complex structure by providing a 3D logic chip capacitance circuit, a logic chip and electronic equipment. The logic chip capacitor circuit may include: logic chip functional circuit and memory chip borrow electric capacity. The memory chip is arranged on the logic chip by a capacitor and is used for providing charges for power consumption elements of the functional circuit of the logic chip.

Description

3D logic chip capacitor circuit, logic chip and electronic device

Technical Field

The embodiments of the present invention relate to the field of chip technology, and in particular, to a 3D logic chip capacitor circuit, a logic chip and an electronic device.

Background technique

With the application of ASIC chips in AI, big data centers, autonomous driving and other technological fields, the market's requirements and functions for chips are also significantly improved. The capacitors integrated on the chip are common devices for various functional circuits of the chip. Logic chips commonly use CMOS (Complementary Metal Oxide Semiconductor) gate capacitors, or MOM (Metal Oxide Metal) metal-oxide-metal capacitors and MIM (Metal Insulator Metal) metal-insulator-metal capacitors. Among them, the capacitance per unit area of MOM capacitors and MIM capacitors is smaller than that of CMOS gate capacitors, generally about 1/3 of CMOS gate capacitors. The CMOS gate capacitor is the capacitance between the gate, source, drain and substrate of the CMOS device. The capacitance per unit area is generally around 11ff/ ^um2 , and the capacitance is significantly affected by voltage.

Therefore, the capacitance per unit area of CMOS gates, MOM capacitors and MIM capacitors widely used in logic chips is relatively limited. Unlike memory chips, the implementation process of logic chips limits the integration of high-capacitance on-chip capacitors on logic chips. When large-capacity on-chip capacitors are needed in logic chip design, they can only occupy a large area of the logic chip. The actual achievable capacitance value in logic chip design is difficult to exceed the nanofarad order.

At present, the required high-capacitance capacitors must be realized through off-chip capacitors, which not only increases the cost, but also greatly restricts the chip design due to the need for external pin connections.

Summary of the invention

A series of simplified concepts are introduced in the summary of the invention, which will be further described in detail in the detailed description. The summary of the invention of the embodiment of the present application does not mean to attempt to define the key features and essential technical features of the technical solution claimed for protection, nor does it mean to attempt to determine the scope of protection of the technical solution claimed for protection.

The embodiments of the present application provide a 3D logic chip capacitor circuit, a logic chip and an electronic device, thereby solving the problem that the capacitance per unit area of the on-chip capacitor of the logic chip is limited, and the off-chip capacitor has high cost and complex structure.

To at least partially solve the above problems, in a first aspect, an embodiment of the present application provides a logic chip capacitor circuit, which may include: a logic chip functional circuit and a storage chip borrowing capacitor,

The storage chip borrowing capacitor is arranged on the logic chip to provide charge for the power consumption components of the functional circuit of the logic chip.

In a first possible implementation of the first aspect, the storage chip borrowing capacitor is a high-density capacitor provided with a high dielectric constant dielectric layer.

In a second possible implementation of the first aspect, the storage chip borrowing capacitor is arranged close to the power-consuming components of the logic chip functional circuit through 3D-IC three-dimensional integrated circuit technology.

In a third possible implementation of the first aspect, the storage chip borrows one or more capacitors.

In a fourth possible implementation of the first aspect, the logic chip functional circuit includes a switched capacitor circuit, and the storage chip borrows capacitors for the switched capacitor circuit.

In a fifth possible implementation of the first aspect, the logic chip functional circuit includes a linear voltage regulator circuit, and the storage chip borrows a capacitor disposed at a voltage output end of the linear voltage regulator circuit.

In a sixth possible implementation of the first aspect, the logic chip functional circuit includes a charge pump circuit, and the storage chip borrowed capacitor is a bootstrap capacitor of the charge pump circuit.

In a second aspect, an embodiment of the present application provides a logic chip, which may include:

The above-mentioned logic chip capacitor circuit.

In a third aspect, an embodiment of the present application provides an electronic device, which may include:

The above-mentioned logic chip and the memory chip provided with the memory chip borrowing capacitor, the logic chip is connected to the memory chip.

In a first possible implementation of the third aspect, the logic chip and the memory chip are connected via 3D-IC three-dimensional integrated circuit technology, wherein a memory chip borrowing capacitor for providing charge to the power-consuming element is arranged at corresponding positions of the logic chip and the power-consuming element.

Compared with the prior art, the logic chip capacitor circuit provided in the embodiment of the present invention has at least the following beneficial effects:

The logic chip capacitor circuit provided by the embodiment of the present invention includes: a logic chip functional circuit and a memory chip borrowing capacitor, wherein the memory chip borrowing capacitor is arranged on the logic chip and is used to provide charge for the power-consuming components of the logic chip functional circuit. Since the logic chip uses the capacitor in the memory chip as a borrowing capacitor to provide charge for the power-consuming components of the logic chip itself. This solves the problem of limited capacitance per unit area of on-chip capacitors very well, while saving the cost of components and improving the response of power supply signals and the functional realization of other functional circuits. In addition, since the on-chip capacitor corresponding to the functional circuit to be provided with charge in the logic chip is borrowed, the problem of high cost and complex structure caused by the need to add external capacitors to increase the capacitance of the on-chip capacitors of the logic chip is avoided.

Correspondingly, the logic chip and electronic device provided by the embodiments of the present invention also have the above technical effects.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work:

FIG1 is a schematic structural block diagram of a logic chip capacitor circuit provided by an embodiment of the present invention;

FIG2 is a circuit topology diagram of a logic chip capacitor circuit provided by an embodiment of the present invention;

FIG3 is a circuit topology diagram of another logic chip capacitor circuit provided by an embodiment of the present invention;

FIG4 is a circuit topology diagram of another logic chip capacitor circuit provided by an embodiment of the present invention;

FIG5 is a schematic structural block diagram of a logic chip provided in an embodiment of the present invention;

FIG6 is a schematic structural block diagram of an electronic device provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention.

Detailed ways

The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments so that those skilled in the art can implement the invention with reference to the description.

It should be understood that terms such as “having”, “including” and “comprising” used herein do not exclude the existence or addition of one or more other elements or combinations thereof.

In addition, it should be noted that, unless otherwise clearly specified and limited, the terms "setting" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an integral connection or the internal connection of two elements. It can also be that signal transmission and data communication can be carried out between the two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

At present, the unit area capacitance values of CMOS gate, MOM capacitor and MIM capacitor widely used in logic chips are relatively limited. Among them, the unit area capacitance of MOM capacitor and MIM capacitor is less than CMOS gate capacitance, generally about 1/3 of CMOS capacitance. And CMOS gate capacitance is the capacitance between gate, source, drain and substrate of CMOS device, generally the unit area capacitance value is about 11ff/ ^um2 , and the capacitance value is obviously affected by voltage. Therefore, and unlike memory chip, the realization process of logic chip limits that it is difficult to integrate high capacitance on-chip capacitor on logic chip. Based on the existing capacitance solution, when large-capacity on-chip capacitor is needed in logic chip design, it is necessary to occupy a large area of logic chip, and the capacitance value that can be actually realized in logic chip design is difficult to exceed the nanofarad order of magnitude.

In view of the above problems, the embodiments of the present application provide a 3D logic chip capacitor circuit, which solves the problem that the capacitance per unit area of the on-chip capacitor of the logic chip is limited, and the off-chip capacitor has high cost and complex structure.

FIG1 is a schematic structural block diagram of a logic chip capacitor circuit provided by an embodiment of the present invention. As shown in FIG1 , the logic chip capacitor circuit 100 may include: a logic chip functional circuit 110 and a storage chip borrowing capacitor 120 .

The storage chip borrowing capacitor 120 is disposed on the logic chip to provide charges for the power-consuming components of the logic chip functional circuit 110 .

Exemplarily, the memory chip borrowing capacitor 120 may be an on-chip capacitor of the memory chip, for example, an on-chip capacitor in a DRAM. When certain conditions are met, the on-chip capacitor in the DRAM may be set in the logic chip and used as a capacitor of the logic chip. That is to say, in this solution, the chip borrowing capacitor 120 is provided by the memory chip to the logic chip for use when the logic chip and the memory chip meet certain position and connection conditions. In addition, exemplarily, in order to achieve high utilization of the capacitor, the chip borrowing capacitor 120 may also be shared by the memory chip and the logic chip when the logic chip and the memory chip meet certain position and connection conditions.

Exemplarily, the storage chip borrowing capacitor 120 can be arranged close to the power-consuming element of the logic chip functional circuit 110, and the pins of the storage chip borrowing capacitor 120 can be arranged around the power-consuming element of the logic chip functional circuit 110, that is, the functional circuit module or the power-consuming element in the module is physically close to the surface of the logic chip. It can also be a connection between element pins, that is, the pins of the storage chip borrowing capacitor 120 are connected to the circuit of the corresponding logic chip functional circuit 110, which plays the role of providing charge to the power-consuming element in the logic chip functional circuit 110 so that the logic chip functional circuit 110 can work normally.

In addition, it should be noted that, whether it is the functional circuit module or the power-consuming element in the module that is physically close to the surface of the logic chip, or the pin of the storage chip borrowing capacitor 120 connected to the corresponding circuit of the logic chip functional circuit 110, the chip borrowing capacitor 120 is provided by the storage chip to the logic chip for use when the logic chip and the storage chip meet certain position and connection conditions. In addition, in order to improve the utilization efficiency of the borrowing capacitor with high capacitance, the chip borrowing capacitor 120 can also be shared by the storage chip and the logic chip when the logic chip and the storage chip meet certain position and connection conditions. Specifically, the above scheme needs to meet the requirement that the pin of the chip borrowing capacitor 120 needs to be connected to the logic chip and the storage chip at the same time.

Therefore, the above-mentioned logic chip capacitor circuit provided by the embodiment of the present invention includes: a logic chip functional circuit and a memory chip borrowing capacitor, and the above-mentioned memory chip borrowing capacitor is arranged on the above-mentioned logic chip, and is used to provide charge for the power-consuming components of the above-mentioned logic chip functional circuit. Since the logic chip uses the capacitor in the memory chip as a borrowing capacitor to provide charge for the power-consuming components of the logic chip itself. The problem of limited capacitance per unit area of on-chip capacitors is solved very well, while saving the cost of original parts and improving the response of power supply signals and the functional realization of other functional circuits. In addition, since the on-chip capacitor corresponding to the functional circuit to be provided with charge in the logic chip is adopted, the problem of high cost and complex structure caused by the need to add external capacitors to increase the capacitance of the on-chip capacitors of the logic chip is avoided.

According to some embodiments, the storage chip borrows capacitors that are high-density capacitors provided with a high-dielectric constant dielectric layer. When an external electric field is applied to the dielectric, an induced charge will be generated to weaken the electric field. The ratio of the original external electric field (in a vacuum) to the electric field in the final dielectric is the dielectric constant (permittivity), also known as the permittivity, which is related to the frequency. The dielectric constant is the product of the relative dielectric constant and the absolute dielectric constant in a vacuum. If a material with a high dielectric constant is placed in an electric field, the strength of the electric field will drop significantly in the dielectric. The polarity of a polymer material can be determined based on the dielectric constant of the substance. Generally, substances with a relative dielectric constant greater than 3.6 are polar substances; substances with a relative dielectric constant in the range of 2.8 to 3.6 are weakly polar substances; and substances with a relative dielectric constant less than 2.8 are non-polar substances.

In some examples, a high-density capacitor constructed with a dielectric layer having a dielectric constant much greater than 3.6 can be selected, for example, a zirconium dioxide high-density capacitor. The high-density capacitor achieved by using a dielectric layer with a high dielectric constant can achieve a unit capacitance density of 1.8pf/ ^um2 . The use of the above-mentioned high-density capacitor can enable the solution to have the advantages of high capacitance per unit area, save space and meet the capacitance requirements of the chip. In addition, it should be noted that the above-mentioned high-density capacitor can be integrated into the memory chip in the memory chip manufacturing process through three-dimensional folding technology. At present, there are no implementation conditions to integrate the above-mentioned high-density capacitor into the logic chip in the manufacturing process of the logic chip, and provide it to the memory chip through the logic chip.

It should be noted that, since the memory chip borrows the capacitor to provide it to the logic chip, the memory chip and the logic chip need to meet certain position and connection conditions to ensure that the memory chip borrows the capacitor and the logic chip does not generate an excessively high resistance value. In other words, the connection between the borrowed capacitor and the functional circuit requires that the resistance between them is very small. Based on the above problem, the embodiment of the present application also provides the following solutions:

Exemplarily, the above-mentioned storage chip borrowing capacitor is set close to the power-consuming components of the functional circuit of the logic chip through 3D-IC three-dimensional integrated circuit technology. It should be noted that 3D-IC technology is a technology that does not require the chip to be punched through, that is, the pins of the capacitor of a certain metal layer in the storage chip can be connected to the functional circuit in the logic chip, such as Hyper-bonding technology. By using 3D-IC technology, the vertical connection between the storage chip borrowing capacitor and the logic chip functional circuit can be achieved, which minimizes the resistance value between the storage chip borrowing capacitor and the logic chip functional circuit, so that the storage chip borrowing capacitor of the above-mentioned storage chip can be directly provided to any functional circuit inside the logic chip for use.

According to some embodiments, the above-mentioned storage chip borrowing capacitor is one or more than two, and according to the positional relationship between the storage chip and the logic chip and the requirements of the logic chip functional circuit, several on-chip capacitors in the storage chip can be selected as the storage chip borrowing capacitors. For example, after the storage chip and the logic chip are connected by 3D-IC process technology, there are two on-chip capacitors in the storage chip on-chip capacitors corresponding to the position of the logic chip functional circuit, then the above-mentioned two on-chip capacitors can be used as storage chip borrowing capacitors, connected to the above-mentioned logic chip functional circuit, to provide the above-mentioned logic chip functional circuit for use. Alternatively, although the storage chip and the logic chip are connected by 3D-IC process technology, there are two on-chip capacitors in the storage chip on-chip capacitors corresponding to the position of the logic chip functional circuit, but the above-mentioned logic chip functional circuit only needs the capacitance of one of the on-chip capacitors to meet the functional requirements, then the capacitor closer to the power-consuming components of the above-mentioned logic chip functional circuit can be selected as the storage chip borrowing capacitor, connected to the above-mentioned logic chip functional circuit, to provide the above-mentioned logic chip functional circuit for use.

The following describes the logic chip capacitor circuit of the embodiment of the present application in some specific functional circuit scenarios through Figures 2 to 4.

As shown in FIG2 , the logic chip functional circuit unit can be a high power consumption functional module in the logic chip. The capacitors C1 and C2 on the memory chip can be connected to the vicinity of the logic chip functional circuit unit on the surface of the logic chip through 3D-IC technology to provide the logic chip functional circuit unit with a capacitance that meets the requirements, thereby improving the power signal response of the logic chip functional circuit unit and improving the instantaneous voltage drop of the circuit. Among them, the original connection relationship of the pins of the capacitors C1 and C2 in the memory chip remains unchanged, and can still provide the corresponding capacitor function for the memory chip.

In some examples, the logic chip functional circuit may be a linear voltage regulator circuit, and the storage chip borrowing capacitor is set at the voltage output end of the linear voltage regulator circuit. As shown in FIG3 , the logic chip functional circuit is a linear voltage regulator circuit. The current linear voltage regulator circuit uses CMOS gate capacitors to provide capacitance functions. However, since the capacitance per unit area of CMOS gate capacitors is relatively low, the storage chip borrowing capacitor provided in this embodiment can be used to replace it to meet the function of the linear voltage regulator circuit. In the linear voltage regulator circuit, when the load current on one side of the output voltage changes, the gate voltage vgate is adjusted by comparing the output voltage and the output voltage fed back to the input end of the operational amplifier, so that the output voltage remains stable at the level on the input voltage side. Among them, Bleeder nmos is used to maintain the static current of the branch. The linear voltage regulator circuit forms a negative feedback circuit loop. The condition for the stability of the negative feedback circuit is that when the gain drops to 1 (unit gain), the phase shift is less than 180 degrees. The stability of the circuit loop is related to the position of the poles P1 (main pole) and P2. The design of the linear voltage regulator circuit usually places P1 at the output end, which can reduce the ripple of the input voltage while maintaining the stability of the loop and improve the power supply rejection characteristics of the system. According to the formula P1=1/(R1×C11), it can be seen that the larger the C11, the smaller the P1, and the better the voltage stabilization effect of the linear voltage regulator circuit. Among them, R1 and C11 are the small signal resistor and capacitor on the output voltage side, respectively. Referring to FIG3, by replacing the capacitor C11 in the original linear voltage regulator circuit with the capacitor C3 of the storage chip, the voltage stabilization effect of the above-mentioned linear voltage regulator circuit can be improved.

In some examples, the above-mentioned logic chip functional circuit can be a charge pump circuit, and the above-mentioned storage chip borrowed capacitor is the bootstrap capacitor of the above-mentioned charge pump circuit, wherein the bootstrap capacitor in the charge pump circuit can utilize the characteristic that the voltage across the capacitor cannot change suddenly, and the level of the capacitor end is switched by the switch formed by CMOS to achieve the purpose of boosting. As shown in Figure 4, the above-mentioned logic chip functional circuit is a charge pump circuit, and the structure is bilaterally symmetrical. As the clock changes, the charge is respectively transferred to the vpp node and the vdd1 node, and repeated. In each clock cycle T, there are 2 charge transfer processes. The output current of the charge pump circuit can be calculated as I=2×C×(2×vdd1-vpp)/T. Therefore, it can be seen that if a higher current output capacity is required, the capacitance value needs to be increased. Referring to Figure 4, by replacing the bootstrap capacitor in the original linear voltage regulator circuit with the storage chip borrowed capacitors C4 and C5, the current output capacity of the above-mentioned charge pump circuit can be improved.

According to some embodiments, the logic chip functional circuit may include a switched capacitor circuit, and the memory chip borrowed capacitor is used in the switched capacitor circuit. Exemplarily, the switched capacitor circuit may be a switched capacitor filter circuit or a switched capacitor analog-to-digital conversion circuit, which is not limited here. The memory chip borrowed capacitor may be used as the capacitor of the switched capacitor circuit to meet the circuit function requirements.

It should be noted that the above logic chip functional circuit is only used as a specific functional circuit example to illustrate that the logic chip of the embodiment of the present invention provides charge. Other functional circuits in the logic chip that require capacitor functions can also improve the functions of the circuit and chip through the above logic chip capacitor circuit, which is not limited here.

The logic chip capacitor circuit according to the embodiment of the present invention is described in detail above in conjunction with FIG. 1 to FIG. 4 . The logic chip according to the embodiment of the present invention will be described in detail below in conjunction with FIG. 5 .

FIG5 is a schematic structural block diagram of a logic chip provided by an embodiment of the present invention. As shown in FIG5 , a logic chip 500 may include:

The above-mentioned logic chip capacitor circuit 510.

The storage chip borrowing capacitor may be arranged close to the power-consuming components of the logic chip functional circuit to provide charge to the power-consuming components, wherein the storage chip borrowing capacitor is also used to provide charge to the storage chip.

In some examples, the borrowed capacitor of the memory chip may be an on-chip capacitor of the memory chip. When certain conditions are met, the on-chip capacitor in the memory chip may be borrowed to the logic chip and used as the capacitor of the logic chip. That is to say, in this scheme, the borrowed capacitor of the chip is provided by the memory chip to the logic chip for use when the logic chip and the memory chip meet certain position and connection conditions. Of course, in some examples, the memory chip itself may also use the borrowed capacitor thereon, that is, the borrowed capacitor is used by the memory chip and the logic chip.

In some examples, the storage chip borrowing capacitor can be arranged close to the power-consuming element of the logic chip functional circuit, and the pins of the storage chip borrowing capacitor can be arranged around the power-consuming element of the logic chip functional circuit, that is, the functional circuit module or the power-consuming element in the module is physically close to the surface of the logic chip. It can also be a connection between the pins of the element, that is, the pins of the storage chip borrowing capacitor are connected to the circuit of the corresponding logic chip functional circuit, which plays the role of providing charge to the power-consuming element in the logic chip functional circuit so that the logic chip functional circuit can work normally.

Accordingly, the above-mentioned logic chip provided by the embodiment of the present invention includes the above-mentioned logic chip capacitor circuit, and the above-mentioned logic chip capacitor circuit includes: a logic chip functional circuit and a storage chip borrowing capacitor, and the above-mentioned storage chip borrowing capacitor is arranged on the logic chip to provide charge for the power-consuming components of the above-mentioned logic chip functional circuit. Since the logic chip uses the capacitor in the storage chip as a borrowing capacitor to provide charge for the power-consuming components of the logic chip itself. The problem of limited capacitance per unit area of on-chip capacitors is solved very well, while saving the cost of original parts and improving the response of power supply signals and the functional realization of other functional circuits. In addition, since the on-chip capacitor corresponding to the functional circuit to be provided with charge in the logic chip is used in the storage chip, the problem of high cost and complex structure caused by the need to add external capacitors to increase the capacitance of the on-chip capacitor of the logic chip is avoided.

According to some embodiments, as shown in FIG6 , the present application embodiment further provides an electronic device 700, which may include:

The logic chip 710 and the memory chip 720 provided with the memory chip borrowing capacitor are connected to each other.

Accordingly, the electronic device provided by the embodiment of the present invention includes the above-mentioned logic chip, and the capacitor circuit of the above-mentioned logic chip includes: a logic chip functional circuit and a storage chip borrowing capacitor, and the above-mentioned storage chip borrowing capacitor is arranged on the above-mentioned logic chip, and is used to provide charge for the power-consuming components of the above-mentioned logic chip functional circuit. Since the logic chip uses the capacitor in the memory chip as a borrowing capacitor to provide charge for the power-consuming components of the logic chip itself. The problem of limited capacitance per unit area of on-chip capacitors is solved very well, while saving the cost of components and improving the response of power supply signals and the functional realization of other functional circuits. In addition, since the on-chip capacitor corresponding to the functional circuit to be provided with charge in the logic chip is used, the problem of high cost and complex structure caused by the need to add external capacitors to increase the capacitance of the on-chip capacitors of the logic chip is avoided.

According to some embodiments, as shown in FIG. 7 , an embodiment of the present application further provides an electronic device, which may include a logic chip 610 and a memory chip 620 .

The logic chip 610 and the memory chip 620 may be connected via 3D-IC three-dimensional integrated circuit technology, wherein a memory chip borrowing capacitor for providing charge to the power-consuming element is disposed at corresponding positions of the logic chip and the power-consuming element.

By using 3D-IC process technology, the memory chip borrowing capacitor and the logic chip functional circuit can be vertically connected, minimizing the resistance value between the memory chip borrowing capacitor and the logic chip functional circuit, so that the memory chip borrowing capacitor of the above-mentioned memory chip can be directly provided to any functional circuit inside the logic chip.

The storage chip borrowing capacitor may be arranged close to the power-consuming components of the logic chip functional circuit to provide charge to the power-consuming components, wherein the storage chip borrowing capacitor is also used to provide charge to the storage chip.

In some examples, the above-mentioned storage chip borrowing capacitor can be an on-chip capacitor of the storage chip, for example, it can be an on-chip capacitor in the storage chip. When certain conditions are met, the on-chip capacitor in the above-mentioned storage chip can be set in the above-mentioned logic chip and used as the capacitor of the above-mentioned logic chip. That is to say, in this scheme, the above-mentioned chip borrowing capacitor is provided by the above-mentioned storage chip to the logic chip for use when the above-mentioned logic chip and the above-mentioned storage chip meet certain position and connection conditions. In addition, in order to achieve the utilization efficiency of the capacitor, the above-mentioned chip borrowing capacitor is when the above-mentioned logic chip and the above-mentioned storage chip meet certain position and connection conditions, and can also be shared by the above-mentioned storage chip and the logic chip.

In some examples, the storage chip borrowing capacitor can be arranged close to the power-consuming element of the logic chip functional circuit, and the pins of the storage chip borrowing capacitor can be arranged around the power-consuming element of the logic chip functional circuit, that is, the functional circuit module or the power-consuming element in the module is physically close to the surface of the logic chip. It can also be a connection between the pins of the element, that is, the pins of the storage chip borrowing capacitor are connected to the circuit of the corresponding logic chip functional circuit, which plays the role of providing charge for the power-consuming element in the logic chip functional circuit so that the logic chip functional circuit can work normally.

In addition, it should be noted that, whether it is the functional circuit module or the power-consuming element in the module that is physically close to the surface of the logic chip, or the pin of the memory chip borrowing capacitor is connected to the circuit of the corresponding logic chip functional circuit, the chip borrowing capacitor is borrowed by the memory chip to the logic chip when the logic chip and the memory chip meet certain position and connection conditions. In addition, in order to achieve the utilization efficiency of the capacitor, the chip borrowing capacitor is shared by the memory chip and the logic chip when the logic chip Logicarea and the memory chip Memoryarea meet certain position and connection conditions. Specifically, the above scheme needs to meet the requirement that the pin of the chip borrowing capacitor needs to be connected to the logic chip and the memory chip at the same time.

In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and implementation modes. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims (10)

1. A 3D logic chip capacitive circuit, comprising: logic chip functional circuits and memory chips borrow capacitors,

The storage chip is arranged on the logic chip by a capacitor and is used for providing charges for power consumption elements of the logic chip functional circuit;

The memory chip borrowing capacitor is vertically connected with the logic chip functional circuit, the memory chip borrowing capacitor is arranged close to the power consumption element, and the memory chip borrowing capacitor is arranged at a corresponding position of the power consumption element of the logic chip;

the memory chip borrowing capacitance is an on-chip capacitance of the memory chip.

2. The logic chip capacitor circuit of claim 1, wherein the memory chip borrows a capacitor to be a high density capacitor provided with a high dielectric constant dielectric layer.

3. The logic chip capacitance circuit according to claim 1 or 2, wherein,

The memory chip is arranged close to the power consumption element of the logic chip functional circuit by a 3D-IC three-dimensional integrated circuit technology through a capacitor.

4. The logic chip capacitance circuit according to claim 3,

The memory chip borrows one or more than two capacitors.

5. The logic chip capacitance circuit according to claim 3,

The logic chip functional circuit comprises a switch capacitor circuit, and the memory chip is used for the switch capacitor circuit by a capacitor.

6. The logic chip capacitance circuit according to claim 3,

The logic chip functional circuit comprises a linear voltage stabilizing circuit, and the memory chip is arranged at the voltage output end of the linear voltage stabilizing circuit by means of a capacitor.

7. The logic chip capacitance circuit according to claim 3,

The logic chip functional circuit comprises a charge pump circuit, and the storage chip borrows a capacitor as a bootstrap capacitor of the charge pump circuit.

8. A logic chip, characterized in that: a logic chip capacitance circuit comprising any one of claims 1 to 7.

9. An electronic device, characterized in that: a memory chip comprising the logic chip of claim 8 and a borrowing capacitor provided with said memory chip, said logic chip being connected to said memory chip.

10. The electronic device of claim 9, wherein the logic chip and the memory chip are connected by 3D-IC three-dimensional integrated circuit technology.